Use codespell to fix lots of typos over frontends.
Manually verified to avoid false-positives.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
/*
- * Handlers for board audio hooks, splitted from bttv-cards
+ * Handlers for board audio hooks, split from bttv-cards
*
* Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@kernel.org>
* This code is placed under the terms of the GNU General Public License
/*
- * Handlers for board audio hooks, splitted from bttv-cards
+ * Handlers for board audio hooks, split from bttv-cards
*
* Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@kernel.org>
* This code is placed under the terms of the GNU General Public License
bttv-cards.c
- this file has configuration informations - card-specific stuff
+ this file has configuration information - card-specific stuff
like the big tvcards array for the most part
Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
.gpiomux = {0x947fff, 0x987fff,0x947fff,0x947fff },
.gpiomute = 0x947fff,
/* tvtuner, radio, external,internal, mute, stereo
- * tuner, Composit, SVid, Composit-on-Svid-adapter */
+ * tuner, Composite, SVid, Composite-on-Svid-adapter */
.muxsel = MUXSEL(2, 3, 0, 1),
.tuner_type = TUNER_MT2032,
.tuner_addr = ADDR_UNSET,
.gpiomux = {0x947fff, 0x987fff,0x947fff,0x947fff },
.gpiomute = 0x947fff,
/* tvtuner, radio, external,internal, mute, stereo
- * tuner, Composit, SVid, Composit-on-Svid-adapter */
+ * tuner, Composite, SVid, Composite-on-Svid-adapter */
.muxsel = MUXSEL(2, 3, 0, 1),
.tuner_type = TUNER_MT2032,
.tuner_addr = ADDR_UNSET,
bttv_I2CWrite(btv,0x5E,0,0x80,1);
/* Initialise 12C508 PIC */
- /* The I2CWrite and I2CRead commmands are actually to the
+ /* The I2CWrite and I2CRead commands are actually to the
* same chips - but the R/W bit is included in the address
* argument so the numbers are different */
/* ----------------------------------------------------------------------- */
/*
* The PCI-8604PW contains a CPLD, probably an ispMACH 4A, that filters
- * the PCI REQ signals comming from the four BT878 chips. After power
+ * the PCI REQ signals coming from the four BT878 chips. After power
* up, the CPLD does not forward requests to the bus, which prevents
* the BT878 from fetching RISC instructions from memory. While the
* CPLD is connected to most of the GPIOs of PCI device 0xD, only
gpio_bits(0x07f, muxgpio[input]);
- /* reset all conections */
+ /* reset all connections */
gpio_bits(0x200,0x200);
mdelay(1);
gpio_bits(0x200,0x000);
f->fmt.pix.field = field;
- /* update our state informations */
+ /* update our state information */
fh->fmt = fmt;
fh->cap.field = f->fmt.pix.field;
fh->cap.last = V4L2_FIELD_NONE;
V4L2 apps we now reset the cropping parameters as seen through
this fh, which is to say VIDIOC_G_SELECTION and scaling limit checks
will use btv->crop[0], the default cropping parameters for the
- current video standard, and VIDIOC_S_FMT will not implicitely
+ current video standard, and VIDIOC_S_FMT will not implicitly
change the cropping parameters until VIDIOC_S_SELECTION has been
called. */
fh->do_crop = !reset_crop; /* module parameter */
*(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
offset+=bpl;
} else {
- /* scanline needs to be splitted */
+ /* scanline needs to be split */
todo = bpl;
*(rp++)=cpu_to_le32(BT848_RISC_WRITE|BT848_RISC_SOL|
(sg_dma_len(sg)-offset));
extern void bttv_init_card2(struct bttv *btv);
extern void bttv_init_tuner(struct bttv *btv);
-/* card-specific funtions */
+/* card-specific functions */
extern void tea5757_set_freq(struct bttv *btv, unsigned short freq);
extern u32 bttv_tda9880_setnorm(struct bttv *btv, u32 gpiobits);
static int dst_tone_power_cmd(struct dst_state *state)
{
- u8 paket[8] = { 0x00, 0x09, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00 };
+ u8 packet[8] = { 0x00, 0x09, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00 };
if (state->dst_type != DST_TYPE_IS_SAT)
return -EOPNOTSUPP;
- paket[4] = state->tx_tuna[4];
- paket[2] = state->tx_tuna[2];
- paket[3] = state->tx_tuna[3];
- paket[7] = dst_check_sum (paket, 7);
- return dst_command(state, paket, 8);
+ packet[4] = state->tx_tuna[4];
+ packet[2] = state->tx_tuna[2];
+ packet[3] = state->tx_tuna[3];
+ packet[7] = dst_check_sum (packet, 7);
+ return dst_command(state, packet, 8);
}
static int dst_get_tuna(struct dst_state *state)
static int dst_set_diseqc(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
{
struct dst_state *state = fe->demodulator_priv;
- u8 paket[8] = { 0x00, 0x08, 0x04, 0xe0, 0x10, 0x38, 0xf0, 0xec };
+ u8 packet[8] = { 0x00, 0x08, 0x04, 0xe0, 0x10, 0x38, 0xf0, 0xec };
if (state->dst_type != DST_TYPE_IS_SAT)
return -EOPNOTSUPP;
if (cmd->msg_len > 0 && cmd->msg_len < 5)
- memcpy(&paket[3], cmd->msg, cmd->msg_len);
+ memcpy(&packet[3], cmd->msg, cmd->msg_len);
else if (cmd->msg_len == 5 && state->dst_hw_cap & DST_TYPE_HAS_DISEQC5)
- memcpy(&paket[2], cmd->msg, cmd->msg_len);
+ memcpy(&packet[2], cmd->msg, cmd->msg_len);
else
return -EINVAL;
- paket[7] = dst_check_sum(&paket[0], 7);
- return dst_command(state, paket, 8);
+ packet[7] = dst_check_sum(&packet[0], 7);
+ return dst_command(state, packet, 8);
}
static int dst_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
}
spin_unlock_irqrestore(&s->irqlock, flags);
- /* Wait 100 milisecond for DMA to finish, abort on timeout. */
+ /* Wait 100 millisecond for DMA to finish, abort on timeout. */
if (!wait_event_timeout(s->q.done_wq, is_dma_done(s),
msecs_to_jiffies(timeout_msec))) {
omni_sg_dma_abort_channel(s);
u32 active_hi_mask; /* GPIO outputs that reset i2c chips when high */
int msecs_asserted; /* time period reset must remain asserted */
int msecs_recovery; /* time after deassert for chips to be ready */
- u32 ir_reset_mask; /* GPIO to reset the Zilog Z8F0811 IR contoller */
+ u32 ir_reset_mask; /* GPIO to reset the Zilog Z8F0811 IR controller */
};
struct cx18_gpio_audio_input { /* select tuner/line in input */
/*
* Due to
*
- * 1. an absence of information on how to prgram the MT352
- * 2. the Linux mt352 module pushing MT352 initialzation off onto us here
+ * 1. an absence of information on how to program the MT352
+ * 2. the Linux mt352 module pushing MT352 initialization off onto us here
*
* We have to use an init sequence that *you* must extract from the Windows
* driver (yuanrap.sys) and which we load as a firmware.
tot_written += rc;
if (stop || /* Forced stopping point for VBI insertion */
- tot_written >= ucount || /* Reader request statisfied */
+ tot_written >= ucount || /* Reader request satisfied */
mdl->curr_buf->readpos < mdl->curr_buf->bytesused ||
mdl->readpos >= mdl->bytesused) /* MDL buffers drained */
break;
/*
* Readback and retry of MMIO access for reliability:
* The concept was suggested by Steve Toth <stoth@linuxtv.org>.
- * The implmentation is the fault of Andy Walls <awalls@md.metrocast.net>.
+ * The impl
ementation is the fault of Andy Walls <awalls@md.metrocast.net>.
*
* *write* functions are implied to retry the mmio unless suffixed with _noretry
* *read* functions never retry the mmio (it never helps to do so)
/*
* Raster Reference/Protection (RP) bytes, used in Start/End Active
* Video codes emitted from the digitzer in VIP 1.x mode, that flag the start
- * of VBI sample or VBI ancillary data regions in the digitial ratser line.
+ * of VBI sample or VBI ancillary data regions in the digital ratser line.
*
* Task FieldEven VerticalBlank HorizontalBlank 0 0 0 0
*/
/* Error in I2C data xfer (but I2C device is present) */
#define CXERR_I2CDEV_XFERERR 0x000011
-/* Chanel changing component not ready */
+/* Channel changing component not ready */
#define CXERR_CHANNELNOTREADY 0x000012
/* PPU (Presensation/Decoder) mail box is corrupted */
pr_info("%s: registered device %s [mpeg]\n",
dev->name, video_device_node_name(dev->v4l_device));
- /* ST: Configure the encoder paramaters, but don't begin
+ /* ST: Configure the encoder parameters, but don't begin
* encoding, this resolves an issue where the first time the
* encoder is started video can be choppy.
*/
MODULE_PARM_DESC(audio_debug, "enable debug messages [analog audio]");
/****************************************************************************
- Board specific funtions
+ Board specific functions
****************************************************************************/
/* Constants taken from cx88-reg.h */
* and report errors if we think we're tampering with a GPIo that might
* be assigned to the encoder (and used for the host bus).
*
- * GPIO 2 thru 0 - On the cx23885 bridge
- * GPIO 18 thru 3 - On the cx23417 host bus interface
- * GPIO 23 thru 19 - On the cx25840 a/v core
+ * GPIO 2 through 0 - On the cx23885 bridge
+ * GPIO 18 through 3 - On the cx23417 host bus interface
+ * GPIO 23 through 19 - On the cx25840 a/v core
*/
void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
{
struct i2c_client i2c_client;
u32 i2c_rc;
- /* 885 registers used for raw addess */
+ /* 885 registers used for raw address */
u32 i2c_period;
u32 reg_ctrl;
u32 reg_stat;
ror = stats & STATS_ROR; /* Rx FIFO Over Run */
tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
- rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
+ rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */
rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
}
if (v) {
- /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
+ /* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */
cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
*handled = true;
MODULE_PARM_DESC(debug, "enable debug messages");
/****************************************************************************
- Module specific funtions
+ Module specific functions
****************************************************************************/
/* Constants taken from cx88-reg.h */
#define AUD_INT_DN_RISCI1 (1 << 0)
#define AUDIO_CMDS_SIZE 80 /* AUDIO CMDS size in bytes */
#define MBIF_CMDS_SIZE 80 /* MBIF CMDS size in bytes */
-/* #define RX_SRAM_POOL_START_SIZE = 0; // Start of useable RX SRAM for buffers */
+/* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */
#define VID_IQ_SIZE 64 /* VID instruction queue size in bytes */
#define MBIF_IQ_SIZE 64
#define AUDIO_IQ_SIZE 64 /* AUD instruction queue size in bytes */
struct i2c_client i2c_client;
u32 i2c_rc;
- /* cx25821 registers used for raw addess */
+ /* cx25821 registers used for raw address */
u32 i2c_period;
u32 reg_ctrl;
u32 reg_stat;
msgs[i].buf[byte] = rc;
}
} else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) {
- /* prepaired for cx24116 firmware */
+ /* prepared for cx24116 firmware */
/* Write in small blocks */
len = msgs[i].len - 1;
k = 1;
*/
/*
- * shift for keeping value range suitable for 32-bit integer arithmetics
+ * shift for keeping value range suitable for 32-bit integer arithmetic
*/
#define LIMIT_SHIFT 8
/*
* Inherit the -EFAULT from rc's
* initialization, but allow it to be
- * overriden by uv_pages above if it was an
+ * overridden by uv_pages above if it was an
* actual errno.
*/
} else {
unsigned long sequence; /* sequence number */
};
-/* size of kfifos containings buffer indices */
+/* size of kfifos containing buffer indices */
#define MEYE_QUEUE_SIZE MEYE_MAX_BUFNBRS
/* Motion Eye device structure */
/* Point to first buffer entry */
struct SBufferHeader *Cur = pRingBuffer->Head;
int i;
- /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
+ /* Loop through all buffer and set Buffer 2 pointers to TSIdlebuffer */
for (i = 0; i < n; i++) {
Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
Cur->scList2 = pIdleBuffer->Head->scList1;
u32 addr_l; /* bus address of target data buffer */
u32 addr_h;
u32 size;
- u32 next_l; /* bus adddress of the next xfer_desc */
+ u32 next_l; /* bus address of the next xfer_desc */
u32 next_h;
};
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7133,
.subvendor = 0x5168,
- .subdevice = 0x3502, /* whats the difference to 0x3306 ?*/
+ .subdevice = 0x3502, /* what's the difference to 0x3306 ?*/
.driver_data = SAA7134_BOARD_FLYDVBT_HYBRID_CARDBUS,
},{
.vendor = PCI_VENDOR_ID_PHILIPS,
/* check if the saa7740 (aka 'sound arena module') is present
on the mxb. if so, we must initialize it. due to lack of
- informations about the saa7740, the values were reverse
+ information about the saa7740, the values were reverse
engineered. */
msg.addr = 0x1b;
msg.flags = 0;
input_port_selection[input].hps_sync);
/* prepare switching of tea6415c and saa7111a;
- have a look at the 'background'-file for further informations */
+ have a look at the 'background'-file for further information */
switch (input) {
case TUNER:
i = SAA7115_COMPOSITE0;
if (port->type == SAA7164_MPEG_ENCODER) {
/* Pick any analog standard to init the diff.
* we'll come back during encoder_init'
- * and set the correct standard if requried.
+ * and set the correct standard if required.
*/
std = V4L2_STD_NTSC;
} else
.subvendor = 0x0070,
.subdevice = 0xf111,
.card = SAA7164_BOARD_HAUPPAUGE_HVR2255,
- /* Prototype card left here for documenation purposes.
+ /* Prototype card left here for documentation purposes.
.card = SAA7164_BOARD_HAUPPAUGE_HVR2255proto,
*/
}, {
* access to I2C. Instead we have to communicate through the device f/w for
* register access to 'processing units'. Each unit has a unique
* id, regardless of how the physical implementation occurs across
- * the three physical i2c busses. The being said if we want leverge of
+ * the three physical i2c buses. The being said if we want leverge of
* the existing kernel drivers for tuners and demods we have to 'speak i2c',
* to this bridge implements 3 virtual i2c buses. This is a helper function
* for those.
}
- /* Only report errors if we've been through this function atleast
+ /* Only report errors if we've been through this function at least
* once already and the cached cc values are primed. First time through
* always generates errors.
*/
dev->bmmio = (u8 __iomem *)dev->lmmio;
dev->bmmio2 = (u8 __iomem *)dev->lmmio2;
- /* Inerrupt and ack register locations offset of bmmio */
+ /* Interrupt and ack register locations offset of bmmio */
dev->int_status = 0x183000 + 0xf80;
dev->int_ack = 0x183000 + 0xf90;
(version & 0x0000001f),
(version & 0xffff0000) >> 16);
- /* Load the firmwware from the disk if required */
+ /* Load the firmware from the disk if required */
if (version == 0) {
printk(KERN_INFO "%s() Waiting for firmware upload (%s)\n",
solo_reg_write(solo_dev, SOLO_VI_CH_FORMAT,
SOLO_VI_FD_SEL_MASK(0) | SOLO_VI_PROG_MASK(0));
- /* On 6110, initialize mozaic darkness stength */
+ /* On 6110, initialize mozaic darkness strength */
if (solo_dev->type == SOLO_DEV_6010)
solo_reg_write(solo_dev, SOLO_VI_FMT_CFG, 0);
else
}
/* First 8k is motion flag (512 bytes * 16). Following that is an 8k+8k
- * threshold and working table for each channel. Atleast that's what the
+ * threshold and working table for each channel. At least that's what the
* spec says. However, this code (taken from rdk) has some mystery 8k
* block right after the flag area, before the first thresh table. */
static void solo_motion_config(struct solo_dev *solo_dev)
* @std: video standard (e.g. PAL/NTSC)
* @input: input line for video signal ( 0 or 1 )
* @disabled: Device is in power down state
- * @slock: for excluse acces of registers
+ * @slock: for excluse access of registers
* @vb_vidq: queue maintained by videobuf2 layer
* @buffer_list: list of buffer in use
* @sequence: sequence number of acquired buffer
* (n in defined in the RPS_THRESH1 counter threshold)
* I think HS is raised high on the beginning of the n-th line
* and remains high until this n-th line that triggered
- * it is completely received. When the receiption of n-th line
+ * it is completely received. When the reception of n-th line
* ends, HS is lowered.
*
* To transmit data over DMA, 7146 needs changing state at
* hardware debug note: a working budget card (including budget patch)
* with vpeirq() interrupt setup in mode "0x90" (every 64K) will
* generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes
- * and that means 3*25=75 Hz of interrupt freqency, as seen by
+ * and that means 3*25=75 Hz of interrupt frequency, as seen by
* watch cat /proc/interrupts
*
* If this frequency is 3x lower (and data received in the DMA
* this means VSYNC line is not connected in the hardware.
* (check soldering pcb and pins)
* The same behaviour of missing VSYNC can be duplicated on budget
- * cards, by seting DD1_INIT trigger mode 7 in 3rd nibble.
+ * cards, by setting DD1_INIT trigger mode 7 in 3rd nibble.
*/
static int av7110_attach(struct saa7146_dev* dev,
struct saa7146_pci_extension_data *pci_ext)
/*
* buffer_prepare
*
- * Set the ancilliary information into the buffer structure. This
+ * Set the ancillary information into the buffer structure. This
* includes generating the necessary risc program if it hasn't already
* been done for the current buffer format.
* The structure fh contains the details of the format requested by the
projects / platform / kernel / linux-starfive.git / commitdiff