PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core

Fix legacy IRQ generation for RK3399 PCIe endpoint core according to
the technical reference manual (TRM). Assert and deassert legacy
interrupt (INTx) through the legacy interrupt control register
("PCIE_CLIENT_LEGACY_INT_CTRL") instead of manually generating a PCIe
message. The generation of the legacy interrupt was tested and validated
with the PCIe endpoint test driver.

Link: https://lore.kernel.org/r/20230418074700.1083505-8-rick.wertenbroek@gmail.com
Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Cc: stable@vger.kernel.org

diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index d00baed..d6d4b0f 100644 (file)
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -337,48 +337,25 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
 }
 
 static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
-                                        u8 intx, bool is_asserted)
+                                        u8 intx, bool do_assert)
 {
        struct rockchip_pcie *rockchip = &ep->rockchip;
-       u32 r = ep->max_regions - 1;
-       u32 offset;
-       u32 status;
-       u8 msg_code;
-
-       if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR ||
-                    ep->irq_pci_fn != fn)) {
-               rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
-                                            AXI_WRAPPER_NOR_MSG,
-                                            ep->irq_phys_addr, 0, 0);
-               ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR;
-               ep->irq_pci_fn = fn;
-       }
 
        intx &= 3;
-       if (is_asserted) {
+
+       if (do_assert) {
                ep->irq_pending |= BIT(intx);
-               msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx;
+               rockchip_pcie_write(rockchip,
+                                   PCIE_CLIENT_INT_IN_ASSERT |
+                                   PCIE_CLIENT_INT_PEND_ST_PEND,
+                                   PCIE_CLIENT_LEGACY_INT_CTRL);
        } else {
                ep->irq_pending &= ~BIT(intx);
-               msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx;
+               rockchip_pcie_write(rockchip,
+                                   PCIE_CLIENT_INT_IN_DEASSERT |
+                                   PCIE_CLIENT_INT_PEND_ST_NORMAL,
+                                   PCIE_CLIENT_LEGACY_INT_CTRL);
        }
-
-       status = rockchip_pcie_read(rockchip,
-                                   ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
-                                   ROCKCHIP_PCIE_EP_CMD_STATUS);
-       status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
-
-       if ((status != 0) ^ (ep->irq_pending != 0)) {
-               status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
-               rockchip_pcie_write(rockchip, status,
-                                   ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
-                                   ROCKCHIP_PCIE_EP_CMD_STATUS);
-       }
-
-       offset =
-          ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) |
-          ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA;
-       writel(0, ep->irq_cpu_addr + offset);
 }
 
 static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,

diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index f3a5ff1..ffc68a3 100644 (file)
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -38,6 +38,11 @@
 #define   PCIE_CLIENT_MODE_EP            HIWORD_UPDATE(0x0040, 0)
 #define   PCIE_CLIENT_GEN_SEL_1                  HIWORD_UPDATE(0x0080, 0)
 #define   PCIE_CLIENT_GEN_SEL_2                  HIWORD_UPDATE_BIT(0x0080)
+#define PCIE_CLIENT_LEGACY_INT_CTRL    (PCIE_CLIENT_BASE + 0x0c)
+#define   PCIE_CLIENT_INT_IN_ASSERT            HIWORD_UPDATE_BIT(0x0002)
+#define   PCIE_CLIENT_INT_IN_DEASSERT          HIWORD_UPDATE(0x0002, 0)
+#define   PCIE_CLIENT_INT_PEND_ST_PEND         HIWORD_UPDATE_BIT(0x0001)
+#define   PCIE_CLIENT_INT_PEND_ST_NORMAL       HIWORD_UPDATE(0x0001, 0)
 #define PCIE_CLIENT_SIDE_BAND_STATUS   (PCIE_CLIENT_BASE + 0x20)
 #define   PCIE_CLIENT_PHY_ST                   BIT(12)
 #define PCIE_CLIENT_DEBUG_OUT_0                (PCIE_CLIENT_BASE + 0x3c)
@@ -227,7 +232,6 @@
 #define   ROCKCHIP_PCIE_EP_MSI_CTRL_ME                         BIT(16)
 #define   ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP       BIT(24)
 #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR                                0x1
-#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR           0x3
 #define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
 #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
        (PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)