nand: add clock for mtd nand driver

PD#156734: nand: add clock and disable nand module in dts to
avoid conflit with sd_emmc_c.

Change-Id: I204bbc58960cbed47b1c55194e371cd1c61be12a
Signed-off-by: Liang Yang <liang.yang@amlogic.com>

diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
index 476418b..5de8651 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts
+++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
@@ -296,11 +296,10 @@
                status = "okay";
        };
 
-
        sd_emmc_c: emmc@ffe07000 {
                status = "okay";
                compatible = "amlogic, meson-mmc-g12a";
-               reg = <0x0 0xffe07000 0x0 0x2000>;
+               reg = <0x0 0xffe07000 0x0 0x800>;
                interrupts = <0 191 1>;
                pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
                pinctrl-0 = <&emmc_clk_cmd_pins>;
@@ -394,7 +393,7 @@
        nand: nfc@0 {
                compatible = "amlogic, aml_mtd_nand";
                dev_name = "mtdnand";
-               status = "okay";
+               status = "disabled";
                reg = <0x0 0xFFE07800 0x0 0x200>;
                interrupts = <0 34 1>;
 
@@ -402,8 +401,11 @@
                pinctrl-0 = <&all_nand_pins>;
                pinctrl-1 = <&all_nand_pins>;
                pinctrl-2 = <&nand_cs_pins>;
-               device_id = <0>;
+               clocks = <&clkc CLKID_SD_EMMC_C>,
+                               <&clkc CLKID_SD_EMMC_C_P0_COMP>;
+               clock-names = "core", "clkin";
 
+               device_id = <0>;
                /*fip/tpl configurations, must be same
                 * with uboot if bl_mode was set as 1
                 * bl_mode: 0 compact mode; 1 descrete mode

diff --git a/drivers/amlogic/mtd/aml_hwctrl.h b/drivers/amlogic/mtd/aml_hwctrl.h
index 0f07139..51b5537 100644 (file)
--- a/drivers/amlogic/mtd/aml_hwctrl.h
+++ b/drivers/amlogic/mtd/aml_hwctrl.h
@@ -48,9 +48,11 @@ struct hw_controller {
        u8 chip_num;
        u32 ce_enable[MAX_CHIP_NUM];
        u32 rb_enable[MAX_CHIP_NUM];
+       struct clk *clk[4];
 
        void __iomem *reg_base;
        void __iomem *nand_clk_reg;
+       void __iomem *nand_clk_upper;
        u32 irq;
 #ifndef AML_NAND_UBOOT
        /*dma_addr_t data_dma_addr;*/
@@ -101,6 +103,8 @@ struct hw_controller {
 #define        POC_CONFIG_REG  ((uint32_t *)(0xc1107d54))
 #endif /* AML_NAND_UBOOT */
 
+#define NAND_CLK_CNTL_INNER    (0xff63c000+(0x097 << 2))
+
 #define A0_GP_CFG0     (0xc8100240)
 #define A0_GP_CFG2     (0xc8100248)
 #define SD_EMMC_BASE_C 0xFFE07000

diff --git a/drivers/amlogic/mtd/m3_nand.c b/drivers/amlogic/mtd/m3_nand.c
index f9c7779..3336a35 100644 (file)
--- a/drivers/amlogic/mtd/m3_nand.c
+++ b/drivers/amlogic/mtd/m3_nand.c
@@ -19,6 +19,8 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
 
 #include "aml_mtd.h"
 
@@ -260,6 +262,41 @@ static void m3_nand_select_chip(struct aml_nand_chip *aml_chip, int chipnr)
        controller_select_chip(controller, chipnr);
 }
 
+#define GATE_CLK       0
+#define GATE_CLKIN     1
+static int aml_nfc_clk_init(struct hw_controller *controller)
+{
+       char *clk_name[2] = {"core", "clkin"};
+       int i, ret = 0;
+
+       for (i = 0; i < 2; i++) {
+               controller->clk[i] =
+                       devm_clk_get(controller->device, clk_name[i]);
+               if (IS_ERR(controller->clk[i])) {
+                       dev_err(controller->device,
+                               "failed to get %s\n", clk_name[i]);
+                       return PTR_ERR(controller->clk[i]);
+               }
+       }
+
+       ret = clk_prepare_enable(controller->clk[GATE_CLK]);
+       if (ret) {
+               dev_err(controller->device, "failed to set nand gate\n");
+               return ret;
+       }
+
+       ret = clk_prepare_enable(controller->clk[GATE_CLKIN]);
+       if (ret) {
+               dev_err(controller->device, "failed to enable nand clk\n");
+               goto clk_enbale_error;
+       }
+       return 0;
+
+clk_enbale_error:
+       clk_disable_unprepare(controller->clk[GATE_CLK]);
+       return ret;
+}
+
 void get_sys_clk_rate_mtd(struct hw_controller *controller, int *rate)
 {
        int clk_freq = *rate;
@@ -309,6 +346,8 @@ static void m3_nand_hw_init(struct aml_nand_chip *aml_chip)
 {
        int sys_clk_rate, bus_cycle, bus_timing;
 
+       aml_nfc_clk_init(controller);
+
        if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
                sys_clk_rate = 24;
                bus_cycle  = 4;
@@ -1075,6 +1114,10 @@ int nand_init(struct platform_device *pdev)
        controller->nand_clk_reg = devm_ioremap_nocache(&pdev->dev,
                                        aml_nand_mid_device.nand_clk_ctrl,
                                        sizeof(int));
+       controller->nand_clk_upper = devm_ioremap_nocache(&pdev->dev,
+                                       NAND_CLK_CNTL_INNER,
+                                       sizeof(int));
+
        if (controller->nand_clk_reg == NULL) {
                dev_err(&pdev->dev, "ioremap External Nand Clock IO fail\n");
                return -ENOMEM;