* config/m32c/cond.md: Set condition flags properly throughout.
* config/m32c/minmax.md: Likewise.
* config/m32c/prologue.md: Likewise.
* config/m32c/bitops.md: Likewise.
* config/m32c/muldiv.md: Likewise.
* config/m32c/mov.md: Likewise.
* config/m32c/addsub.md: Likewise.
* config/m32c/m32c.md: Likewise.
* config/m32c/jump.md: Likewise.
* config/m32c/shift.md: Likewise.
* config/m32c/cond.md (cmp<mode>): Call m32c_output_compare to
conditionally output the pattern for this.
* config/m32c/m32c.c (flags_needed_for_conditional): New.
(m32c_compare_redundant): New.
(m32c_output_compare): New.
* config/m32c/m32c-protos.h (m32c_output_compare): New.
* config/m32c/m32c.c (m32c_prepare_shift): Fix logic to clobber
dest, not src. Allow other 4-byte modes.
From-SVN: r112591
+2006-03-31 DJ Delorie <dj@redhat.com>
+
+ * config/m32c/cond.md: Set condition flags properly throughout.
+ * config/m32c/minmax.md: Likewise.
+ * config/m32c/prologue.md: Likewise.
+ * config/m32c/bitops.md: Likewise.
+ * config/m32c/muldiv.md: Likewise.
+ * config/m32c/mov.md: Likewise.
+ * config/m32c/addsub.md: Likewise.
+ * config/m32c/m32c.md: Likewise.
+ * config/m32c/jump.md: Likewise.
+ * config/m32c/shift.md: Likewise.
+
+ * config/m32c/cond.md (cmp<mode>): Call m32c_output_compare to
+ conditionally output the pattern for this.
+ * config/m32c/m32c.c (flags_needed_for_conditional): New.
+ (m32c_compare_redundant): New.
+ (m32c_output_compare): New.
+ * config/m32c/m32c-protos.h (m32c_output_compare): New.
+
+ * config/m32c/m32c.c (m32c_prepare_shift): Fix logic to clobber
+ dest, not src. Allow other 4-byte modes.
+
2006-03-30 Denis Chertykov <denisc@overta.ru>
* doc/md.texi: Refer to avr/constraints.md instead of
stc\t%1,%0
mova\t%D2[%1],%0
add.w\t%2,%0"
- [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,oszc,oszc,oszc,oszc")]
+ [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc")]
)
(define_insn "addpsi3"
add.l\t%2,%0
mova\t%d2[%1],%0
mova\t%D2[%1],%0"
- [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,*,*")]
+ [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")]
)
(define_insn "subqi3"
(neg:SI (match_operand:SI 1 "mra_operand" "0,0")))]
""
"not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0"
- [(set_attr "flags" "oszc,oszc")]
+ [(set_attr "flags" "x")]
)
(define_insn "absqi2"
(match_operand:QI 2 "" "0")))]
"TARGET_A16"
"bset\t%0[%1]"
- [(set_attr "flags" "sz")]
+ [(set_attr "flags" "n")]
)
(define_insn "bset_hi"
(const_int 1))]
"TARGET_A16"
"bset\t%0[%1]"
- [(set_attr "flags" "sz")]
+ [(set_attr "flags" "n")]
)
;;----------------------------------------------------------------------
(const_int 0))]
"TARGET_A16"
"bclr\t%0[%1]"
- [(set_attr "flags" "sz")]
+ [(set_attr "flags" "n")]
)
(define_insn "iorqi3_24"
- [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
- (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
- (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
+ [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
+ (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
+ (match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
"TARGET_A24"
"@
bset\t%B2,%0
- bset\t%B2,%0
or.b\t%x2,%0
or.b\t%x2,%0
or.b\t%x2,%0
or.b\t%x2,%0"
- [(set_attr "flags" "n,n,sz,sz,sz,sz")]
+ [(set_attr "flags" "n,sz,sz,sz,sz")]
)
(define_insn "iorhi3_24"
"@
stzx\t%1,%2,%0
stz\t%1,%0
- stnz\t%2,%0")
+ stnz\t%2,%0"
+ [(set_attr "flags" "n,n,n")]
+)
(define_insn "stzx_24_<mode>"
[(set (match_operand:QHI 0 "mrai_operand" "=RraSd,RraSd,RraSd")
"@
stzx.<bwl>\t%1,%2,%0
stz.<bwl>\t%1,%0
- stnz.<bwl>\t%2,%0")
+ stnz.<bwl>\t%2,%0"
+ [(set_attr "flags" "n,n,n")])
(define_insn_and_split "stzx_reversed"
[(set (match_operand 0 "m32c_r0_operand" "")
(compare (match_operand:QHPSI 0 "mra_operand" "RraSd")
(match_operand:QHPSI 1 "mrai_operand" "RraSdi")))]
""
- "cmp.<bwl>\t%1,%0")
+ "* return m32c_output_compare(insn, operands); "
+ [(set_attr "flags" "oszc")])
(define_insn "b<code>"
[(set (pc)
(pc)))]
""
"j<code>\t%l0"
+ [(set_attr "flags" "n")]
)
;; m32c_conditional_register_usage changes the setcc_gen_code array to
[(set (match_operand:HI 0 "mra_operand" "=RhiSd")
(any_cond:HI (reg:CC FLG_REGNO) (const_int 0)))]
"TARGET_A24"
- "sc<code>\t%0")
+ "sc<code>\t%0"
+ [(set_attr "flags" "n")]
+)
(define_expand "movqicc"
[(set (match_operand:QI 0 "register_operand" "")
;; value. This pattern recovers the sign of the discarded value based
;; on the flags. Operand 0 is set to -1, 0, or 1. This is used for
;; the cmpstr pattern. For optimal code, this should be removed if
-;; followed by a suitable CMP insn, as SCMPU sets the flags correctly
-;; already (see the peephole following). This pattern is 7 bytes and
-;; 5 cycles. If you don't need specific values, a 5/4 pattern can be
-;; made with SCGT and BMLT to set the appropriate bits.
+;; followed by a suitable CMP insn (see the peephole following). This
+;; pattern is 7 bytes and 5 cycles. If you don't need specific
+;; values, a 5/4 pattern can be made with SCGT and BMLT to set the
+;; appropriate bits.
(define_insn "cond_to_int"
[(set (match_operand:HI 0 "mra_qi_operand" "=Rqi")
(const_int -1))))]
"TARGET_A24"
"sceq\t%0\n\tbmgt\t1,%h0\n\tdec.w\t%0"
- [(set_attr "flags" "sz")]
+ [(set_attr "flags" "x")]
)
;; A cond_to_int followed by a compare against zero is essentially a no-op.
; "jmpi.a\t%0"
; no 16 bit jmpi in r8c
"push.b #0 | push.w\t%0 | rts"
+ [(set_attr "flags" "x")]
)
(define_insn "indirect_jump_24"
(match_operand:PSI 0 "register_operand" "Rpi"))]
"TARGET_A24"
"jmpi.a\t%0"
+ [(set_attr "flags" "n")]
)
(define_expand "indirect_jump"
(label_ref (match_operand 0 "" "")))]
""
"jmp.a\t%l0"
+ [(set_attr "flags" "n")]
)
; No 16 bit indirect calls on r8c/m16c. */
case 1: return TARGET_A16 ? \"push.w %a0 | jsr.a\tm32c_jsri16\" : \"jsri.a\t%a0\";
case 2: return \"jsri.a\t%a0\";
}"
+ [(set_attr "flags" "x")]
)
(define_insn "call_value"
case 1: return TARGET_A16 ? \"push.w %a1 | jsr.a\tm32c_jsri16\" : \"jsri.a\t%a1\";
case 2: return \"jsri.a\t%a1\";
}"
+ [(set_attr "flags" "x,x,x")]
)
int m32c_mode_dependent_address (rtx);
int m32c_modes_tieable_p (MM, MM);
bool m32c_mov_ok (rtx *, MM);
+char * m32c_output_compare (rtx, rtx *);
int m32c_preferred_output_reload_class (rtx, int);
int m32c_preferred_reload_class (rtx, int);
int m32c_prepare_move (rtx *, MM);
else
/* We'll only use it for the shift, no point emitting a move. */
temp = operands[2];
-
- if (TARGET_A16 && mode == SImode)
+ if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
{
/* The m16c has a limit of -16..16 for SI shifts, even when the
shift count is in a register. Since there are so many targets
rtx count;
rtx label, lref, insn;
+ emit_move_insn (operands[0], operands[1]);
+
count = temp;
label = gen_label_rtx ();
lref = gen_rtx_LABEL_REF (VOIDmode, label);
/* This is a left shift. We only need check positive counts. */
emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
count, GEN_INT (16), label));
- emit_insn (func (operands[1], operands[1], GEN_INT (8)));
- emit_insn (func (operands[1], operands[1], GEN_INT (8)));
+ emit_insn (func (operands[0], operands[0], GEN_INT (8)));
+ emit_insn (func (operands[0], operands[0], GEN_INT (8)));
insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
emit_label_after (label, insn);
}
/* This is a right shift. We only need check negative counts. */
emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
count, GEN_INT (-16), label));
- emit_insn (func (operands[1], operands[1], GEN_INT (-8)));
- emit_insn (func (operands[1], operands[1], GEN_INT (-8)));
+ emit_insn (func (operands[0], operands[0], GEN_INT (-8)));
+ emit_insn (func (operands[0], operands[0], GEN_INT (-8)));
insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
emit_label_after (label, insn);
}
-
+ operands[1] = operands[0];
+ emit_insn (func (operands[0], operands[0], count));
+ return 1;
}
operands[2] = temp;
storing a zero, we want an AND mask, so invert it. */
if (INTVAL (operands[3]) == 0)
{
+ /* Storing a zero, use an AND mask */
if (GET_MODE (op0) == HImode)
mask ^= 0xffff;
else
emit_barrier ();
}
+/* Indicate which flags must be properly set for a given conditional. */
+static int
+flags_needed_for_conditional (rtx cond)
+{
+ switch (GET_CODE (cond))
+ {
+ case LE:
+ case GT:
+ return FLAGS_OSZ;
+ case LEU:
+ case GTU:
+ return FLAGS_ZC;
+ case LT:
+ case GE:
+ return FLAGS_OS;
+ case LTU:
+ case GEU:
+ return FLAGS_C;
+ case EQ:
+ case NE:
+ return FLAGS_Z;
+ default:
+ return FLAGS_N;
+ }
+}
+
+#define DEBUG_CMP 0
+
+/* Returns true if a compare insn is redundant because it would only
+ set flags that are already set correctly. */
+static bool
+m32c_compare_redundant (rtx cmp, rtx *operands)
+{
+ int flags_needed;
+ int pflags;
+ rtx prev, pp, next;
+ rtx op0, op1, op2;
+#if DEBUG_CMP
+ int prev_icode, i;
+#endif
+
+ op0 = operands[0];
+ op1 = operands[1];
+ op2 = operands[2];
+
+#if DEBUG_CMP
+ fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
+ debug_rtx(cmp);
+ for (i=0; i<2; i++)
+ {
+ fprintf(stderr, "operands[%d] = ", i);
+ debug_rtx(operands[i]);
+ }
+#endif
+
+ next = next_nonnote_insn (cmp);
+ if (!next || !INSN_P (next))
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "compare not followed by insn\n");
+ debug_rtx(next);
+#endif
+ return false;
+ }
+ if (GET_CODE (PATTERN (next)) == SET
+ && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
+ {
+ next = XEXP (XEXP (PATTERN (next), 1), 0);
+ }
+ else if (GET_CODE (PATTERN (next)) == SET)
+ {
+ /* If this is a conditional, flags_needed will be something
+ other than FLAGS_N, which we test below. */
+ next = XEXP (PATTERN (next), 1);
+ }
+ else
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "compare not followed by conditional\n");
+ debug_rtx(next);
+#endif
+ return false;
+ }
+#if DEBUG_CMP
+ fprintf(stderr, "conditional is: ");
+ debug_rtx(next);
+#endif
+
+ flags_needed = flags_needed_for_conditional (next);
+ if (flags_needed == FLAGS_N)
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "compare not followed by conditional\n");
+ debug_rtx(next);
+#endif
+ return false;
+ }
+
+ /* Compare doesn't set overflow and carry the same way that
+ arithmetic instructions do, so we can't replace those. */
+ if (flags_needed & FLAGS_OC)
+ return false;
+
+ prev = cmp;
+ do {
+ prev = prev_nonnote_insn (prev);
+ if (!prev)
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "No previous insn.\n");
+#endif
+ return false;
+ }
+ if (!INSN_P (prev))
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "Previous insn is a non-insn.\n");
+#endif
+ return false;
+ }
+ pp = PATTERN (prev);
+ if (GET_CODE (pp) != SET)
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "Previous insn is not a SET.\n");
+#endif
+ return false;
+ }
+ pflags = get_attr_flags (prev);
+
+ /* Looking up attributes of previous insns corrupted the recog
+ tables. */
+ INSN_UID (cmp) = -1;
+ recog (PATTERN (cmp), cmp, 0);
+
+ if (pflags == FLAGS_N
+ && reg_mentioned_p (op0, pp))
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "intermediate non-flags insn uses op:\n");
+ debug_rtx(prev);
+#endif
+ return false;
+ }
+ } while (pflags == FLAGS_N);
+#if DEBUG_CMP
+ fprintf(stderr, "previous flag-setting insn:\n");
+ debug_rtx(prev);
+ debug_rtx(pp);
+#endif
+
+ if (GET_CODE (pp) == SET
+ && GET_CODE (XEXP (pp, 0)) == REG
+ && REGNO (XEXP (pp, 0)) == FLG_REGNO
+ && GET_CODE (XEXP (pp, 1)) == COMPARE)
+ {
+ /* Adjacent cbranches must have the same operands to be
+ redundant. */
+ rtx pop0 = XEXP (XEXP (pp, 1), 0);
+ rtx pop1 = XEXP (XEXP (pp, 1), 1);
+#if DEBUG_CMP
+ fprintf(stderr, "adjacent cbranches\n");
+ debug_rtx(pop0);
+ debug_rtx(pop1);
+#endif
+ if (rtx_equal_p (op0, pop0)
+ && rtx_equal_p (op1, pop1))
+ return true;
+#if DEBUG_CMP
+ fprintf(stderr, "prev cmp not same\n");
+#endif
+ return false;
+ }
+
+ /* Else the previous insn must be a SET, with either the source or
+ dest equal to operands[0], and operands[1] must be zero. */
+
+ if (!rtx_equal_p (op1, const0_rtx))
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "operands[1] not const0_rtx\n");
+#endif
+ return false;
+ }
+ if (GET_CODE (pp) != SET)
+ {
+#if DEBUG_CMP
+ fprintf (stderr, "pp not set\n");
+#endif
+ return false;
+ }
+ if (!rtx_equal_p (op0, SET_SRC (pp))
+ && !rtx_equal_p (op0, SET_DEST (pp)))
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "operands[0] not found in set\n");
+#endif
+ return false;
+ }
+
+#if DEBUG_CMP
+ fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
+#endif
+ if ((pflags & flags_needed) == flags_needed)
+ return true;
+
+ return false;
+}
+
+/* Return the pattern for a compare. This will be commented out if
+ the compare is redundant, else a normal pattern is returned. Thus,
+ the assembler output says where the compare would have been. */
+char *
+m32c_output_compare (rtx insn, rtx *operands)
+{
+ static char template[] = ";cmp.b\t%1,%0";
+ /* ^ 5 */
+
+ template[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
+ if (m32c_compare_redundant (insn, operands))
+ {
+#if DEBUG_CMP
+ fprintf(stderr, "cbranch: cmp not needed\n");
+#endif
+ return template;
+ }
+
+#if DEBUG_CMP
+ fprintf(stderr, "cbranch: cmp needed: `%s'\n", template);
+#endif
+ return template + 1;
+}
+
/* The Global `targetm' Variable. */
struct gcc_target targetm = TARGET_INITIALIZER;
(define_insn "nop"
[(const_int 0)]
""
- "nop")
+ "nop"
+ [(set_attr "flags" "n")]
+)
(define_insn "no_insn"
[(const_int 1)]
""
- "")
+ ""
+ [(set_attr "flags" "n")]
+)
(match_operand:QI 2 "mrai_operand" "iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm")))]
"TARGET_A24"
"min.b\t%2,%0"
+ [(set_attr "flags" "n")]
)
(define_insn "sminhi3"
(match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
"TARGET_A24"
"min.w\t%2,%0"
+ [(set_attr "flags" "n")]
)
(define_insn "smaxqi3"
(match_operand:QI 2 "mrai_operand" "iRhlSdRaa,?Rmm,iRhlSdRaa,?Rmm,iRhlSd,?Rmm")))]
"TARGET_A24"
"max.b\t%2,%0"
+ [(set_attr "flags" "n")]
)
(define_insn "smaxhi3"
(match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
"TARGET_A24"
"max.w\t%2,%0"
+ [(set_attr "flags" "n")]
)
pop.w\t%0
pushc\t%1
popc\t%0"
- [(set_attr "flags" "sz,sz,sz,*,*,*,*,*,*")]
+ [(set_attr "flags" "sz,sz,sz,n,n,n,n,n,n")]
)
(define_expand "movhi"
pushc\t%1
popc\t%0
#"
- [(set_attr "flags" "sz,sz,*,*,*,*,*,*")]
+ [(set_attr "flags" "sz,sz,n,n,n,n,n,*")]
)
(match_operand 0 "a_operand" "Raa"))]
""
"push.l\t%0"
+ [(set_attr "flags" "n")]
)
(define_insn "movsi_24"
mov.l\t%1,%0
#
push.l\t%1"
+ [(set_attr "flags" "sz,sz,*,n")]
)
(define_expand "movdi"
(match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
""
"push.b\t%0"
+ [(set_attr "flags" "n")]
)
(define_expand "pushhi"
"@
push.w\t%0
pushc\t%0"
+ [(set_attr "flags" "n,n")]
)
(define_insn "pushhi_24"
(match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
"TARGET_A24"
"push.w\t%0"
+ [(set_attr "flags" "n")]
)
;(define_insn "pushpi"
(match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
"TARGET_A24"
"push.l\t%0"
+ [(set_attr "flags" "n")]
)
(define_expand "pophi"
"@
pop.w\t%0
popc\t%0"
+ [(set_attr "flags" "n,n")]
)
(define_insn "pophi_24"
(mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
"TARGET_A24"
"pop.w\t%0"
+ [(set_attr "flags" "n")]
)
(define_insn "poppsi"
(mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
"TARGET_A24"
"popc\t%0"
+ [(set_attr "flags" "n")]
)
"*
if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
- [(set_attr "flags" "sz")]
+ [(set_attr "flags" "x")]
)
(define_insn "extendpsisi2"
(sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
""
"; expand psi %1 to si %0"
+ [(set_attr "flags" "n")]
)
(define_insn "zero_extendpsisi2"
(zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
""
"; expand psi %1 to si %0"
+ [(set_attr "flags" "n")]
)
(define_insn "zero_extendhipsi2"
(truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
""
"mov.w\t%1,%0"
+ [(set_attr "flags" "sz")]
)
(define_insn "zero_extendhisi2"
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
""
"mov.w\t#0,%H0"
+ [(set_attr "flags" "x")]
)
(define_insn "zero_extendqihi2"
"@
mov.b\t#0,%H0
and.w\t#255,%0"
+ [(set_attr "flags" "x,x")]
)
(define_insn "truncsipsi2_16"
#
ldc\t%1,%0
stc\t%1,%0"
+ [(set_attr "flags" "n,*,n,n")]
)
(define_insn "trunchiqi2"
(truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
""
"; no-op trunc hi %1 to qi %0"
+ [(set_attr "flags" "n")]
)
(define_insn "truncsipsi2_24"
mov.l\t%1,%0
ldc\t%1,%0
stc\t%1,%0"
+ [(set_attr "flags" "n,sz,n,n")]
)
(define_expand "truncsipsi2"
(match_operand 2 "immediate_operand" "i,i")))]
""
"mul.b\t%2,%1"
+ [(set_attr "flags" "o")]
)
; Here is the pattern for registers and such.
(sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
""
"mul.b\t%2,%1"
+ [(set_attr "flags" "o")]
)
; Don't try to sign_extend a const_int. Same for all other multiplies.
(match_operand 2 "immediate_operand" "i,i")))]
""
"mulu.b\t%U2,%1"
+ [(set_attr "flags" "o")]
)
(define_insn "umulqihi3_r"
(zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
""
"mulu.b\t%U2,%1"
+ [(set_attr "flags" "o")]
)
(define_expand "umulqihi3"
(match_operand 2 "immediate_operand" "i,i")))]
""
"mul.w\t%2,%1"
+ [(set_attr "flags" "o")]
)
(define_insn "mulhisi3_r"
(sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
""
"mul.w\t%2,%1"
+ [(set_attr "flags" "o")]
)
(define_expand "mulhisi3"
(match_operand 2 "immediate_operand" "i,i")))]
""
"mulu.w\t%u2,%1"
+ [(set_attr "flags" "o")]
)
(define_insn "umulhisi3_r"
(zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
""
"mulu.w\t%u2,%1"
+ [(set_attr "flags" "o")]
)
(define_expand "umulhisi3"
]
"0"
"div.b\t%2"
+ [(set_attr "flags" "o")]
)
(define_expand "udivmodqi4"
]
"0"
"divu.b\t%2"
+ [(set_attr "flags" "o")]
)
(define_expand "divmodhi4"
]
""
"div.w\t%2"
+ [(set_attr "flags" "o")]
)
(define_expand "udivmodhi4"
]
""
"divu.w\t%2"
+ [(set_attr "flags" "o")]
)
]
"TARGET_A16"
"enter\t%0"
+ [(set_attr "flags" "x")]
)
(define_insn "prologue_enter_24"
]
"TARGET_A24"
"enter\t%0"
+ [(set_attr "flags" "x")]
)
; Just a comment, for debugging the assembler output.
[(unspec_volatile [(const_int 0)] UNS_PROLOGUE_END)]
""
"; end of prologue"
+ [(set_attr "flags" "n")]
)
] UNS_EH_EPILOGUE))]
""
"jmp.a\t__m32c_eh_return"
+ [(set_attr "flags" "x")]
)
(define_insn "epilogue_exitd"
]
""
"exitd"
+ [(set_attr "flags" "x")]
)
(define_insn "epilogue_reit"
]
""
"reit"
+ [(set_attr "flags" "x")]
)
(define_insn "epilogue_rts"
]
""
"rts"
+ [(set_attr "flags" "x")]
)
(define_insn "epilogue_start"
[(unspec_volatile [(const_int 0)] UNS_EPILOGUE_START)]
""
"; start of epilogue"
+ [(set_attr "flags" "n")]
)
(define_insn "pushm"
[(unspec [(match_operand 0 "const_int_operand" "i")] UNS_PUSHM)]
""
- "pushm\t%p0")
+ "pushm\t%p0"
+ [(set_attr "flags" "n")]
+ )
(define_insn "popm"
[(unspec [(match_operand 0 "const_int_operand" "i")] UNS_POPM)]
""
- "popm\t%p0")
+ "popm\t%p0"
+ [(set_attr "flags" "n")]
+ )
"@
sha.b\t%2,%0
mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
+ [(set_attr "flags" "oszc,oszc")]
)
(define_insn "ashrqi3_i"
"@
sha.b\t%2,%0
mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
+ [(set_attr "flags" "oszc,oszc")]
)
(define_insn "lshrqi3_i"
"@
shl.b\t%2,%0
mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
+ [(set_attr "flags" "szc,szc")]
)
"@
sha.w\t%2,%0
mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
+ [(set_attr "flags" "oszc,oszc")]
)
(define_insn "ashrhi3_i"
"@
sha.w\t%2,%0
mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
+ [(set_attr "flags" "oszc,oszc")]
)
(define_insn "lshrhi3_i"
"@
shl.w\t%2,%0
mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
+ [(set_attr "flags" "szc,szc")]
)
"@
sha.l\t%2,%0
mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+ [(set_attr "flags" "oszc,oszc")]
)
(define_insn "ashrpsi3_i"
"@
sha.l\t%2,%0
mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+ [(set_attr "flags" "oszc,oszc")]
)
(define_insn "lshrpsi3_i"
"@
shl.l\t%2,%0
mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
+ [(set_attr "flags" "szc,szc")]
)
"@
sha.l\t%2,%0
mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
- [(set_attr "flags" "sz,sz")]
+ [(set_attr "flags" "oszc,oszc")]
)
(define_insn "ashrsi3_16"
"@
sha.l\t%2,%0
mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
+ [(set_attr "flags" "oszc,oszc")]
)
(define_insn "lshrsi3_16"
"@
shl.l\t%2,%0
mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
+ [(set_attr "flags" "szc,szc")]
)
projects / platform / upstream / gcc.git / commitdiff