static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
{
struct spi_qup *controller = spi_master_get_devdata(spi->master);
- u32 config, iomode, mode;
- int ret, n_words, w_size;
+ u32 config, iomode, mode, control;
- --- int ret, n_words, w_size;
+ ++++ int ret, n_words;
if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
dev_err(controller->dev, "too big size for loopback %d > %d\n",
return -EIO;
}
- ---- w_size = 4;
- ---- if (xfer->bits_per_word <= 8)
- ---- w_size = 1;
- ---- else if (xfer->bits_per_word <= 16)
- ---- w_size = 2;
-
- n_words = xfer->len / w_size;
- controller->w_size = w_size;
+ ++++ mode = spi_qup_get_mode(spi->master, xfer);
+ ++++ n_words = controller->n_words;
---- n_words = xfer->len / w_size;
---- controller->w_size = w_size;
----
- ---- if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
- ---- mode = QUP_IO_M_MODE_FIFO;
+ ++++ if (mode == QUP_IO_M_MODE_FIFO) {
writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
/* must be zero for FIFO */
}
/* div doesn't support odd number */
----- div = max_t(u32, rs->max_freq / rs->speed, 1);
+++++ div = DIV_ROUND_UP(rs->max_freq, rs->speed);
div = (div + 1) & 0xfffe;
++ +++ /* Rx sample delay is expressed in parent clock cycles (max 3) */
++ +++ rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
++ +++ 1000000000 >> 8);
++ +++ if (!rsd && rs->rsd_nsecs) {
++ +++ pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
++ +++ rs->max_freq, rs->rsd_nsecs);
++ +++ } else if (rsd > 3) {
++ +++ rsd = 3;
++ +++ pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
++ +++ rs->max_freq, rs->rsd_nsecs,
++ +++ rsd * 1000000000U / rs->max_freq);
++ +++ }
++ +++ cr0 |= rsd << CR0_RSD_OFFSET;
++ +++
writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);