imx: define ARCH_MXC for i.MX8/8M/7ULP
authorPeng Fan <peng.fan@nxp.com>
Thu, 9 May 2019 08:33:55 +0000 (08:33 +0000)
committerStefano Babic <sbabic@denx.de>
Tue, 11 Jun 2019 08:43:00 +0000 (10:43 +0200)
Without this definition, fsl_esdhc will access reserved registers
on i.MX chips, so define ARCH_MXC to fix it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
arch/arm/include/asm/arch-imx8/imx-regs.h
arch/arm/include/asm/arch-imx8m/imx-regs.h
arch/arm/include/asm/arch-mx7ulp/imx-regs.h

index af0fb51..6333ff4 100644 (file)
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARCH_IMX8_REGS_H__
 #define __ASM_ARCH_IMX8_REGS_H__
 
+#define ARCH_MXC
+
 #define LPUART_BASE            0x5A060000
 
 #define GPT1_BASE_ADDR         0x5D140000
index 3facd54..68666a5 100644 (file)
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARCH_IMX8M_REGS_H__
 #define __ASM_ARCH_IMX8M_REGS_H__
 
+#define ARCH_MXC
+
 #include <asm/mach-imx/regs-lcdif.h>
 
 #define ROM_VERSION_A0         0x800
index bf9f39a..63b02de 100644 (file)
@@ -8,6 +8,8 @@
 
 #include <linux/sizes.h>
 
+#define ARCH_MXC
+
 #define CAAM_SEC_SRAM_BASE      (0x26000000)
 #define CAAM_SEC_SRAM_SIZE      (SZ_32K)
 #define CAAM_SEC_SRAM_END       (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)