#define GEN6_TD_CTL 0x7000 /* <= GEN5 was at 0x8000 */
#define GEN6_TD_CTL_FORCE_TD_BKPT (1<<4)
+/* Port debugging
+ */
+
+#define PORT_DBG 0x42308
+#define PORT_DBG_DRRS_HW_STATE_OFF (0<<30)
+#define PORT_DBG_DRRS_HW_STATE_LOW (1<<30)
+#define PORT_DBG_DRRS_HW_STATE_HIGH (2<<30)
+
#endif /* _I810_REG_H */
_OREG_UPDATE_STATUS);
}
+DEBUGSTRING(ivb_debug_port)
+{
+ char *drrs;
+ switch (val & (2 << 30)) {
+ case PORT_DBG_DRRS_HW_STATE_OFF:
+ drrs = "off";
+ break;
+ case PORT_DBG_DRRS_HW_STATE_LOW:
+ drrs = "low";
+ break;
+ case PORT_DBG_DRRS_HW_STATE_HIGH:
+ drrs = "high";
+ break;
+ }
+ snprintf(result, len, "HW DRRS %s",
+ drrs);
+}
+
DEBUGSTRING(i830_debug_hvtotal)
{
snprintf(result, len, "%d active, %d total",
DEFINEREG(PCH_PP_ON_DELAYS),
DEFINEREG(PCH_PP_OFF_DELAYS),
DEFINEREG(PCH_PP_DIVISOR),
+
+ DEFINEREG2(PORT_DBG, ivb_debug_port),
};
static struct reg_debug i945gm_mi_regs[] = {