This patch fixes a bug in the AArch64 assembler where an incorrect structural load...
authorBarnaby Wilks <barnaby.wilks@arm.com>
Tue, 2 Jul 2019 13:09:52 +0000 (14:09 +0100)
committerNick Clifton <nickc@redhat.com>
Tue, 2 Jul 2019 13:11:14 +0000 (14:11 +0100)
For example, when provided with the (incorrect) instruction

st4 {v0.16b-v3.16b}[4],[x0]

currently assembler provides the following error message
"Error: comma expected between operands at operand 2 -- `st4 {v0.16b-v3.16b}[4],[x0]'".

This was due to the assembler consuming the {v0.16b-v3.16b} as the first operand leaving
[4],[x0] as what it believed to be the second operand.

The actual error is that the first operand should be of element type and not
vector type (as provided). The new diagnostic for this error is
"Error: expected element type rather than vector type at operand 1 -- `st4 {v0.16b-v3.16b}[4],[x0]'.

Added testcases to check for the correct diagnostic message as well as checking that
variations of the structural load/store by element instruction also generate the error
when they have the same problem.

* config/tc-aarch64.c (parse_operands): Add error check.
* testsuite/gas/aarch64/diagnostic.l: New test.
* testsuite/gas/aarch64/diagnostic.s: New test.
* testsuite/gas/aarch64/illegal.l: New tests.
* testsuite/gas/aarch64/illegal.s: New tests.

gas/ChangeLog
gas/config/tc-aarch64.c
gas/testsuite/gas/aarch64/diagnostic.l
gas/testsuite/gas/aarch64/diagnostic.s
gas/testsuite/gas/aarch64/illegal.l
gas/testsuite/gas/aarch64/illegal.s

index f3fe16a..2134607 100644 (file)
@@ -1,3 +1,11 @@
+2019-07-02  Barnaby Wilks  <barnaby.wilks@arm.com>
+
+       * config/tc-aarch64.c (parse_operands): Add error check.
+       * testsuite/gas/aarch64/diagnostic.l: New test.
+       * testsuite/gas/aarch64/diagnostic.s: New test.
+       * testsuite/gas/aarch64/illegal.l: New tests.
+       * testsuite/gas/aarch64/illegal.s: New tests.
+
 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 
        * testsuite/gas/aarch64/sve-movprfx_27.s,
index 000a81c..47af143 100644 (file)
@@ -5733,11 +5733,20 @@ parse_operands (char *str, const aarch64_opcode *opcode)
              val = parse_vector_reg_list (&str, reg_type, &vectype);
              if (val == PARSE_FAIL)
                goto failure;
+
              if (! reg_list_valid_p (val, /* accept_alternate */ 0))
                {
                  set_fatal_syntax_error (_("invalid register list"));
                  goto failure;
                }
+
+             if (vectype.width != 0 && *str != ',')
+               {
+                 set_fatal_syntax_error
+                   (_("expected element type rather than vector type"));
+                 goto failure;
+               }
+
              info->reglist.first_regno = (val >> 2) & 0x1f;
              info->reglist.num_regs = (val & 0x3) + 1;
            }
index 6aae306..b5f304a 100644 (file)
 [^:]*:311: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x26,\[x3\]'
 [^:]*:312: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x26,\[x5\]'
 [^:]*:313: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x1,\[x26\]'
+[^:]*:314: Error: expected element type rather than vector type at operand 1 -- `st4 {v0\.16b-v3\.16b}\[4\],\[x0\]'
index c18c48e..21cbc53 100644 (file)
        stlxr   w26, x26, [x3]
        ldxp    x26, x26, [x5]
        ldxp    x26, x1, [x26]
+       st4     {v0.16b-v3.16b}[4], [x0]
index 0c90110..75ef830 100644 (file)
 [^:]*:585: Error: .*`fcmgt v0\.2d,v0\.2d,#-0\.0'
 [^:]*:589: Error: .*`fmov s9,x0'
 [^:]*:590: Error: .*`fmov d7,w1'
-[^:]*:592: Error: .*
+[^:]*:592: Error: .*`st1 {v0\.16b}\[0\],\[x0\]'
+[^:]*:593: Error: .*`st2 {v0\.16b-v1\.16b}\[1\],\[x0\]'
+[^:]*:594: Error: .*`st3 {v0\.16b-v2\.16b}\[2\],\[x0\]'
+[^:]*:595: Error: .*`st4 {v0\.8b-v3\.8b}\[4\],\[x0\]'
+[^:]*:597: Error: .*
index 7efe69e..ef03cc9 100644 (file)
@@ -589,4 +589,9 @@ one_label:
        fmov    s9, x0
        fmov    d7, w1
 
+       st1 {v0.16b}[0],[x0]
+       st2 {v0.16b-v1.16b}[1],[x0]
+       st3 {v0.16b-v2.16b}[2],[x0]
+       st4 {v0.8b-v3.8b}[4],[x0]
+
        // End (for errors during literal pool generation)