clk: renesas: r9a07g044: Add OSTM clock and reset entries

Add OSTM{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211110082019.28554-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 54c2eb3..6c0c95b 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -145,6 +145,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
                                0x52c, 0),
        DEF_MOD("dmac_pclk",    R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
                                0x52c, 1),
+       DEF_MOD("ostm0_pclk",   R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
+                               0x534, 0),
+       DEF_MOD("ostm1_clk",    R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
+                               0x534, 1),
+       DEF_MOD("ostm2_pclk",   R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
+                               0x534, 2),
        DEF_MOD("wdt0_pclk",    R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
                                0x548, 0),
        DEF_MOD("wdt0_clk",     R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
@@ -247,6 +253,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
        DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
        DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
+       DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
+       DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
+       DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
        DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
        DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
        DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),