[Clang][AArch64][SME] Add intrinsics for reading streaming vector length

This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):

  - svcntsb
  - svcntsh
  - svcntsw
  - svcntsd

Co-authored-by: Sagar Kulkarni <sagar.kulkarni1@huawei.com>
Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D134679

diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td
index 945f212..74ba023 100644 (file)
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -135,3 +135,19 @@ let TargetGuard = "sme" in {
   def SVZERO_ZA      : SInst<"svzero_za", "v", "", MergeNone, "aarch64_sme_zero",
                              [IsOverloadNone, IsStreamingCompatible, IsSharedZA]>;
 }
+
+////////////////////////////////////////////////////////////////////////////////
+// SME - Counting elements in a streaming vector
+
+multiclass ZACount<string n_suffix> {
+  let TargetGuard = "sme" in {
+    def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone,
+                      "aarch64_sme_" # n_suffix,
+                      [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
+  }
+}
+
+defm SVCNTSB : ZACount<"cntsb">;
+defm SVCNTSH : ZACount<"cntsh">;
+defm SVCNTSW : ZACount<"cntsw">;
+defm SVCNTSD : ZACount<"cntsd">;

diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 416c220..d8d1e7a 100644 (file)
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -9955,6 +9955,7 @@ Value *CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
   getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
   assert(Error == ASTContext::GE_None && "Should not codegen an error");
 
+  llvm::Type *Ty = ConvertType(E->getType());
   llvm::SmallVector<Value *, 4> Ops;
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
     if ((ICEArguments & (1 << i)) == 0)
@@ -9987,6 +9988,12 @@ Value *CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
   else if (BuiltinID == SME::BI__builtin_sme_svldr_vnum_za ||
            BuiltinID == SME::BI__builtin_sme_svstr_vnum_za)
     return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (Builtin->LLVMIntrinsic != 0) {
+    Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic,
+                                   getSVEOverloadTypes(TypeFlags, Ty, Ops));
+    Value *Call = Builder.CreateCall(F, Ops);
+    return Call;
+  }
 
   /// Should not happen
   return nullptr;

diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
new file mode 100644 (file)
index 0000000..b3b2499
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include <arm_sme_draft_spec_subject_to_change.h>
+
+// CHECK-C-LABEL: @test_svcntsb(
+// CHECK-CXX-LABEL: @_Z12test_svcntsbv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t test_svcntsb() {
+  return svcntsb();
+}
+
+// CHECK-C-LABEL: @test_svcntsh(
+// CHECK-CXX-LABEL: @_Z12test_svcntshv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t test_svcntsh() {
+  return svcntsh();
+}
+
+// CHECK-C-LABEL: @test_svcntsw(
+// CHECK-CXX-LABEL: @_Z12test_svcntswv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t test_svcntsw() {
+  return svcntsw();
+}
+
+// CHECK-C-LABEL: @test_svcntsd(
+// CHECK-CXX-LABEL: @_Z12test_svcntsdv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t test_svcntsd() {
+  return svcntsd();
+}