ARM: dts: exynos4: add sysmmu nodes

This patch adds System MMU nodes that are specific to Exynos4210/4x12 series.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 77ea547768f4fa24965ce945b6a7ea2adc12ba60..4089313bc0fde5ca7a8658613ef8cffc33e40cf8 100644 (file)
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -187,6 +187,7 @@
                        clock-names = "fimc", "sclk_fimc";
                        power-domains = <&pd_cam>;
                        samsung,sysreg = <&sys_reg>;
+                       iommus = <&sysmmu_fimc0>;
                        status = "disabled";
                };
 
@@ -198,6 +199,7 @@
                        clock-names = "fimc", "sclk_fimc";
                        power-domains = <&pd_cam>;
                        samsung,sysreg = <&sys_reg>;
+                       iommus = <&sysmmu_fimc1>;
                        status = "disabled";
                };
 
@@ -209,6 +211,7 @@
                        clock-names = "fimc", "sclk_fimc";
                        power-domains = <&pd_cam>;
                        samsung,sysreg = <&sys_reg>;
+                       iommus = <&sysmmu_fimc2>;
                        status = "disabled";
                };
 
@@ -220,6 +223,7 @@
                        clock-names = "fimc", "sclk_fimc";
                        power-domains = <&pd_cam>;
                        samsung,sysreg = <&sys_reg>;
+                       iommus = <&sysmmu_fimc3>;
                        status = "disabled";
                };
 
@@ -414,6 +418,8 @@
                clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
                clock-names = "mfc", "sclk_mfc";
                status = "disabled";
+               iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
+               iommu-names = "left", "right";
        };
 
        serial_0: serial@13800000 {
@@ -679,6 +685,7 @@
                power-domains = <&pd_lcd0>;
                samsung,sysreg = <&sys_reg>;
                status = "disabled";
+               iommus = <&sysmmu_fimd0>;
        };
 
        tmu: tmu@100C0000 {
@@ -705,6 +712,7 @@
                interrupts = <0 91 0>;
                reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
                power-domains = <&pd_tv>;
+               iommus = <&sysmmu_tv>;
                status = "disabled";
        };
 
@@ -815,4 +823,114 @@
                clock-names = "ppmu";
                status = "disabled";
        };
+
+       sysmmu_mfc_l: sysmmu@13620000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x13620000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <5 5>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
+               power-domains = <&pd_mfc>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_mfc_r: sysmmu@13630000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x13630000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <5 6>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
+               power-domains = <&pd_mfc>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_tv: sysmmu@12E20000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x12E20000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <5 4>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
+               power-domains = <&pd_tv>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc0: sysmmu@11A20000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x11A20000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <4 2>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
+               power-domains = <&pd_cam>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc1: sysmmu@11A30000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x11A30000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <4 3>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
+               power-domains = <&pd_cam>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc2: sysmmu@11A40000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x11A40000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <4 4>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
+               power-domains = <&pd_cam>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc3: sysmmu@11A50000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x11A50000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <4 5>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
+               power-domains = <&pd_cam>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_jpeg: sysmmu@11A60000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x11A60000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <4 6>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
+               power-domains = <&pd_cam>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_rotator: sysmmu@12A30000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x12A30000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <5 0>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
+               power-domains = <&pd_lcd0>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimd0: sysmmu@11E20000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x11E20000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <5 2>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
+               power-domains = <&pd_lcd0>;
+               #iommu-cells = <0>;
+       };
 };

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index be89f83f70e7750577441c7400567a57c89ec9cb..19a8e711e61627f7b223c320ec7468b2b9261184 100644 (file)
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -195,6 +195,7 @@
                interrupts = <0 89 0>;
                clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
                clock-names = "sclk_fimg2d", "fimg2d";
+               iommus = <&sysmmu_g2d>;
                status = "disabled";
        };
 
@@ -244,4 +245,26 @@
                clock-names = "ppmu";
                status = "disabled";
        };
+
+       sysmmu_g2d: sysmmu@12A20000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x12A20000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <4 7>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+               power-domains = <&pd_lcd0>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimd1: sysmmu@12220000 {
+               compatible = "samsung,exynos-sysmmu";
+               interrupt-parent = <&combiner>;
+               reg = <0x12220000 0x1000>;
+               interrupts = <5 3>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
+               power-domains = <&pd_lcd1>;
+               #iommu-cells = <0>;
+       };
 };

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 6a6abe14fd9b59eed66e033ef43b970c6d4ce256..6c664bae0d9fcb1669614e3ae8bdfa3c04333f35 100644 (file)
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -165,6 +165,7 @@
                interrupts = <0 89 0>;
                clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
                clock-names = "sclk_fimg2d", "fimg2d";
+               iommus = <&sysmmu_g2d>;
                status = "disabled";
        };
 
@@ -214,6 +215,7 @@
                        power-domains = <&pd_isp>;
                        clocks = <&clock CLK_FIMC_LITE0>;
                        clock-names = "flite";
+                       iommus = <&sysmmu_fimc_lite0>;
                        status = "disabled";
                };
 
@@ -224,6 +226,7 @@
                        power-domains = <&pd_isp>;
                        clocks = <&clock CLK_FIMC_LITE1>;
                        clock-names = "flite";
+                       iommus = <&sysmmu_fimc_lite1>;
                        status = "disabled";
                };
 
@@ -252,6 +255,9 @@
                                      "mcuispdiv1", "uart", "aclk200",
                                      "div_aclk200", "aclk400mcuisp",
                                      "div_aclk400mcuisp";
+                       iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
+                                <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
+                       iommu-names = "isp", "drc", "fd", "mcuctl";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
@@ -309,4 +315,80 @@
                clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
                         <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
        };
+
+       sysmmu_g2d: sysmmu@10A40000{
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x10A40000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <4 7>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc_isp: sysmmu@12260000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x12260000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <16 2>;
+               power-domains = <&pd_isp>;
+               clock-names = "sysmmu";
+               clocks = <&clock CLK_SMMU_ISP>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc_drc: sysmmu@12270000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x12270000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <16 3>;
+               power-domains = <&pd_isp>;
+               clock-names = "sysmmu";
+               clocks = <&clock CLK_SMMU_DRC>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc_fd: sysmmu@122A0000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x122A0000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <16 4>;
+               power-domains = <&pd_isp>;
+               clock-names = "sysmmu";
+               clocks = <&clock CLK_SMMU_FD>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc_mcuctl: sysmmu@122B0000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x122B0000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <16 5>;
+               power-domains = <&pd_isp>;
+               clock-names = "sysmmu";
+               clocks = <&clock CLK_SMMU_ISPCX>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc_lite0: sysmmu@123B0000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x123B0000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <16 0>;
+               power-domains = <&pd_isp>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
+               #iommu-cells = <0>;
+       };
+
+       sysmmu_fimc_lite1: sysmmu@123C0000 {
+               compatible = "samsung,exynos-sysmmu";
+               reg = <0x123C0000 0x1000>;
+               interrupt-parent = <&combiner>;
+               interrupts = <16 1>;
+               power-domains = <&pd_isp>;
+               clock-names = "sysmmu", "master";
+               clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
+               #iommu-cells = <0>;
+       };
 };