clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock

The pll0_vote clock definitely should have pll0 as a parent (instead of
pll8).

Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers")
Cc: stable@kernel.org
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-7-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index fb5c1244fb97abc7eb92565ee2ed7967ca69ebf9..2f921891008d3c509d3553b2d383350a39d838c4 100644 (file)
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = {
        .enable_mask = BIT(0),
        .hw.init = &(struct clk_init_data){
                .name = "pll0_vote",
-               .parent_names = (const char *[]){ "pll8" },
+               .parent_names = (const char *[]){ "pll0" },
                .num_parents = 1,
                .ops = &clk_pll_vote_ops,
        },