[tblgen][disasm] Emit record names again when decoder conflicts occur.

And add a test for it.

llvm-svn: 350277

diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td b/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td
new file mode 100644 (file)
index 0000000..a9a95bc
--- /dev/null
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td
@@ -0,0 +1,35 @@
+// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t
+// RUN: FileCheck %s < %t
+
+include "llvm/Target/Target.td"
+
+def MyTargetISA : InstrInfo;
+def MyTarget : Target { let InstructionSet = MyTargetISA; }
+
+def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
+def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+
+class I<dag OOps, dag IOps, list<dag> Pat>
+  : Instruction {
+  let Namespace = "MyTarget";
+  let OutOperandList = OOps;
+  let InOperandList = IOps;
+  let Pattern = Pat;
+  bits<32> Inst;
+  bits<32> SoftFail;
+}
+
+def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
+  let Size = 4;
+  let Inst{31-0} = 0;
+}
+def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
+  let Size = 4;
+  let Inst{31-0} = 0;
+}
+
+// CHECK: Decoding Conflict:
+// CHECK:   00000000000000000000000000000000
+// CHECK:   ................................
+// CHECK: A 00000000000000000000000000000000
+// CHECK: B 00000000000000000000000000000000

diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
index 1206f77..5e621fc 100644 (file)
--- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -1717,7 +1717,7 @@ void FilterChooser::emitTableEntries(DecoderTableInfo &TableInfo) const {
   dumpStack(errs(), "\t\t");
 
   for (unsigned i = 0; i < Opcodes.size(); ++i) {
-    errs() << '\t' << Opcodes[i] << " ";
+    errs() << '\t' << AllInstructions[Opcodes[i]] << " ";
     dumpBits(errs(),
              getBitsField(*AllInstructions[Opcodes[i]].EncodingDef, "Inst"));
     errs() << '\n';