arm64: tegra: Add Tegra234 I2C devicetree nodes

Add device tree nodes for Tegra234 I2C controllers

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 6b6f158..c686827 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -144,6 +144,96 @@
                        status = "disabled";
                };
 
+               gen1_i2c: i2c@3160000 {
+                       compatible = "nvidia,tegra194-i2c";
+                       reg = <0x3160000 0x100>;
+                       status = "disabled";
+                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <400000>;
+                       clocks = <&bpmp TEGRA234_CLK_I2C1
+                                 &bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "div-clk", "parent";
+                       resets = <&bpmp TEGRA234_RESET_I2C1>;
+                       reset-names = "i2c";
+               };
+
+               cam_i2c: i2c@3180000 {
+                       compatible = "nvidia,tegra194-i2c";
+                       reg = <0x3180000 0x100>;
+                       interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clock-frequency = <400000>;
+                       clocks = <&bpmp TEGRA234_CLK_I2C3
+                               &bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "div-clk", "parent";
+                       resets = <&bpmp TEGRA234_RESET_I2C3>;
+                       reset-names = "i2c";
+               };
+
+               dp_aux_ch1_i2c: i2c@3190000 {
+                       compatible = "nvidia,tegra194-i2c";
+                       reg = <0x3190000 0x100>;
+                       interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clock-frequency = <100000>;
+                       clocks = <&bpmp TEGRA234_CLK_I2C4
+                               &bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "div-clk", "parent";
+                       resets = <&bpmp TEGRA234_RESET_I2C4>;
+                       reset-names = "i2c";
+               };
+
+               dp_aux_ch0_i2c: i2c@31b0000 {
+                       compatible = "nvidia,tegra194-i2c";
+                       reg = <0x31b0000 0x100>;
+                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clock-frequency = <100000>;
+                       clocks = <&bpmp TEGRA234_CLK_I2C6
+                               &bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "div-clk", "parent";
+                       resets = <&bpmp TEGRA234_RESET_I2C6>;
+                       reset-names = "i2c";
+               };
+
+               dp_aux_ch2_i2c: i2c@31c0000 {
+                       compatible = "nvidia,tegra194-i2c";
+                       reg = <0x31c0000 0x100>;
+                       interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clock-frequency = <100000>;
+                       clocks = <&bpmp TEGRA234_CLK_I2C7
+                               &bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "div-clk", "parent";
+                       resets = <&bpmp TEGRA234_RESET_I2C7>;
+                       reset-names = "i2c";
+               };
+
+               dp_aux_ch3_i2c: i2c@31e0000 {
+                       compatible = "nvidia,tegra194-i2c";
+                       reg = <0x31e0000 0x100>;
+                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clock-frequency = <100000>;
+                       clocks = <&bpmp TEGRA234_CLK_I2C9
+                               &bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "div-clk", "parent";
+                       resets = <&bpmp TEGRA234_RESET_I2C9>;
+                       reset-names = "i2c";
+               };
+
                mmc@3460000 {
                        compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
                        reg = <0x03460000 0x20000>;
@@ -212,6 +302,37 @@
                        #mbox-cells = <2>;
                };
 
+               gen2_i2c: i2c@c240000 {
+                       compatible = "nvidia,tegra194-i2c";
+                       reg = <0xc240000 0x100>;
+                       interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clock-frequency = <100000>;
+                       clocks = <&bpmp TEGRA234_CLK_I2C2
+                               &bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "div-clk", "parent";
+                       assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       resets = <&bpmp TEGRA234_RESET_I2C2>;
+                       reset-names = "i2c";
+               };
+
+               gen8_i2c: i2c@c250000 {
+                       compatible = "nvidia,tegra194-i2c";
+                       reg = <0xc250000 0x100>;
+                       nvidia,hw-instance-id = <0x7>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clock-frequency = <400000>;
+                       clocks = <&bpmp TEGRA234_CLK_I2C8
+                               &bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "div-clk", "parent";
+                       assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       resets = <&bpmp TEGRA234_RESET_I2C8>;
+                       reset-names = "i2c";
+               };
+
                rtc@c2a0000 {
                        compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
                        reg = <0x0c2a0000 0x10000>;