+Wed Sep 20 21:44:31 2000 Denis Chertykov <denisc@overta.ru>
+
+ * config/avr/avr.c (adjust_insn_length): Adjust lengths of
+ `reload_in*' insns.
+
+2000-09-19 Marek Michalkiewicz <marekm@linux.org.pl>
+
+ * config/avr/avr.md (neghi2): Add alternative for input and output
+ operands in different registers, as in negsi2.
+ (*negsi2): Remove '*' from the name. Use "movw" if available.
+
2000-09-19 Jim Wilson <wilson@cygnus.com>
* config/ia64/crtbegin.asm (__dso_handle): Delete use of
{
rtx patt = PATTERN (insn);
rtx set;
+
if (GET_CODE (patt) == SET)
{
rtx op[10];
if (set)
{
rtx op[10];
+
op[1] = SET_SRC (set);
op[0] = SET_DEST (set);
- if (GET_CODE (op[1]) == ASHIFT
+
+ if (GET_CODE (patt) == PARALLEL
+ && general_operand (op[1], VOIDmode)
+ && general_operand (op[0], VOIDmode))
+ {
+ if (XVECLEN (patt, 0) == 2)
+ op[2] = XVECEXP (patt, 0, 1);
+
+ switch (GET_MODE (op[0]))
+ {
+ case QImode:
+ len = 2;
+ break;
+ case HImode:
+ output_reload_inhi (insn, op, &len);
+ break;
+ case SImode:
+ case SFmode:
+ output_reload_insisf (insn, op, &len);
+ break;
+ default:
+ break;
+ }
+ }
+ else if (GET_CODE (op[1]) == ASHIFT
|| GET_CODE (op[1]) == ASHIFTRT
|| GET_CODE (op[1]) == LSHIFTRT)
{
(set_attr "cc" "set_zn")])
(define_insn "neghi2"
- [(set (match_operand:HI 0 "register_operand" "=!d,r")
- (neg:HI (match_operand:HI 1 "register_operand" "0,0")))]
+ [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
+ (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
""
"@
com %B0\;neg %A0\;sbci %B0,lo8(-1)
- com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0"
- [(set_attr "length" "3,4")
- (set_attr "cc" "set_czn,set_n")])
+ com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
+ clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
+ [(set_attr "length" "3,4,4")
+ (set_attr "cc" "set_czn,set_n,set_czn")])
-(define_insn "*negsi2"
+(define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=!d,r,&r")
(neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
""
"@
com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
- clr %A0\;clr %B0\;clr %C0\;clr %D0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
- [(set_attr "length" "7,8,8")
+ clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
+ [(set_attr_alternative "length"
+ [(const_int 7)
+ (const_int 8)
+ (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (const_int 7)
+ (const_int 8))])
(set_attr "cc" "set_czn,set_n,set_czn")])
(define_insn "negsf2"