Get the cached subtarget off the MachineFunction rather than

inquiring for a new one from the TargetMachine.

llvm-svn: 229998

diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 572d7c8..62416bc 100644 (file)
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -224,7 +224,7 @@ def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
   // put it at the end of the list.
   let AltOrders = [(add (sub GPRC, R2), R2)];
   let AltOrderSelect = [{
-    const PPCSubtarget &S = MF.getTarget().getSubtarget<PPCSubtarget>();
+    const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
     return S.isPPC64() && S.isSVR4ABI();
   }];
 }
@@ -236,7 +236,7 @@ def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
   // put it at the end of the list.
   let AltOrders = [(add (sub G8RC, X2), X2)];
   let AltOrderSelect = [{
-    const PPCSubtarget &S = MF.getTarget().getSubtarget<PPCSubtarget>();
+    const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
     return S.isPPC64() && S.isSVR4ABI();
   }];
 }
@@ -249,7 +249,7 @@ def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)> {
   // put it at the end of the list.
   let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
   let AltOrderSelect = [{
-    const PPCSubtarget &S = MF.getTarget().getSubtarget<PPCSubtarget>();
+    const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
     return S.isPPC64() && S.isSVR4ABI();
   }];
 }
@@ -259,7 +259,7 @@ def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
   // put it at the end of the list.
   let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
   let AltOrderSelect = [{
-    const PPCSubtarget &S = MF.getTarget().getSubtarget<PPCSubtarget>();
+    const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
     return S.isPPC64() && S.isSVR4ABI();
   }];
 }