@item
@code{AMX_TILE} -- Tile architecture.
+@item
+@code{APX_F} -- The APX instruction extensions.
+
@item
@code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
x86_cpu_AVX_NE_CONVERT = x86_cpu_index_7_ecx_1_edx + 5,
x86_cpu_AMX_COMPLEX = x86_cpu_index_7_ecx_1_edx + 8,
x86_cpu_PREFETCHI = x86_cpu_index_7_ecx_1_edx + 14,
+ x86_cpu_APX_F = x86_cpu_index_7_ecx_1_edx + 21,
x86_cpu_index_19_ebx
= (CPUID_INDEX_19 * 8 * 4 * sizeof (unsigned int)
CPU_FEATURE_SET_ACTIVE (cpu_features, AMX_COMPLEX);
}
+ /* APX is usable only if the APX state is supported by kernel. */
+ if ((xcrlow & bit_APX_state) != 0)
+ CPU_FEATURE_SET_ACTIVE (cpu_features, APX_F);
+
/* These features are usable only when OSXSAVE is enabled. */
CPU_FEATURE_SET (cpu_features, XSAVE);
CPU_FEATURE_SET_ACTIVE (cpu_features, XSAVEOPT);
#define bit_cpu_AVX_NE_CONVERT (1u << 5)
#define bit_cpu_AMX_COMPLEX (1u << 8)
#define bit_cpu_PREFETCHI (1u << 14)
+#define bit_cpu_APX_F (1u << 21)
/* CPUID_INDEX_19. */
#define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
#define index_cpu_AMX_COMPLEX CPUID_INDEX_7_ECX_1
#define index_cpu_PREFETCHI CPUID_INDEX_7_ECX_1
+#define index_cpu_APX_F CPUID_INDEX_7_ECX_1
/* CPUID_INDEX_19. */
#define reg_AVX_NE_CONVERT edx
#define reg_AMX_COMPLEX edx
#define reg_PREFETCHI edx
+#define reg_APX_F edx
/* CPUID_INDEX_19. */
#define bit_ZMM16_31_state (1u << 7)
#define bit_XTILECFG_state (1u << 17)
#define bit_XTILEDATA_state (1u << 18)
+#define bit_APX_state (1u << 19)
enum cpu_features_kind
{
CHECK_CPU_FEATURE_PRESENT (AVX_NE_CONVERT);
CHECK_CPU_FEATURE_PRESENT (AMX_COMPLEX);
CHECK_CPU_FEATURE_PRESENT (PREFETCHI);
+ CHECK_CPU_FEATURE_PRESENT (APX_F);
CHECK_CPU_FEATURE_PRESENT (AESKLE);
CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
CHECK_CPU_FEATURE_PRESENT (PTWRITE);
CHECK_CPU_FEATURE_ACTIVE (AVX_NE_CONVERT);
CHECK_CPU_FEATURE_ACTIVE (AMX_COMPLEX);
CHECK_CPU_FEATURE_ACTIVE (PREFETCHI);
+ CHECK_CPU_FEATURE_ACTIVE (APX_F);
CHECK_CPU_FEATURE_ACTIVE (AESKLE);
CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
CHECK_CPU_FEATURE_ACTIVE (PTWRITE);