;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
+;;- Information about MCF5200 port.
+
+;;- The MCF5200 "ColdFire" architecture is a reduced version of the
+;;- 68k ISA. Differences include reduced support for byte and word
+;;- operands and the removal of BCD, bitfield, rotate, and integer
+;;- divide instructions. The TARGET_5200 flag turns the use of the
+;;- removed opcodes and addressing modes off.
+;;-
+
;;- instruction definitions
/* ISI's assembler fails to handle tstl a0. */
if (! ADDRESS_REG_P (operands[0]))
#else
- if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
+ if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
#endif
return \"tst%.l %0\";
/* If you think that the 68020 does not support tstl a0,
[(set (cc0)
(compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
(match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
- ""
+ "!TARGET_5200"
"*
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
[(set (cc0)
(compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
(match_operand:QI 1 "general_operand" "dm,nd,>")))]
- ""
+ "!TARGET_5200"
"*
{
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
#ifndef NO_ADDSUB_Q
if (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) <= 8)
- return (ADDRESS_REG_P (operands[0])
+ return (ADDRESS_REG_P (operands[0]) && !TARGET_5200
? \"addq%.w %2,%0\"
: \"addq%.l %2,%0\");
if (INTVAL (operands[2]) < 0
{
operands[2] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[2]));
- return (ADDRESS_REG_P (operands[0])
+ return (ADDRESS_REG_P (operands[0]) && !TARGET_5200
? \"subq%.w %2,%0\"
: \"subq%.l %2,%0\");
}
#endif
if (ADDRESS_REG_P (operands[0])
&& INTVAL (operands[2]) >= -0x8000
- && INTVAL (operands[2]) < 0x8000)
+ && INTVAL (operands[2]) < 0x8000
+ && !TARGET_5200)
return \"add%.w %2,%0\";
}
return \"add%.l %2,%0\";
(plus:SI (match_operand:SI 1 "general_operand" "0")
(sign_extend:SI
(match_operand:HI 2 "nonimmediate_operand" "rm"))))]
- ""
+ "!TARGET_5200"
"add%.w %2,%0")
(define_insn "addhi3"
[(set (match_operand:HI 0 "general_operand" "=m,r")
(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_operand" "dn,rmn")))]
- ""
+ "!TARGET_5200"
"*
{
#ifndef NO_ADDSUB_Q
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
(plus:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dn,rmn")))]
- ""
+ "!TARGET_5200"
"*
{
#ifndef NO_ADDSUB_Q
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
(plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
(match_dup 0)))]
- ""
+ "!TARGET_5200"
"*
{
#ifndef NO_ADDSUB_Q
[(set (match_operand:QI 0 "general_operand" "=m,d")
(plus:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"*
{
#ifndef NO_ADDSUB_Q
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
(plus:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"*
{
#ifndef NO_ADDSUB_Q
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
(plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
(match_dup 0)))]
- ""
+ "!TARGET_5200"
"*
{
#ifndef NO_ADDSUB_Q
(minus:SI (match_operand:SI 1 "general_operand" "0")
(sign_extend:SI
(match_operand:HI 2 "nonimmediate_operand" "rm"))))]
- ""
+ "!TARGET_5200"
"sub%.w %2,%0")
(define_insn "subhi3"
[(set (match_operand:HI 0 "general_operand" "=m,r")
(minus:HI (match_operand:HI 1 "general_operand" "0,0")
(match_operand:HI 2 "general_operand" "dn,rmn")))]
- ""
+ "!TARGET_5200"
"sub%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
(minus:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dn,rmn")))]
- ""
+ "!TARGET_5200"
"sub%.w %1,%0")
(define_insn "subqi3"
[(set (match_operand:QI 0 "general_operand" "=m,d")
(minus:QI (match_operand:QI 1 "general_operand" "0,0")
(match_operand:QI 2 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"sub%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
(minus:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"sub%.b %1,%0")
(define_expand "subdf3"
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(zero_extend:DI (match_dup 2)))
(const_int 32))))])]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"")
(define_insn ""
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(zero_extend:DI (match_dup 2)))
(const_int 32))))]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"mulu%.l %2,%3:%0")
; Match immediate case. For 2.4 only match things < 2^31.
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(match_dup 2))
(const_int 32))))]
- "TARGET_68020 && !TARGET_68060
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200
&& (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
"mulu%.l %2,%3:%0")
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(sign_extend:DI (match_dup 2)))
(const_int 32))))])]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"")
(define_insn ""
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(sign_extend:DI (match_dup 2)))
(const_int 32))))]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"muls%.l %2,%3:%0")
(define_insn ""
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(match_dup 2))
(const_int 32))))]
- "TARGET_68020 && !TARGET_68060
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200
/* This test is a noop on 32 bit machines,
but important for a cross-compiler hosted on 64-bit machines. */
&& INTVAL (operands[2]) <= 0x7fffffff
(zero_extend:DI (match_operand:SI 2 "general_operand" "")))
(const_int 32))))
(clobber (match_dup 3))])]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"
{
operands[3] = gen_reg_rtx (SImode);
(zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"mulu%.l %3,%0:%1")
(define_insn "const_umulsi3_highpart"
(match_operand 3 "const_uint32_operand" ""))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"mulu%.l %3,%0:%1")
(define_expand "smulsi3_highpart"
(sign_extend:DI (match_operand:SI 2 "general_operand" "")))
(const_int 32))))
(clobber (match_dup 3))])]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"
{
operands[3] = gen_reg_rtx (SImode);
(sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"muls%.l %3,%0:%1")
(define_insn "const_smulsi3_highpart"
(match_operand 3 "const_sint32_operand" ""))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
- "TARGET_68020 && !TARGET_68060"
+ "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
"muls%.l %3,%0:%1")
(define_expand "muldf3"
(match_operand:SI 2 "general_operand" "dmsK")))
(set (match_operand:SI 3 "general_operand" "=d")
(mod:SI (match_dup 1) (match_dup 2)))]
- "TARGET_68020"
+ "TARGET_68020 && !TARGET_5200"
"*
{
if (find_reg_note (insn, REG_UNUSED, operands[3]))
(match_operand:SI 2 "general_operand" "dmsK")))
(set (match_operand:SI 3 "general_operand" "=d")
(umod:SI (match_dup 1) (match_dup 2)))]
- "TARGET_68020"
+ "TARGET_68020 && !TARGET_5200"
"*
{
if (find_reg_note (insn, REG_UNUSED, operands[3]))
(match_operand:HI 2 "general_operand" "dmsK")))
(set (match_operand:HI 3 "general_operand" "=d")
(mod:HI (match_dup 1) (match_dup 2)))]
- ""
+ "!TARGET_5200"
"*
{
#ifdef MOTOROLA
(match_operand:HI 2 "general_operand" "dmsK")))
(set (match_operand:HI 3 "general_operand" "=d")
(umod:HI (match_dup 1) (match_dup 2)))]
- ""
+ "!TARGET_5200"
"*
{
#ifdef MOTOROLA
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) | 0xffff) == 0xffffffff
&& (DATA_REG_P (operands[0])
- || offsettable_memref_p (operands[0])))
+ || offsettable_memref_p (operands[0]))
+ && !TARGET_5200)
{
if (GET_CODE (operands[0]) != REG)
operands[0] = adj_offsettable_operand (operands[0], 2);
[(set (match_operand:HI 0 "general_operand" "=m,d")
(and:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"and%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
(and:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"and%.w %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
(and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
(match_dup 0)))]
- ""
+ "!TARGET_5200"
"and%.w %1,%0")
(define_insn "andqi3"
[(set (match_operand:QI 0 "general_operand" "=m,d")
(and:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"and%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
(and:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"and%.b %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
(and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
(match_dup 0)))]
- ""
+ "!TARGET_5200"
"and%.b %1,%0")
\f
;; inclusive-or instructions
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) >> 16 == 0
&& (DATA_REG_P (operands[0])
- || offsettable_memref_p (operands[0])))
+ || offsettable_memref_p (operands[0]))
+ && !TARGET_5200)
{
if (GET_CODE (operands[0]) != REG)
operands[0] = adj_offsettable_operand (operands[0], 2);
[(set (match_operand:HI 0 "general_operand" "=m,d")
(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"or%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
(ior:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"or%.w %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
(ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
(match_dup 0)))]
- ""
+ "!TARGET_5200"
"or%.w %1,%0")
(define_insn "iorqi3"
[(set (match_operand:QI 0 "general_operand" "=m,d")
(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
(match_operand:QI 2 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"or%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
(ior:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dn,dmn")))]
- ""
+ "!TARGET_5200"
"or%.b %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
(ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
(match_dup 0)))]
- ""
+ "!TARGET_5200"
"or%.b %1,%0")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=o,d")
(ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
(match_operand:SI 2 "general_operand" "0,0")))]
- ""
+ "!TARGET_5200"
"*
{
int byte_mode;
{
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) >> 16 == 0
- && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
+ && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
+ && !TARGET_5200)
{
if (! DATA_REG_P (operands[0]))
operands[0] = adj_offsettable_operand (operands[0], 2);
[(set (match_operand:HI 0 "general_operand" "=dm")
(xor:HI (match_operand:HI 1 "general_operand" "%0")
(match_operand:HI 2 "general_operand" "dn")))]
- ""
+ "!TARGET_5200"
"eor%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
(xor:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dn")))]
- ""
+ "!TARGET_5200"
"eor%.w %1,%0")
-
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
(xor:HI (match_operand:HI 1 "general_operand" "dn")
(match_dup 0)))]
- ""
+ "!TARGET_5200"
"eor%.w %1,%0")
(define_insn "xorqi3"
[(set (match_operand:QI 0 "general_operand" "=dm")
(xor:QI (match_operand:QI 1 "general_operand" "%0")
(match_operand:QI 2 "general_operand" "dn")))]
- ""
+ "!TARGET_5200"
"eor%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
(xor:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dn")))]
- ""
+ "!TARGET_5200"
"eor%.b %1,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
(xor:QI (match_operand:QI 1 "general_operand" "dn")
(match_dup 0)))]
- ""
+ "!TARGET_5200"
"eor%.b %1,%0")
\f
;; negation instructions
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
else
operands[1] = adj_offsettable_operand (operands[0], 4);
- if (ADDRESS_REG_P (operands[0]))
- return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
- else
- return \"neg%.l %1\;negx%.l %0\";
+ return \"neg%.l %1\;negx%.l %0\";
} ")
(define_insn "negsi2"
(define_insn "neghi2"
[(set (match_operand:HI 0 "general_operand" "=dm")
(neg:HI (match_operand:HI 1 "general_operand" "0")))]
- ""
+ "!TARGET_5200"
"neg%.w %0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
(neg:HI (match_dup 0)))]
- ""
+ "!TARGET_5200"
"neg%.w %0")
(define_insn "negqi2"
[(set (match_operand:QI 0 "general_operand" "=dm")
(neg:QI (match_operand:QI 1 "general_operand" "0")))]
- ""
+ "!TARGET_5200"
"neg%.b %0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
(neg:QI (match_dup 0)))]
- ""
+ "!TARGET_5200"
"neg%.b %0")
;; If using software floating point, just flip the sign bit.
(define_insn "one_cmplhi2"
[(set (match_operand:HI 0 "general_operand" "=dm")
(not:HI (match_operand:HI 1 "general_operand" "0")))]
- ""
+ "!TARGET_5200"
"not%.w %0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
(not:HI (match_dup 0)))]
- ""
+ "!TARGET_5200"
"not%.w %0")
(define_insn "one_cmplqi2"
[(set (match_operand:QI 0 "general_operand" "=dm")
(not:QI (match_operand:QI 1 "general_operand" "0")))]
- ""
+ "!TARGET_5200"
"not%.b %0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
(not:QI (match_dup 0)))]
- ""
+ "!TARGET_5200"
"not%.b %0")
\f
;; arithmetic shift instructions
[(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
- "(! TARGET_68020
+ "(! TARGET_68020 && !TARGET_5200
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
"*
{
[(set (match_operand:HI 0 "register_operand" "=d")
(ashift:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"lsl%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashift:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"lsl%.w %1,%0")
(define_insn "ashlqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashift:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"lsl%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashift:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"lsl%.b %1,%0")
;; On all 68k models, this makes faster code in a special case.
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
- "(! TARGET_68020
+ "(! TARGET_68020 && !TARGET_5200
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
"*
{
[(set (match_operand:DI 0 "general_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))]
- "(INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
+ "!TARGET_5200
+ && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
|| INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
- || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63)"
+ || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
"*
{
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashiftrt:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"asr%.w %1,%0")
(define_insn "ashrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"asr%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashiftrt:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"asr%.b %1,%0")
\f
;; logical shift instructions
[(set (match_operand:DI 0 "general_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
(match_operand 2 "const_int_operand" "n")))]
- "(INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
+ "!TARGET_5200
+ && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
|| INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
- || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63)"
+ || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
"*
{
operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
[(set (match_operand:DI 0 "general_operand" "")
(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
(match_operand 2 "const_int_operand" "")))]
- ""
+ "!TARGET_5200"
"
{
if (GET_CODE (operands[2]) != CONST_INT
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "const_int_operand" "n")))]
- "(! TARGET_68020
+ "(! TARGET_68020 && !TARGET_5200
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
"*
{
[(set (match_operand:HI 0 "register_operand" "=d")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"lsr%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(lshiftrt:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"lsr%.w %1,%0")
(define_insn "lshrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"lsr%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(lshiftrt:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"lsr%.b %1,%0")
\f
;; rotate instructions
[(set (match_operand:SI 0 "register_operand" "=d")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"rol%.l %2,%0")
(define_insn "rotlhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotate:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"rol%.w %2,%0")
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotate:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"rol%.w %1,%0")
(define_insn "rotlqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotate:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"rol%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotate:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"rol%.b %1,%0")
(define_insn "rotrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"ror%.l %2,%0")
(define_insn "rotrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotatert:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"ror%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotatert:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"ror%.w %1,%0")
(define_insn "rotrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotatert:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"ror%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotatert:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "dI")))]
- ""
+ "!TARGET_5200"
"ror%.b %1,%0")
\f
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))]
- ""
+ "!TARGET_5200"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))]
- ""
+ "!TARGET_5200"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))]
- "find_reg_note (insn, REG_NONNEG, 0)"
+ "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))]
- "find_reg_note (insn, REG_NONNEG, 0)"
+ "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
CC_STATUS_INIT;
rtx xoperands[2];
xoperands[0] = stack_pointer_rtx;
xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
+ if (TARGET_5200)
+ output_asm_insn (\"add%.l %1,%0\", xoperands);
+ else
#ifndef NO_ADDSUB_Q
if (INTVAL (xoperands[1]) <= 8)
output_asm_insn (\"addq%.w %1,%0\", xoperands);
rtx xoperands[2];
xoperands[0] = stack_pointer_rtx;
xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
+ if (TARGET_5200)
+ output_asm_insn (\"add%.l %1,%0\", xoperands);
+ else
#ifndef NO_ADDSUB_Q
if (INTVAL (xoperands[1]) <= 8)
- output_asm_insn (\"addq%.w %1,%0\", xoperands);
+ output_asm_insn (\"addq%.w %1,%0\", xoperands);
else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020)
{
xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
gen_rtx (CONST_INT, VOIDmode, 3)));
xoperands[3] = stack_pointer_rtx;
- output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
+ if (!TARGET_5200)
+ output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
+ else
+ output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
return \"\";
}")
(set (match_dup 0)
(plus:HI (match_dup 0)
(const_int -1)))])]
- "DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
"*
{
CC_STATUS_INIT;
(set (match_dup 0)
(plus:SI (match_dup 0)
(const_int -1)))])]
- "DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+ "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
"*
{
CC_STATUS_INIT;