* rl78-decode.c: Regenerate.
* config/rl78-parse.y: Fix encoding of DIVWU insn.
+2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
+
+ * config/rl78-parse.y: Fix encoding of DIVWU insn.
+
2013-02-25 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (arm_cpus): Add cortex-r7 entry.
/* rl78-parse.y Renesas RL78 parser
- Copyright 2011
- Free Software Foundation, Inc.
+ Copyright 2011-2013 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
| DIVHU
{ B3 (0xce, 0xfb, 0x03); }
+/* Note that the DIVWU encoding was changed from [0xce,0xfb,0x04] to
+ [0xce,0xfb,0x0b]. Different versions of the Software Manual exist
+ with the same version number, but varying encodings. The version
+ here matches the hardware. */
+
| DIVWU
- { B3 (0xce, 0xfb, 0x04); }
+ { B3 (0xce, 0xfb, 0x0b); }
| MACHU
{ B3 (0xce, 0xfb, 0x05); }
+2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
+
+ * rl78-decode.opc: Fix encoding of DIVWU insn.
+ * rl78-decode.c: Regenerate.
+
2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
PR gas/15159
#line 1 "rl78-decode.opc"
/* -*- c -*- */
-/* Copyright 2012 Free Software Foundation, Inc.
+/* Copyright 2012-2013 Free Software Foundation, Inc.
Contributed by Red Hat.
Written by DJ Delorie.
rl78->syntax = "divhu"; ID(divhu);
break;
case 0x04:
- rl78->syntax = "divwu"; ID(divwu);
+ rl78->syntax = "divwu <old-encoding>"; ID(divwu);
break;
case 0x05:
rl78->syntax = "machu"; ID(machu);
case 0x06:
rl78->syntax = "mach"; ID(mach);
break;
+ case 0x0b:
+ rl78->syntax = "divwu"; ID(divwu);
+ break;
}
-
- }
+ }
break;
case 0xcf:
{
/* -*- c -*- */
-/* Copyright 2012 Free Software Foundation, Inc.
+/* Copyright 2012-2013 Free Software Foundation, Inc.
Contributed by Red Hat.
Written by DJ Delorie.
rl78->syntax = "divhu"; ID(divhu);
break;
case 0x04:
- rl78->syntax = "divwu"; ID(divwu);
+ rl78->syntax = "divwu <old-encoding>" ID(divwu);
break;
case 0x05:
rl78->syntax = "machu"; ID(machu);
case 0x06:
rl78->syntax = "mach"; ID(mach);
break;
+ case 0x0b:
+ rl78->syntax = "divwu"; ID(divwu);
+ break;
}
/** 1001 1110 mov %0, %1 */