bool retry_cam_enabled;
};
+enum interrupt_node_id_per_xcp {
+ XCD0_NODEID = 1,
+ XCD1_NODEID = 2,
+ XCD2_NODEID = 5,
+ XCD3_NODEID = 6,
+ XCD4_NODEID = 9,
+ XCD5_NODEID = 10,
+ XCD6_NODEID = 13,
+ XCD7_NODEID = 14,
+ NODEID_MAX,
+};
+
+extern const int node_id_to_phys_map[NODEID_MAX];
+
void amdgpu_irq_disable_all(struct amdgpu_device *adev);
int amdgpu_irq_init(struct amdgpu_device *adev);
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
- int i;
+ int i, phys_id;
u8 me_id, pipe_id, queue_id;
struct amdgpu_ring *ring;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
+ phys_id = node_id_to_phys_map[entry->node_id];
+
switch (me_id) {
case 0:
case 1:
case 2:
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
- ring = &adev->gfx.compute_ring[i];
+ ring = &adev->gfx.compute_ring[i + phys_id * adev->gfx.num_compute_rings];
/* Per-queue interrupt is supported for MEC starting from VI.
* The interrupt can only be enabled/disabled per pipe instead of per queue.
*/