arm64: dts: sparx5: Add pinctrl support

This add pinctrl support to the Microchip Sparx5 SoC.

Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 4a54b7d..baf4176 100644 (file)
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -109,6 +109,8 @@
                };
 
                uart0: serial@600100000 {
+                       pinctrl-0 = <&uart_pins>;
+                       pinctrl-names = "default";
                        compatible = "ns16550a";
                        reg = <0x6 0x00100000 0x20>;
                        clocks = <&ahb_clk>;
@@ -120,6 +122,8 @@
                };
 
                uart1: serial@600102000 {
+                       pinctrl-0 = <&uart2_pins>;
+                       pinctrl-names = "default";
                        compatible = "ns16550a";
                        reg = <0x6 0x00102000 0x20>;
                        clocks = <&ahb_clk>;
@@ -138,5 +142,27 @@
                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               gpio: pinctrl@6110101e0 {
+                       compatible = "microchip,sparx5-pinctrl";
+                       reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&gpio 0 0 64>;
+                       interrupt-controller;
+                       interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                       #interrupt-cells = <2>;
+
+                       uart_pins: uart-pins {
+                               pins = "GPIO_10", "GPIO_11";
+                               function = "uart";
+                       };
+
+                       uart2_pins: uart2-pins {
+                               pins = "GPIO_26", "GPIO_27";
+                               function = "uart2";
+                       };
+
+               };
+
        };
 };

diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 005cf6b..9b2aec4 100644 (file)
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -7,4 +7,9 @@
 #include "sparx5_pcb_common.dtsi"
 
 /{
+       gpio-restart {
+               compatible = "gpio-restart";
+               gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+               priority = <200>;
+       };
 };

diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index 005cf6b..9b2aec4 100644 (file)
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -7,4 +7,9 @@
 #include "sparx5_pcb_common.dtsi"
 
 /{
+       gpio-restart {
+               compatible = "gpio-restart";
+               gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+               priority = <200>;
+       };
 };