void addReg(MCPhysReg Reg) {
assert(TRI && "LivePhysRegs is not initialized.");
assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- LiveRegs.insert(*SubRegs);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
+ LiveRegs.insert(SubReg);
}
/// Removes a physical register, all its sub-registers, and all its
// Definition for isSuperRegister. Put it down here since it needs the
// iterator defined above in addition to the MCRegisterInfo class itself.
inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{
- for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
- if (*I == RegB)
+ for (MCPhysReg I : superregs(RegA))
+ if (I == RegB)
return true;
return false;
}
if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) ||
IsImplicitDefUse(MI, MO)) {
const Register Reg = MO.getReg();
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- PassthruRegs.insert(*SubRegs);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
+ PassthruRegs.insert(SubReg);
}
}
}
// was not live because otherwise, regardless whether we have an explicit
// use of the subregister, the subregister's contents are needed for the
// uses of the superregister.
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubregReg = *SubRegs;
+ for (MCPhysReg SubregReg : TRI->subregs(Reg)) {
if (!State->IsLive(SubregReg)) {
KillIndices[SubregReg] = KillIdx;
DefIndices[SubregReg] = ~0u;
// Walk up the super-register chain until we find a valid number.
// For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
- for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
- Reg = TRI.getDwarfRegNum(*SR, false);
+ for (MCPhysReg SR : TRI.superregs(MachineReg)) {
+ Reg = TRI.getDwarfRegNum(SR, false);
if (Reg >= 0) {
- unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
+ unsigned Idx = TRI.getSubRegIndex(SR, MachineReg);
unsigned Size = TRI.getSubRegIdxSize(Idx);
unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));
// this doesn't find a combination of subregisters that fully cover
// the register (even though one may exist).
SmallBitVector Coverage(RegSize, false);
- for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
- unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
+ for (MCPhysReg SR : TRI.subregs(MachineReg)) {
+ unsigned Idx = TRI.getSubRegIndex(MachineReg, SR);
unsigned Size = TRI.getSubRegIdxSize(Idx);
unsigned Offset = TRI.getSubRegIdxOffset(Idx);
- Reg = TRI.getDwarfRegNum(*SR, false);
+ Reg = TRI.getDwarfRegNum(SR, false);
if (Reg < 0)
continue;
} else {
if (Uses.erase(Reg)) {
if (Reg.isPhysical()) {
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
- Uses.erase(*SubRegs); // Use sub-registers to be conservative
+ for (MCPhysReg SubReg : TRI->subregs(Reg))
+ Uses.erase(SubReg); // Use sub-registers to be conservative
}
}
addRegAndItsAliases(Reg, TRI, Defs);
if (MO.isUse() && Special) {
if (!KeepRegs.test(Reg)) {
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- KeepRegs.set(*SubRegs);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
+ KeepRegs.set(SubReg);
}
}
}
// itself can't be changed.
if (MI.isRegTiedToUseOperand(I) &&
Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs) {
- KeepRegs.set(*SubRegs);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
+ KeepRegs.set(SubReg);
}
- for (MCSuperRegIterator SuperRegs(Reg, TRI);
- SuperRegs.isValid(); ++SuperRegs) {
- KeepRegs.set(*SuperRegs);
+ for (MCPhysReg SuperReg : TRI->superregs(Reg)) {
+ KeepRegs.set(SuperReg);
}
}
}
if (MO.isRegMask()) {
auto ClobbersPhysRegAndSubRegs = [&](unsigned PhysReg) {
- for (MCSubRegIterator SRI(PhysReg, TRI, true); SRI.isValid(); ++SRI)
- if (!MO.clobbersPhysReg(*SRI))
+ for (MCPhysReg SR : TRI->subregs_inclusive(PhysReg))
+ if (!MO.clobbersPhysReg(SR))
return false;
return true;
// For the reg itself and all subregs: update the def to current;
// reset the kill state, any restrictions, and references.
- for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) {
- unsigned SubregReg = *SRI;
+ for (MCPhysReg SubregReg : TRI->subregs_inclusive(Reg)) {
DefIndices[SubregReg] = Count;
KillIndices[SubregReg] = ~0u;
Classes[SubregReg] = nullptr;
KeepRegs.reset(SubregReg);
}
// Conservatively mark super-registers as unusable.
- for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
- Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
+ for (MCPhysReg SR : TRI->superregs(Reg))
+ Classes[SR] = reinterpret_cast<TargetRegisterClass *>(-1);
}
}
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MIB.addReg(Reg, RegState::Implicit);
else {
bool HasLiveSubReg = false;
- for (MCSubRegIterator S(Reg, TRI); S.isValid(); ++S) {
- if (!LiveBeforeMI.count(*S))
+ for (MCPhysReg S : TRI->subregs(Reg)) {
+ if (!LiveBeforeMI.count(S))
continue;
HasLiveSubReg = true;
break;
} else if (!RedefsByFalse.count(Reg)) {
// These are defined before ctrl flow reach the 'false' instructions.
// They cannot be modified by the 'true' instructions.
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- ExtUses.insert(*SubRegs);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
+ ExtUses.insert(SubReg);
}
}
for (MCPhysReg Reg : Defs) {
if (!ExtUses.count(Reg)) {
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- RedefsByFalse.insert(*SubRegs);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
+ RedefsByFalse.insert(SubReg);
}
}
}
if (Size != MainRegSize || Offset) {
// Enumerate all subregisters, searching.
Register NewReg = 0;
- for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) {
- unsigned Subreg = TRI->getSubRegIndex(Reg, *SRI);
+ for (MCPhysReg SR : TRI->subregs(Reg)) {
+ unsigned Subreg = TRI->getSubRegIndex(Reg, SR);
unsigned SubregSize = TRI->getSubRegIdxSize(Subreg);
unsigned SubregOffset = TRI->getSubRegIdxOffset(Subreg);
if (SubregSize == Size && SubregOffset == Offset) {
- NewReg = *SRI;
+ NewReg = SR;
break;
}
}
};
// Then, transfer subreg bits.
- for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) {
+ for (MCPhysReg SR : TRI->subregs(Reg)) {
// Ensure this reg is tracked,
- (void)MTracker->lookupOrTrackRegister(*SRI);
- unsigned SubregIdx = TRI->getSubRegIndex(Reg, *SRI);
+ (void)MTracker->lookupOrTrackRegister(SR);
+ unsigned SubregIdx = TRI->getSubRegIndex(Reg, SR);
unsigned SpillID = MTracker->getLocID(Loc, SubregIdx);
- DoTransfer(*SRI, SpillID);
+ DoTransfer(SR, SpillID);
}
// Directly lookup size of main source reg, and transfer.
MTracker->setReg(DestReg, ReadValue);
};
- for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) {
- unsigned Subreg = TRI->getSubRegIndex(Reg, *SRI);
+ for (MCPhysReg SR : TRI->subregs(Reg)) {
+ unsigned Subreg = TRI->getSubRegIndex(Reg, SR);
unsigned SpillID = MTracker->getLocID(*Loc, Subreg);
- DoTransfer(*SRI, SpillID);
+ DoTransfer(SR, SpillID);
}
// Directly look up this registers slot idx by size, and transfer.
bool IsReserved = false;
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
bool IsRootReserved = true;
- for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
- Super.isValid(); ++Super) {
- MCRegister Reg = *Super;
+ for (MCPhysReg Reg : TRI->superregs_inclusive(*Root)) {
if (!MRI->reg_empty(Reg))
LICalc->createDeadDefs(LR, Reg);
// A register unit is considered reserved if all its roots and all their
// Ignore uses of reserved registers. We only track defs of those.
if (!IsReserved) {
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
- for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
- Super.isValid(); ++Super) {
- MCRegister Reg = *Super;
+ for (MCPhysReg Reg : TRI->superregs_inclusive(*Root)) {
if (!MRI->reg_empty(Reg))
LICalc->extendToUses(LR, Reg);
}
continue;
// Skip the register if we are about to add one of its super registers.
bool ContainsSuperReg = false;
- for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
- if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
+ for (MCPhysReg SReg : TRI.superregs(Reg)) {
+ if (LiveRegs.contains(SReg) && !MRI.isReserved(SReg)) {
ContainsSuperReg = true;
break;
}
unsigned LastDefReg = 0;
unsigned LastDefDist = 0;
MachineInstr *LastDef = nullptr;
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs(Reg)) {
MachineInstr *Def = PhysRegDef[SubReg];
if (!Def)
continue;
continue;
Register DefReg = MO.getReg();
if (TRI->isSubRegister(Reg, DefReg)) {
- for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- PartDefRegs.insert(*SubRegs);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg))
+ PartDefRegs.insert(SubReg);
}
}
return LastDef;
true/*IsImp*/));
PhysRegDef[Reg] = LastPartialDef;
SmallSet<unsigned, 8> Processed;
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs(Reg)) {
if (Processed.count(SubReg))
continue;
if (PartDefRegs.count(SubReg))
false/*IsDef*/,
true/*IsImp*/));
PhysRegDef[SubReg] = LastPartialDef;
- for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
- Processed.insert(*SS);
+ for (MCPhysReg SS : TRI->subregs(SubReg))
+ Processed.insert(SS);
}
}
} else if (LastDef && !PhysRegUse[Reg] &&
true/*IsImp*/));
// Remember this use.
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- PhysRegUse[*SubRegs] = &MI;
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
+ PhysRegUse[SubReg] = &MI;
}
/// FindLastRefOrPartRef - Return the last reference or partial reference of
MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
unsigned LastPartDefDist = 0;
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs(Reg)) {
MachineInstr *Def = PhysRegDef[SubReg];
if (Def && Def != LastDef) {
// There was a def of this sub-register in between. This is a partial
MachineInstr *LastPartDef = nullptr;
unsigned LastPartDefDist = 0;
SmallSet<unsigned, 8> PartUses;
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs(Reg)) {
MachineInstr *Def = PhysRegDef[SubReg];
if (Def && Def != LastDef) {
// There was a def of this sub-register in between. This is a partial
continue;
}
if (MachineInstr *Use = PhysRegUse[SubReg]) {
- for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true); SS.isValid();
- ++SS)
- PartUses.insert(*SS);
+ for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
+ PartUses.insert(SS);
unsigned Dist = DistanceMap[Use];
if (Dist > LastRefOrPartRefDist) {
LastRefOrPartRefDist = Dist;
// dead EAX = op implicit-def AL
// That is, EAX def is dead but AL def extends pass it.
PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs(Reg)) {
if (!PartUses.count(SubReg))
continue;
bool NeedDef = true;
LastSubRef->addRegisterKilled(SubReg, TRI, true);
else {
LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
- for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
- SS.isValid(); ++SS)
- PhysRegUse[*SS] = LastRefOrPartRef;
+ for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
+ PhysRegUse[SS] = LastRefOrPartRef;
}
- for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
- PartUses.erase(*SS);
+ for (MCPhysReg SS : TRI->subregs(SubReg))
+ PartUses.erase(SS);
}
} else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
if (LastPartDef)
// Kill the largest clobbered super-register.
// This avoids needless implicit operands.
unsigned Super = Reg;
- for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
- if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
- Super = *SR;
+ for (MCPhysReg SR : TRI->superregs(Reg))
+ if ((PhysRegDef[SR] || PhysRegUse[SR]) && MO.clobbersPhysReg(SR))
+ Super = SR;
HandlePhysRegKill(Super, nullptr);
}
}
// What parts of the register are previously defined?
SmallSet<unsigned, 32> Live;
if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- Live.insert(*SubRegs);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
+ Live.insert(SubReg);
} else {
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs(Reg)) {
// If a register isn't itself defined, but all parts that make up of it
// are defined, then consider it also defined.
// e.g.
if (Live.count(SubReg))
continue;
if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
- for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true);
- SS.isValid(); ++SS)
- Live.insert(*SS);
+ for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
+ Live.insert(SS);
}
}
}
// is referenced.
HandlePhysRegKill(Reg, MI);
// Only some of the sub-registers are used.
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs(Reg)) {
if (!Live.count(SubReg))
// Skip if this sub-register isn't defined.
continue;
SmallVectorImpl<unsigned> &Defs) {
while (!Defs.empty()) {
Register Reg = Defs.pop_back_val();
- for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
PhysRegDef[SubReg] = &MI;
PhysRegUse[SubReg] = nullptr;
}
// Saved CSRs are not pristine.
for (const auto &I : getCalleeSavedInfo())
- for (MCSubRegIterator S(I.getReg(), TRI, true); S.isValid(); ++S)
- BV.reset(*S);
+ for (MCPhysReg S : TRI->subregs_inclusive(I.getReg()))
+ BV.reset(S);
return BV;
}
}
if (!MO.isDead() && Reg.isPhysical()) {
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- unsigned SubReg = *SubRegs;
+ for (MCPhysReg SubReg : TRI->subregs(Reg)) {
if (LocalDefSet.insert(SubReg).second)
LocalDefs.push_back(SubReg);
}
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
bool IsRootReserved = true;
- for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
- Super.isValid(); ++Super) {
- MCRegister Reg = *Super;
+ for (MCPhysReg Super : TRI->superregs_inclusive(*Root)) {
+ MCRegister Reg = Super;
if (!isReserved(Reg)) {
IsRootReserved = false;
break;
MachineFunction &MF = *SuccBB->getParent();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
for (unsigned DefReg : DefedRegsInCopy)
- for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)
- SuccBB->removeLiveIn(*S);
+ for (MCPhysReg S : TRI->subregs_inclusive(DefReg))
+ SuccBB->removeLiveIn(S);
for (auto U : UsedOpsInCopy) {
Register SrcReg = MI->getOperand(U).getReg();
LaneBitmask Mask;
Register R = Op.getReg();
if (!R.isPhysical())
continue;
- for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
- Live.reset(*SR);
+ for (MCPhysReg SR : TRI.subregs_inclusive(R))
+ Live.reset(SR);
}
for (auto &Op : MI.operands()) {
if (!Op.isReg() || !Op.isUse() || Op.isUndef())
}
if (!IsLive)
Op.setIsKill(true);
- for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
- Live.set(*SR);
+ for (MCPhysReg SR : TRI.subregs_inclusive(R))
+ Live.set(SR);
}
}
}
for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
BitVector AS(TRI.getNumRegs());
for (MCRegUnitRootIterator R(U, &TRI); R.isValid(); ++R)
- for (MCSuperRegIterator S(*R, &TRI, true); S.isValid(); ++S)
- AS.set(*S);
+ for (MCPhysReg S : TRI.superregs_inclusive(*R))
+ AS.set(S);
AliasInfos[U].Regs = AS;
}
}
MCPhysReg Reg = CSRegs[i];
if (SavedRegs.test(Reg)) {
// Save subregisters
- for (MCSubRegIterator SR(Reg, &TRI); SR.isValid(); ++SR)
- SavedRegs.set(*SR);
+ for (MCPhysReg SR : TRI.subregs(Reg))
+ SavedRegs.set(SR);
}
}
}
break;
}
bool SuperUsed = false;
- for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
- if (isRegUsed(*SR)) {
+ for (MCPhysReg SR : TRI->superregs(Reg)) {
+ if (isRegUsed(SR)) {
SuperUsed = true;
break;
}
addPhysRegDataDeps(SU, OperIdx);
// Clear previous uses and defs of this register and its subergisters.
- for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) {
- if (Uses.contains(*SubReg))
- Uses.eraseAll(*SubReg);
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
+ if (Uses.contains(SubReg))
+ Uses.eraseAll(SubReg);
if (!MO.isDead())
- Defs.eraseAll(*SubReg);
+ Defs.eraseAll(SubReg);
}
if (MO.isDead() && SU->isCall) {
// Calls will not be reordered because of chain dependencies (see
/// Go up the super-register chain until we hit a valid dwarf register number.
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
int RegNum = TRI->getDwarfRegNum(Reg, false);
- for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
- RegNum = TRI->getDwarfRegNum(*SR, false);
+ for (MCPhysReg SR : TRI->superregs(Reg)) {
+ if (RegNum >= 0)
+ break;
+ RegNum = TRI->getDwarfRegNum(SR, false);
+ }
assert(RegNum >= 0 && "Invalid Dwarf register number.");
return (unsigned)RegNum;
void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,
MCRegister Reg) const {
- for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
- RegisterSet.set(*AI);
+ for (MCPhysReg SR : superregs_inclusive(Reg))
+ RegisterSet.set(SR);
}
bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
for (unsigned Reg : RegisterSet.set_bits()) {
if (Checked[Reg])
continue;
- for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
- if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
- dbgs() << "Error: Super register " << printReg(*SR, this)
+ for (MCPhysReg SR : superregs(Reg)) {
+ if (!RegisterSet[SR] && !is_contained(Exceptions, Reg)) {
+ dbgs() << "Error: Super register " << printReg(SR, this)
<< " of reserved register " << printReg(Reg, this)
<< " is not reserved.\n";
return false;
// We transitively check superregs. So we can remember this for later
// to avoid compiletime explosion in deep register hierarchies.
- Checked.set(*SR);
+ Checked.set(SR);
}
}
return true;
MCRegister
MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
const MCRegisterClass *RC) const {
- for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
- if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
- return *Supers;
+ for (MCPhysReg Super : superregs(Reg))
+ if (RC->contains(Super) && Reg == getSubReg(Super, SubIdx))
+ return Super;
return 0;
}
// Get a pointer to the corresponding SubRegIndices list. This list has the
// name of each sub-register in the same order as MCSubRegIterator.
const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
- for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
+ for (MCPhysReg Sub : subregs(Reg)) {
if (*SRI == Idx)
- return *Subs;
+ return Sub;
+ ++SRI;
+ }
return 0;
}
// Get a pointer to the corresponding SubRegIndices list. This list has the
// name of each sub-register in the same order as MCSubRegIterator.
const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
- for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
- if (*Subs == SubReg)
+ for (MCPhysReg Sub : subregs(Reg)) {
+ if (Sub == SubReg)
return *SRI;
+ ++SRI;
+ }
return 0;
}
if (WR.getWriteState() == &WS)
WR.notifyExecuted(CurrentCycle);
- for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
- WriteRef &OtherWR = RegisterMappings[*I].first;
+ for (MCPhysReg I : MRI.subregs(RegID)) {
+ WriteRef &OtherWR = RegisterMappings[I].first;
if (OtherWR.getWriteState() == &WS)
OtherWR.notifyExecuted(CurrentCycle);
}
if (!WS.clearsSuperRegisters())
continue;
- for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {
- WriteRef &OtherWR = RegisterMappings[*I].first;
+ for (MCPhysReg I : MRI.superregs(RegID)) {
+ WriteRef &OtherWR = RegisterMappings[I].first;
if (OtherWR.getWriteState() == &WS)
OtherWR.notifyExecuted(CurrentCycle);
}
Entry.AllowMoveElimination = RCE.AllowMoveElimination;
// Assume the same cost for each sub-register.
- for (MCSubRegIterator I(Reg, &MRI); I.isValid(); ++I) {
- RegisterRenamingInfo &OtherEntry = RegisterMappings[*I].second;
+ for (MCPhysReg I : MRI.subregs(Reg)) {
+ RegisterRenamingInfo &OtherEntry = RegisterMappings[I].second;
if (!OtherEntry.IndexPlusCost.first &&
(!OtherEntry.RenameAs ||
- MRI.isSuperRegister(*I, OtherEntry.RenameAs))) {
+ MRI.isSuperRegister(I, OtherEntry.RenameAs))) {
OtherEntry.IndexPlusCost = IPC;
OtherEntry.RenameAs = Reg;
}
MCPhysReg ZeroRegisterID =
WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();
ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero);
- for (MCSubRegIterator I(ZeroRegisterID, &MRI); I.isValid(); ++I)
- ZeroRegisters.setBitVal(*I, IsWriteZero);
+ for (MCPhysReg I : MRI.subregs(ZeroRegisterID))
+ ZeroRegisters.setBitVal(I, IsWriteZero);
// If this move has been eliminated, then method tryEliminateMoveOrSwap should
// have already updated all the register mappings.
// Update the mapping for register RegID including its sub-registers.
RegisterMappings[RegID].first = Write;
RegisterMappings[RegID].second.AliasRegID = 0U;
- for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
- RegisterMappings[*I].first = Write;
- RegisterMappings[*I].second.AliasRegID = 0U;
+ for (MCPhysReg I : MRI.subregs(RegID)) {
+ RegisterMappings[I].first = Write;
+ RegisterMappings[I].second.AliasRegID = 0U;
}
// No physical registers are allocated for instructions that are optimized
if (!WS.clearsSuperRegisters())
return;
- for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {
+ for (MCPhysReg I : MRI.superregs(RegID)) {
if (!IsEliminated) {
- RegisterMappings[*I].first = Write;
- RegisterMappings[*I].second.AliasRegID = 0U;
+ RegisterMappings[I].first = Write;
+ RegisterMappings[I].second.AliasRegID = 0U;
}
- ZeroRegisters.setBitVal(*I, IsWriteZero);
+ ZeroRegisters.setBitVal(I, IsWriteZero);
}
}
if (WR.getWriteState() == &WS)
WR.commit();
- for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
- WriteRef &OtherWR = RegisterMappings[*I].first;
+ for (MCPhysReg I : MRI.subregs(RegID)) {
+ WriteRef &OtherWR = RegisterMappings[I].first;
if (OtherWR.getWriteState() == &WS)
OtherWR.commit();
}
if (!WS.clearsSuperRegisters())
return;
- for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {
- WriteRef &OtherWR = RegisterMappings[*I].first;
+ for (MCPhysReg I : MRI.superregs(RegID)) {
+ WriteRef &OtherWR = RegisterMappings[I].first;
if (OtherWR.getWriteState() == &WS)
OtherWR.commit();
}
AliasedReg = RMAlias.AliasRegID;
RegisterMappings[AliasReg].second.AliasRegID = AliasedReg;
- for (MCSubRegIterator I(AliasReg, &MRI); I.isValid(); ++I)
- RegisterMappings[*I].second.AliasRegID = AliasedReg;
+ for (MCPhysReg I : MRI.subregs(AliasReg))
+ RegisterMappings[I].second.AliasRegID = AliasedReg;
if (ZeroRegisters[RS.getRegisterID()]) {
WS.setWriteZero();
}
// Handle potential partial register updates.
- for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
- const WriteRef &WR = RegisterMappings[*I].first;
+ for (MCPhysReg I : MRI.subregs(RegID)) {
+ const WriteRef &WR = RegisterMappings[I].first;
if (WR.getWriteState()) {
Writes.push_back(WR);
} else if (WR.hasKnownWriteBackCycle()) {
for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
if (MF.getSubtarget<AArch64Subtarget>().isXRegCustomCalleeSaved(i)) {
- for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i),
- this, true);
- SubReg.isValid(); ++SubReg) {
+ for (MCPhysReg SubReg :
+ subregs_inclusive(AArch64::GPR64commonRegClass.getRegister(i))) {
// See TargetRegisterInfo::getCallPreservedMask for how to interpret the
// register mask.
- UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32);
+ UpdatedMask[SubReg / 32] |= 1u << (SubReg % 32);
}
}
}
// SME tiles are not allocatable.
if (MF.getSubtarget<AArch64Subtarget>().hasSME()) {
- for (MCSubRegIterator SubReg(AArch64::ZA, this, /*self=*/true);
- SubReg.isValid(); ++SubReg)
- Reserved.set(*SubReg);
+ for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA))
+ Reserved.set(SubReg);
}
markSuperRegs(Reserved, AArch64::FPCR);
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
// Find the 'd' register that has this 's' register as a sub-register,
// and determine the lane number.
- for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
- if (!ARM::DPRRegClass.contains(*SR))
+ for (MCPhysReg SR : TRI->superregs(Reg)) {
+ if (!ARM::DPRRegClass.contains(SR))
continue;
- bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
- O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
+ bool Lane0 = TRI->getSubReg(SR, ARM::ssub_0) == Reg;
+ O << ARMInstPrinter::getRegisterName(SR) << (Lane0 ? "[0]" : "[1]");
return false;
}
}
}
const TargetRegisterClass &RC = ARM::GPRPairRegClass;
for (unsigned Reg : RC)
- for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI)
- if (Reserved.test(*SI))
+ for (MCPhysReg S : subregs(Reg))
+ if (Reserved.test(S))
markSuperRegs(Reserved, Reg);
// For v8.1m architecture
markSuperRegs(Reserved, ARM::ZR);
// Get the other register in a GPRPair.
static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd,
const MCRegisterInfo *RI) {
- for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
- if (ARM::GPRPairRegClass.contains(*Supers))
- return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
+ for (MCPhysReg Super : RI->superregs(Reg))
+ if (ARM::GPRPairRegClass.contains(Super))
+ return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0);
return 0;
}
auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
for (unsigned Reg : Regs)
- for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
- Subreg.isValid(); ++Subreg)
- UsesDefs.insert(*Subreg);
+ for (MCPhysReg Subreg : TRI->subregs_inclusive(Reg))
+ UsesDefs.insert(Subreg);
};
InsertUsesDefs(LocalDefs, Defs);
// Otherwise, return true if any aliased SuperReg of GPR32 is not dead.
for (auto I : GPR32LiveDefs)
- for (MCSuperRegIterator SR(I, TRI); SR.isValid(); ++SR)
- if (!llvm::is_contained(GPR64DeadDefs, *SR))
+ for (MCPhysReg SR : TRI->superregs(I))
+ if (!llvm::is_contained(GPR64DeadDefs, SR))
return true;
return false;
inline static unsigned getHexagonRegisterPair(unsigned Reg,
const MCRegisterInfo *RI) {
assert(Hexagon::IntRegsRegClass.contains(Reg));
- MCSuperRegIterator SR(Reg, RI, false);
- unsigned Pair = *SR;
+ unsigned Pair = *RI->superregs(Reg).begin();
assert(Hexagon::DoubleRegsRegClass.contains(Pair));
return Pair;
}
}
if (R.Reg.isPhysical()) {
- MCSubRegIterator I(R.Reg, &TRI);
- if (!I.isValid())
+ if (TRI.subregs(R.Reg).empty())
SRs.insert({R.Reg, 0});
- for (; I.isValid(); ++I)
- SRs.insert({*I, 0});
+ for (MCPhysReg I : TRI.subregs(R.Reg))
+ SRs.insert({I, 0});
} else {
assert(R.Reg.isVirtual());
auto &RC = *MRI.getRegClass(R.Reg);
// Skip registers that have subregisters. A register is preserved
// iff its bit is set in the regmask, so if R1:0 was preserved, both
// R1 and R0 would also be present.
- if (MCSubRegIterator(PR, &TRI, false).isValid())
+ if (!TRI.subregs(PR).empty())
continue;
if (Reserved[PR])
continue;
// Update maps for defs.
for (RegisterRef S : Defs) {
// Defs should already be expanded into subregs.
- assert(!S.Reg.isPhysical() ||
- !MCSubRegIterator(S.Reg, &TRI, false).isValid());
+ assert(!S.Reg.isPhysical() || TRI.subregs(S.Reg).empty());
if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None)
closeRange(S);
LastDef[S] = Index;
// Update maps for clobbers.
for (RegisterRef S : Clobbers) {
// Clobbers should already be expanded into subregs.
- assert(!S.Reg.isPhysical() ||
- !MCSubRegIterator(S.Reg, &TRI, false).isValid());
+ assert(!S.Reg.isPhysical() || TRI.subregs(S.Reg).empty());
if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None)
closeRange(S);
// Create a single-instruction range.
continue;
Register Reg = Op.getReg();
if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
- for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
- LastDef[*SubRegs] = &MI;
+ for (MCPhysReg SubReg : TRI->subregs(Reg))
+ LastDef[SubReg] = &MI;
} else if (Hexagon::IntRegsRegClass.contains(Reg))
LastDef[Reg] = &MI;
} else if (Op.isRegMask()) {
return Reg;
Register RegNo = 0;
- for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
+ for (MCPhysReg SubReg : TRI.subregs(Reg)) {
if (hireg) {
- if (*SubRegs > RegNo)
- RegNo = *SubRegs;
+ if (SubReg > RegNo)
+ RegNo = SubReg;
} else {
- if (!RegNo || *SubRegs < RegNo)
- RegNo = *SubRegs;
+ if (!RegNo || SubReg < RegNo)
+ RegNo = SubReg;
}
}
return RegNo;
// a stack slot.
if (R.isVirtual())
return true;
- for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
- if (CSR[*S])
+ for (MCPhysReg S : HRI.subregs_inclusive(R))
+ if (CSR[S])
return true;
continue;
}
SmallVector<MachineBasicBlock*,16> SFBlocks;
BitVector CSR(Hexagon::NUM_TARGET_REGS);
for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
- for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
- CSR[*S] = true;
+ for (MCPhysReg S : HRI.subregs_inclusive(*P))
+ CSR[S] = true;
for (auto &I : MF)
if (needsStackFrame(I, CSR, HRI))
for (const CalleeSavedInfo &I : CSI) {
Register R = I.getReg();
LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
- for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
- SRegs[*SR] = true;
+ for (MCPhysReg SR : TRI->subregs_inclusive(R))
+ SRegs[SR] = true;
}
LLVM_DEBUG(dbgs() << " }\n");
LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
if (AP.isValid()) {
Reserved[AP] = false;
// Unreserve super-regs if no other subregisters are reserved.
- for (MCSuperRegIterator SP(AP, TRI, false); SP.isValid(); ++SP) {
+ for (MCPhysReg SP : TRI->superregs(AP)) {
bool HasResSub = false;
- for (MCSubRegIterator SB(*SP, TRI, false); SB.isValid(); ++SB) {
- if (!Reserved[*SB])
+ for (MCPhysReg SB : TRI->subregs(SP)) {
+ if (!Reserved[SB])
continue;
HasResSub = true;
break;
}
if (!HasResSub)
- Reserved[*SP] = false;
+ Reserved[SP] = false;
}
}
for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
Register R = x;
- for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
- SRegs[*SR] = false;
+ for (MCPhysReg SR : TRI->superregs_inclusive(R))
+ SRegs[SR] = false;
}
LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
dbgs() << "\n");
BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
Register R = x;
- for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
- TmpSup[*SR] = true;
+ for (MCPhysReg SR : TRI->superregs(R))
+ TmpSup[SR] = true;
}
for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
Register R = x;
- for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
- if (!Reserved[*SR])
+ for (MCPhysReg SR : TRI->subregs_inclusive(R)) {
+ if (!Reserved[SR])
continue;
TmpSup[R] = false;
break;
// remove R from SRegs.
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
Register R = x;
- for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
- if (!SRegs[*SR])
+ for (MCPhysReg SR : TRI->superregs(R)) {
+ if (!SRegs[SR])
continue;
SRegs[R] = false;
break;
"Hexagon generate mux instructions", false, false)
void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const {
- for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I)
- SRs[*I] = true;
+ for (MCPhysReg I : HRI->subregs(Reg))
+ SRs[I] = true;
}
void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const {
LivePhysRegs LPR(*HRI);
LPR.addLiveOuts(B);
- auto IsLive = [&LPR,this] (unsigned Reg) -> bool {
- for (MCSubRegIterator S(Reg, HRI, true); S.isValid(); ++S)
- if (LPR.contains(*S))
+ auto IsLive = [&LPR, this](unsigned Reg) -> bool {
+ for (MCPhysReg S : HRI->subregs_inclusive(Reg))
+ if (LPR.contains(S))
return true;
return false;
};
return true;
if (RegA.isPhysical())
- for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
- if (RegB == *SubRegs)
+ for (MCPhysReg SubReg : HRI.subregs(RegA))
+ if (RegB == SubReg)
return true;
if (RegB.isPhysical())
- for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
- if (RegA == *SubRegs)
+ for (MCPhysReg SubReg : HRI.subregs(RegB))
+ if (RegA == SubReg)
return true;
}
if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
if (DefMO.isImplicit()) {
- for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
- int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
+ for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) {
+ int Idx = DefMI.findRegisterDefOperandIdx(SR, false, false, &HRI);
if (Idx != -1) {
DefIdx = Idx;
break;
const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
if (UseMO.isImplicit()) {
- for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
- int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
+ for (MCPhysReg SR : HRI.superregs(UseMO.getReg())) {
+ int Idx = UseMI.findRegisterUseOperandIdx(SR, false, &HRI);
if (Idx != -1) {
UseIdx = Idx;
break;
} else
// Note register use. Super-registers are not tracked directly,
// but their components.
- for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
- SRI.isValid(); ++SRI)
- if (!MCSubRegIterator(*SRI, &RI).isValid())
+ for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid();
+ ++SRI)
+ if (RI.subregs(*SRI).empty())
// Skip super-registers used indirectly.
Uses.insert(*SRI);
// Note register definitions, direct ones as well as indirect side-effects.
// Super-registers are not tracked directly, but their components.
- for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
- SRI.isValid(); ++SRI) {
- if (MCSubRegIterator(*SRI, &RI).isValid())
+ for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid();
+ ++SRI) {
+ if (!RI.subregs(*SRI).empty())
// Skip super-registers defined indirectly.
continue;
unsigned
M68kRegisterInfo::getMatchingMegaReg(unsigned Reg,
const TargetRegisterClass *RC) const {
- for (MCSuperRegIterator Super(Reg, this); Super.isValid(); ++Super)
+ for (MCPhysReg Super : superregs(Reg))
if (RC->contains(*Super))
return *Super;
return 0;
for (MCRegAliasIterator I(Reg, this, /* self */ true); I.isValid(); ++I) {
Reserved.set(*I);
}
- for (MCSubRegIterator I(Reg, this, /* self */ true); I.isValid(); ++I) {
+ for (MCPhysReg I : subregs_inclusive(Reg)) {
Reserved.set(*I);
}
};
for (; MII != MEE; ++MII) {
for (const MachineOperand &MO : MII->operands())
if (MO.isReg() && MO.getReg().isPhysical()) {
- for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
- SI.isValid(); ++SI)
- if (NewRC->contains(*SI)) {
- PhysClobbered.set(*SI);
+ for (MCPhysReg SI : superregs_inclusive(MO.getReg()))
+ if (NewRC->contains(SI)) {
+ PhysClobbered.set(SI);
break;
}
}
// In some calling conventions we need to remove the used registers
// from the register mask.
if (RegMask) {
- for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(VA.getLocReg()))
+ RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
}
// Report an error if there was an attempt to return FP values via XMM
// in the RegMask.
if (ShouldDisableArgRegs) {
for (auto const &RegPair : RegsToPass)
- for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true);
- SubRegs.isValid(); ++SubRegs)
- RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
+ for (MCPhysReg SubReg : TRI->subregs_inclusive(RegPair.first))
+ RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
}
// Create the RegMask Operand according to our updated mask.