PowerPC VLE

VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE.  For
example
{"evaddw",  VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe.  Also, we don't check
user assembly against the processor type as well as we could.

Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31.  Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.

This patch fixes those problems in the opcode table, and removes
PPCNONE.  I find a plain 0 distracts less from other values.

In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects.  It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.

include/
	* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
	PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
	PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
	PPC_APUINFO_VLE: Define.
opcodes/
	* ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
	cpu for "vle" to e500.
	* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
	(PPCNONE): Delete, substitute throughout.
	(powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
	except for major opcode 4 and 31.
	(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
	* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
	to match other 32-bit archs.
	* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
	(ppc_elf_object_p): Call it.
	(ppc_elf_special_sections): Use APUINFO_SECTION_NAME.  Fix
	overlong line.
	(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
	* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
	* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
	_bfd_elf_ppc_at_tprel_transform): Move to..
	* elf-bfd.h: ..here.
	(_bfd_elf_ppc_set_arch): Declare.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
	PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
	PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
	(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
	by vle_opcodes, and that vle flag doesn't enable opcodes.  Don't
	add vle_opcodes twice.
	(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
	* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
	* testsuite/ld-powerpc/apuinfo-vle2.s: New.
	* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 857caea..fb66662 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,19 @@
+2016-06-07  Alan Modra  <amodra@gmail.com>
+
+       * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
+       to match other 32-bit archs.
+       * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
+       (ppc_elf_object_p): Call it.
+       (ppc_elf_special_sections): Use APUINFO_SECTION_NAME.  Fix
+       overlong line.
+       (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
+       * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
+       * bfd-in.h (_bfd_elf_ppc_at_tls_transform,
+       _bfd_elf_ppc_at_tprel_transform): Move to..
+       * elf-bfd.h: ..here.
+       (_bfd_elf_ppc_set_arch): Declare.
+       * bfd-in2.h: Regenerate.
+
 2016-06-06  H.J. Lu  <hongjiu.lu@intel.com>
 
        * elf64-x86-64.c (elf_x86_64_link_hash_entry): Add tls_get_addr.

diff --git a/bfd/bfd-in.h b/bfd/bfd-in.h
index 196bd70..656d991 100644 (file)
--- a/bfd/bfd-in.h
+++ b/bfd/bfd-in.h
@@ -951,13 +951,6 @@ extern bfd_boolean elf32_arm_fix_exidx_coverage
 extern bfd_boolean elf32_tic6x_fix_exidx_coverage
 (struct bfd_section **, unsigned int, struct bfd_link_info *, bfd_boolean);
 
-/* PowerPC @tls opcode transform/validate.  */
-extern unsigned int _bfd_elf_ppc_at_tls_transform
-  (unsigned int, unsigned int);
-/* PowerPC @tprel opcode transform/validate.  */
-extern unsigned int _bfd_elf_ppc_at_tprel_transform
-  (unsigned int, unsigned int);
-
 extern void bfd_elf64_aarch64_init_maps
   (bfd *);
 

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 7292492..b536a59 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -958,13 +958,6 @@ extern bfd_boolean elf32_arm_fix_exidx_coverage
 extern bfd_boolean elf32_tic6x_fix_exidx_coverage
 (struct bfd_section **, unsigned int, struct bfd_link_info *, bfd_boolean);
 
-/* PowerPC @tls opcode transform/validate.  */
-extern unsigned int _bfd_elf_ppc_at_tls_transform
-  (unsigned int, unsigned int);
-/* PowerPC @tprel opcode transform/validate.  */
-extern unsigned int _bfd_elf_ppc_at_tprel_transform
-  (unsigned int, unsigned int);
-
 extern void bfd_elf64_aarch64_init_maps
   (bfd *);
 

diff --git a/bfd/cpu-powerpc.c b/bfd/cpu-powerpc.c
index 5b77317..fd72cd1 100644 (file)
--- a/bfd/cpu-powerpc.c
+++ b/bfd/cpu-powerpc.c
@@ -35,6 +35,10 @@ powerpc_compatible (const bfd_arch_info_type *a,
     default:
       return NULL;
     case bfd_arch_powerpc:
+      if (a->mach == bfd_mach_ppc_vle && b->bits_per_word == 32)
+       return a;
+      if (b->mach == bfd_mach_ppc_vle && a->bits_per_word == 32)
+       return b;
       return bfd_default_compatible (a, b);
     case bfd_arch_rs6000:
       if (b->mach == bfd_mach_rs6k)

diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
index 99dbbce..d37c208 100644 (file)
--- a/bfd/elf-bfd.h
+++ b/bfd/elf-bfd.h
@@ -2368,6 +2368,15 @@ extern bfd_boolean bfd_elf_lookup_section_flags
 extern Elf_Internal_Phdr * _bfd_elf_find_segment_containing_section
   (bfd * abfd, asection * section);
 
+/* PowerPC @tls opcode transform/validate.  */
+extern unsigned int _bfd_elf_ppc_at_tls_transform
+  (unsigned int, unsigned int);
+/* PowerPC @tprel opcode transform/validate.  */
+extern unsigned int _bfd_elf_ppc_at_tprel_transform
+  (unsigned int, unsigned int);
+/* PowerPC elf_object_p tweak.  */
+extern bfd_boolean _bfd_elf_ppc_set_arch (bfd *);
+
 /* Exported interface for writing elf corefile notes. */
 extern char *elfcore_write_note
   (bfd *, char *, int *, const char *, int, const void *, int);

diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index accb85f..95ce1dc 100644 (file)
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -2196,13 +2196,93 @@ ppc_elf_mkobject (bfd *abfd)
                                  PPC32_ELF_DATA);
 }
 
+/* When defaulting arch/mach, decode apuinfo to find a better match.  */
+
+bfd_boolean
+_bfd_elf_ppc_set_arch (bfd *abfd)
+{
+  unsigned long mach = 0;
+  asection *s;
+  unsigned char *contents;
+
+  if (abfd->arch_info->bits_per_word == 32
+      && bfd_big_endian (abfd))
+    {
+
+      for (s = abfd->sections; s != NULL; s = s->next)
+       if ((elf_section_data (s)->this_hdr.sh_flags & SHF_PPC_VLE) != 0)
+         break;
+      if (s != NULL)
+       mach = bfd_mach_ppc_vle;
+    }
+
+  if (mach == 0)
+    {
+      s = bfd_get_section_by_name (abfd, APUINFO_SECTION_NAME);
+      if (s != NULL && bfd_malloc_and_get_section (abfd, s, &contents))
+       {
+         unsigned int apuinfo_size = bfd_get_32 (abfd, contents + 4);
+         unsigned int i;
+
+         for (i = 20; i < apuinfo_size + 20 && i + 4 <= s->size; i += 4)
+           {
+             unsigned int val = bfd_get_32 (abfd, contents + i);
+             switch (val >> 16)
+               {
+               case PPC_APUINFO_PMR:
+               case PPC_APUINFO_RFMCI:
+                 if (mach == 0)
+                   mach = bfd_mach_ppc_titan;
+                 break;
+
+               case PPC_APUINFO_ISEL:
+               case PPC_APUINFO_CACHELCK:
+                 if (mach == bfd_mach_ppc_titan)
+                   mach = bfd_mach_ppc_e500mc;
+                 break;
+
+               case PPC_APUINFO_SPE:
+               case PPC_APUINFO_EFS:
+               case PPC_APUINFO_BRLOCK:
+                 if (mach != bfd_mach_ppc_vle)
+                   mach = bfd_mach_ppc_e500;
+
+               case PPC_APUINFO_VLE:
+                 mach = bfd_mach_ppc_vle;
+                 break;
+
+               default:
+                 mach = -1ul;
+               }
+           }
+         free (contents);
+       }
+    }
+
+  if (mach != 0 && mach != -1ul)
+    {
+      const bfd_arch_info_type *arch;
+
+      for (arch = abfd->arch_info->next; arch; arch = arch->next)
+       if (arch->mach == mach)
+         {
+           abfd->arch_info = arch;
+           break;
+         }
+    }
+  return TRUE;
+}
+
 /* Fix bad default arch selected for a 32 bit input bfd when the
-   default is 64 bit.  */
+   default is 64 bit.  Also select arch based on apuinfo.  */
 
 static bfd_boolean
 ppc_elf_object_p (bfd *abfd)
 {
-  if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 64)
+  if (!abfd->arch_info->the_default)
+    return TRUE;
+
+  if (abfd->arch_info->bits_per_word == 64)
     {
       Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
 
@@ -2213,7 +2293,7 @@ ppc_elf_object_p (bfd *abfd)
          BFD_ASSERT (abfd->arch_info->bits_per_word == 32);
        }
     }
-  return TRUE;
+  return _bfd_elf_ppc_set_arch (abfd);
 }
 
 /* Function to set whether a module needs the -mrelocatable bit set.  */
@@ -2519,16 +2599,16 @@ ppc_elf_modify_segment_map (bfd *abfd,
 
 static const struct bfd_elf_special_section ppc_elf_special_sections[] =
 {
-  { STRING_COMMA_LEN (".plt"),             0, SHT_NOBITS,   SHF_ALLOC + SHF_EXECINSTR },
-  { STRING_COMMA_LEN (".sbss"),           -2, SHT_NOBITS,   SHF_ALLOC + SHF_WRITE },
-  { STRING_COMMA_LEN (".sbss2"),          -2, SHT_PROGBITS, SHF_ALLOC },
-  { STRING_COMMA_LEN (".sdata"),          -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
-  { STRING_COMMA_LEN (".sdata2"),         -2, SHT_PROGBITS, SHF_ALLOC },
-  { STRING_COMMA_LEN (".tags"),            0, SHT_ORDERED,  SHF_ALLOC },
-  { STRING_COMMA_LEN (".PPC.EMB.apuinfo"), 0, SHT_NOTE,     0 },
-  { STRING_COMMA_LEN (".PPC.EMB.sbss0"),   0, SHT_PROGBITS, SHF_ALLOC },
-  { STRING_COMMA_LEN (".PPC.EMB.sdata0"),  0, SHT_PROGBITS, SHF_ALLOC },
-  { NULL,                              0,  0, 0,            0 }
+  { STRING_COMMA_LEN (".plt"), 0, SHT_NOBITS, SHF_ALLOC + SHF_EXECINSTR },
+  { STRING_COMMA_LEN (".sbss"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
+  { STRING_COMMA_LEN (".sbss2"), -2, SHT_PROGBITS, SHF_ALLOC },
+  { STRING_COMMA_LEN (".sdata"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
+  { STRING_COMMA_LEN (".sdata2"), -2, SHT_PROGBITS, SHF_ALLOC },
+  { STRING_COMMA_LEN (".tags"), 0, SHT_ORDERED, SHF_ALLOC },
+  { STRING_COMMA_LEN (APUINFO_SECTION_NAME), 0, SHT_NOTE, 0 },
+  { STRING_COMMA_LEN (".PPC.EMB.sbss0"), 0, SHT_PROGBITS, SHF_ALLOC },
+  { STRING_COMMA_LEN (".PPC.EMB.sdata0"), 0, SHT_PROGBITS, SHF_ALLOC },
+  { NULL, 0, 0, 0, 0 }
 };
 
 /* This is what we want for new plt/got.  */
@@ -2637,9 +2717,6 @@ apuinfo_list_finish (void)
   head = NULL;
 }
 
-#define APUINFO_SECTION_NAME   ".PPC.EMB.apuinfo"
-#define APUINFO_LABEL          "APUinfo"
-
 /* Scan the input BFDs and create a linked list of
    the APUinfo values that will need to be emitted.  */
 

diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 41fe879..70fa5c3 100644 (file)
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -2888,12 +2888,15 @@ ppc64_elf_mkobject (bfd *abfd)
 }
 
 /* Fix bad default arch selected for a 64 bit input bfd when the
-   default is 32 bit.  */
+   default is 32 bit.  Also select arch based on apuinfo.  */
 
 static bfd_boolean
 ppc64_elf_object_p (bfd *abfd)
 {
-  if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 32)
+  if (!abfd->arch_info->the_default)
+    return TRUE;
+
+  if (abfd->arch_info->bits_per_word == 32)
     {
       Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
 
@@ -2904,7 +2907,7 @@ ppc64_elf_object_p (bfd *abfd)
          BFD_ASSERT (abfd->arch_info->bits_per_word == 64);
        }
     }
-  return TRUE;
+  return _bfd_elf_ppc_set_arch (abfd);
 }
 
 /* Support for core dump NOTE sections.  */

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d41cd6d..c3b2436 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2016-06-07  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
+       PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
+       PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
+       (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
+       by vle_opcodes, and that vle flag doesn't enable opcodes.  Don't
+       add vle_opcodes twice.
+       (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
+
 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 
        * config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.

diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 2492573..fc2a045 100644 (file)
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1048,18 +1048,6 @@ static segT ppc_current_section;
 
 #ifdef OBJ_ELF
 symbolS *GOT_symbol;           /* Pre-defined "_GLOBAL_OFFSET_TABLE" */
-#define PPC_APUINFO_ISEL       0x40
-#define PPC_APUINFO_PMR                0x41
-#define PPC_APUINFO_RFMCI      0x42
-#define PPC_APUINFO_CACHELCK   0x43
-#define PPC_APUINFO_SPE                0x100
-#define PPC_APUINFO_EFS                0x101
-#define PPC_APUINFO_BRLOCK     0x102
-#define PPC_APUINFO_VLE                0x104
-
-/*
- * We keep a list of APUinfo
- */
 unsigned long *ppc_apuinfo_list;
 unsigned int ppc_apuinfo_num;
 unsigned int ppc_apuinfo_num_alloc;
@@ -1563,6 +1551,18 @@ ppc_setup_opcodes (void)
                  bad_insn = TRUE;
                }
            }
+         if ((op->flags & PPC_OPCODE_VLE) != 0)
+           {
+             as_bad (_("%s is enabled by vle flag"), op->name);
+             bad_insn = TRUE;
+           }
+         if (PPC_OP (op->opcode) != 4
+             && PPC_OP (op->opcode) != 31
+             && (op->deprecated & PPC_OPCODE_VLE) == 0)
+           {
+             as_bad (_("%s not disabled by vle flag"), op->name);
+             bad_insn = TRUE;
+           }
          bad_insn |= insn_validate (op);
        }
 
@@ -1634,10 +1634,6 @@ ppc_setup_opcodes (void)
        }
     }
 
-  if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
-    for (op = vle_opcodes; op < op_end; op++)
-      hash_insert (ppc_hash, op->name, (void *) op);
-
   /* Insert the macros into a hash table.  */
   ppc_macro_hash = hash_new ();
 
@@ -1736,7 +1732,7 @@ ppc_cleanup (void)
     unsigned int i;
 
     /* Create the .PPC.EMB.apuinfo section.  */
-    apuinfo_secp = subseg_new (".PPC.EMB.apuinfo", 0);
+    apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0);
     bfd_set_section_flags (stdoutput,
                           apuinfo_secp,
                           SEC_HAS_CONTENTS | SEC_READONLY);
@@ -1751,7 +1747,7 @@ ppc_cleanup (void)
     md_number_to_chars (p, (valueT) 2, 4);
 
     p = frag_more (8);
-    strcpy (p, "APUinfo");
+    strcpy (p, APUINFO_LABEL);
 
     for (i = 0; i < ppc_apuinfo_num; i++)
       {

diff --git a/include/ChangeLog b/include/ChangeLog
index abf5a52..4d9a0b0 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-07  Alan Modra  <amodra@gmail.com>
+
+       * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
+       PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
+       PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
+       PPC_APUINFO_VLE: Define.
+
 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 
        * opcode/arm.h (ARM_EXT2_RAS): New.  Also align preceding

diff --git a/include/elf/ppc.h b/include/elf/ppc.h
index 43b36c1..f4a6bbd 100644 (file)
--- a/include/elf/ppc.h
+++ b/include/elf/ppc.h
@@ -202,6 +202,19 @@ END_RELOC_NUMBERS (R_PPC_max)
                                                   specified in the associated \
                                                   symbol table entry.  */
 
+/* APUinfo note section.  */
+#define APUINFO_SECTION_NAME   ".PPC.EMB.apuinfo"
+#define APUINFO_LABEL          "APUinfo"
+
+#define PPC_APUINFO_ISEL       0x40
+#define PPC_APUINFO_PMR                0x41
+#define PPC_APUINFO_RFMCI      0x42
+#define PPC_APUINFO_CACHELCK   0x43
+#define PPC_APUINFO_SPE                0x100
+#define PPC_APUINFO_EFS                0x101
+#define PPC_APUINFO_BRLOCK     0x102
+#define PPC_APUINFO_VLE                0x104
+
 /* Object attribute tags.  */
 enum
 {

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 96b844b..ac08ee6 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,9 @@
+2016-06-07  Alan Modra  <amodra@gmail.com>
+
+       * testsuite/ld-powerpc/apuinfo1.s: Delete nop.
+       * testsuite/ld-powerpc/apuinfo-vle2.s: New.
+       * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
+
 2016-06-06  H.J. Lu  <hongjiu.lu@intel.com>
 
        * testsuite/ld-x86-64/pass.out: New file.

diff --git a/ld/testsuite/ld-powerpc/apuinfo-vle2.s b/ld/testsuite/ld-powerpc/apuinfo-vle2.s
new file mode 100644 (file)
index 0000000..7174a8a
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/apuinfo-vle2.s
@@ -0,0 +1,8 @@
+       .text
+       .global apuinfo2
+apuinfo2:
+       evstdd 29,8(1)
+       mfbbear 29
+       mfpmr   29, 27
+       dcbtstls 1, 29, 28
+       se_rfmci

diff --git a/ld/testsuite/ld-powerpc/apuinfo1.s b/ld/testsuite/ld-powerpc/apuinfo1.s
index fd42eac..cdcfc47 100644 (file)
--- a/ld/testsuite/ld-powerpc/apuinfo1.s
+++ b/ld/testsuite/ld-powerpc/apuinfo1.s
@@ -1,9 +1,8 @@
        .text
        .global apuinfo1
-apuinfo1:      
+apuinfo1:
        evstdd 29,8(1)
        isellt 29, 28, 27
        efsabs 29, 28
        .global _start
 _start:
-       nop

diff --git a/ld/testsuite/ld-powerpc/powerpc.exp b/ld/testsuite/ld-powerpc/powerpc.exp
index 46ffcf5..37e53fd 100644 (file)
--- a/ld/testsuite/ld-powerpc/powerpc.exp
+++ b/ld/testsuite/ld-powerpc/powerpc.exp
@@ -104,7 +104,7 @@ set ppcelftests {
      "-a32 -me500" {apuinfo1.s apuinfo-nul.s apuinfo2.s}
      {{readelf -x2 apuinfo.rd}} "apuinfo"}
     {"APUinfo VLE section processing" "-melf32ppc" ""
-     "-a32 -me500 -mvle" {apuinfo1.s apuinfo-vle.s apuinfo2.s}
+     "-a32 -me500 -mvle" {apuinfo1.s apuinfo-vle.s apuinfo-vle2.s}
      {{readelf -x2 apuinfo-vle.rd}} "apuinfo-vle"}
     {"APUinfo NULL section processing" "-melf32ppc" ""
      "-a32 -me500" {apuinfo-nul1.s apuinfo-nul.s}

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 04757f6..13d35e0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2016-06-07  Alan Modra  <amodra@gmail.com>
+
+       * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
+       cpu for "vle" to e500.
+       * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
+       (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
+       (PPCNONE): Delete, substitute throughout.
+       (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
+       except for major opcode 4 and 31.
+       (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
+
 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 
        * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with

diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index f835968..77a2a60 100644 (file)
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -51,9 +51,9 @@ struct ppc_mopt {
 };
 
 struct ppc_mopt ppc_opts[] = {
-  { "403",     (PPC_OPCODE_PPC | PPC_OPCODE_403),
+  { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
     0 },
-  { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
+  { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
     0 },
   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
                | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
@@ -64,48 +64,48 @@ struct ppc_mopt ppc_opts[] = {
   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
                | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
     0 },
-  { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_601),
+  { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
     0 },
-  { "603",     (PPC_OPCODE_PPC),
+  { "603",     PPC_OPCODE_PPC,
     0 },
-  { "604",     (PPC_OPCODE_PPC),
+  { "604",     PPC_OPCODE_PPC,
     0 },
-  { "620",     (PPC_OPCODE_PPC | PPC_OPCODE_64),
+  { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
     0 },
-  { "7400",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+  { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
     0 },
-  { "7410",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+  { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
     0 },
-  { "7450",    (PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC),
+  { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
     0 },
-  { "7455",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+  { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
     0 },
-  { "750cl",   (PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS)
+  { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
     , 0 },
-  { "821",     (PPC_OPCODE_PPC | PPC_OPCODE_860),
+  { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
     0 },
-  { "850",     (PPC_OPCODE_PPC | PPC_OPCODE_860),
+  { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
     0 },
-  { "860",     (PPC_OPCODE_PPC | PPC_OPCODE_860),
+  { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
     0 },
   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
                | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
                | PPC_OPCODE_A2),
     0 },
-  { "altivec", (PPC_OPCODE_PPC),
+  { "altivec", PPC_OPCODE_PPC,
     PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
   { "any",     0,
     PPC_OPCODE_ANY },
-  { "booke",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
+  { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
     0 },
-  { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
+  { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
     0 },
   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
                | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
     0 },
-  { "com",     (PPC_OPCODE_COMMON),
+  { "com",     PPC_OPCODE_COMMON,
     0 },
-  { "e300",    (PPC_OPCODE_PPC | PPC_OPCODE_E300),
+  { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
     0 },
   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
                | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
@@ -138,9 +138,9 @@ struct ppc_mopt ppc_opts[] = {
                | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
                | PPC_OPCODE_E500),
     0 },
-  { "efs",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
+  { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
     0 },
-  { "power4",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
+  { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
     0 },
   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
                | PPC_OPCODE_POWER5),
@@ -163,21 +163,21 @@ struct ppc_mopt ppc_opts[] = {
                | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
                | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
     0 },
-  { "ppc",     (PPC_OPCODE_PPC),
+  { "ppc",     PPC_OPCODE_PPC,
     0 },
-  { "ppc32",   (PPC_OPCODE_PPC),
+  { "ppc32",   PPC_OPCODE_PPC,
     0 },
-  { "ppc64",   (PPC_OPCODE_PPC | PPC_OPCODE_64),
+  { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
     0 },
-  { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
+  { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
     0 },
-  { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
+  { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
     0 },
-  { "pwr",     (PPC_OPCODE_POWER),
+  { "pwr",     PPC_OPCODE_POWER,
     0 },
-  { "pwr2",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
+  { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
     0 },
-  { "pwr4",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
+  { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
     0 },
   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
                | PPC_OPCODE_POWER5),
@@ -203,18 +203,21 @@ struct ppc_mopt ppc_opts[] = {
                | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
                | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
     0 },
-  { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
+  { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
     0 },
-  { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
+  { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
     PPC_OPCODE_SPE },
   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
                | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
     0 },
-  { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
+  { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
+               | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
+               | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+               | PPC_OPCODE_E500),
     PPC_OPCODE_VLE },
-  { "vsx",     (PPC_OPCODE_PPC),
+  { "vsx",     PPC_OPCODE_PPC,
     PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
-  { "htm",     (PPC_OPCODE_PPC),
+  { "htm",     PPC_OPCODE_PPC,
     PPC_OPCODE_HTM },
 };
 

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index a5948e5..f3349e5 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2049,7 +2049,7 @@ extract_spr (unsigned long insn,
 }
 
 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
-#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
+#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
 
 static unsigned long
 insert_sprg (unsigned long insn,
@@ -2977,7 +2977,6 @@ extract_vleil (unsigned long insn,
 \f
 /* Smaller names for the flags so each entry in the opcodes table will
    fit on a single line.  */
-#define PPCNONE        0
 #undef PPC
 #define PPC    PPC_OPCODE_PPC
 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
@@ -3016,11 +3015,11 @@ extract_vleil (unsigned long insn,
 #define MFDEC1 PPC_OPCODE_POWER
 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
 #define BOOKE  PPC_OPCODE_BOOKE
-#define NO371  PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE
+#define NO371  PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
 #define PPCE300 PPC_OPCODE_E300
-#define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE
-#define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
-#define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE
+#define PPCSPE PPC_OPCODE_SPE
+#define PPCISEL PPC_OPCODE_ISEL
+#define PPCEFS PPC_OPCODE_EFS
 #define PPCBRLK PPC_OPCODE_BRLOCK
 #define PPCPMR PPC_OPCODE_PMR
 #define PPCTMR  PPC_OPCODE_TMR
@@ -3029,7 +3028,7 @@ extract_vleil (unsigned long insn,
 #define E500MC  PPC_OPCODE_E500MC
 #define PPCA2  PPC_OPCODE_A2
 #define TITAN   PPC_OPCODE_TITAN
-#define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
+#define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
 #define E500   PPC_OPCODE_E500
 #define E6500  PPC_OPCODE_E6500
 #define PPCVLE  PPC_OPCODE_VLE
@@ -3037,7 +3036,7 @@ extract_vleil (unsigned long insn,
 /* The list of embedded processors that use the embedded operand ordering
    for the 3 operand dcbt and dcbtst instructions.  */
 #define DCBT_EO        (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
-                | PPC_OPCODE_A2 | PPC_OPCODE_VLE)
+                | PPC_OPCODE_A2)
 
 
 \f
@@ -3064,3930 +3063,3930 @@ extract_vleil (unsigned long insn,
    constrained otherwise by disassembler operation.  */
 
 const struct powerpc_opcode powerpc_opcodes[] = {
-{"attn",       X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
-{"tdlgti",     OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdllti",     OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdeqi",      OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdlgei",     OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdlnli",     OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdllei",     OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdlngi",     OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdgti",      OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdgei",      OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdnli",      OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdlti",      OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdlei",      OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdngi",      OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdnei",      OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdui",       OPTO(2,TOU),    OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
-{"tdi",                OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
-
-{"twlgti",     OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twllti",     OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tllti",      OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"tweqi",      OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"teqi",       OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twlgei",     OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twlnli",     OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twllei",     OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tllei",      OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twlngi",     OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twgti",      OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tgti",       OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twgei",      OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tgei",       OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twnli",      OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tnli",       OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twlti",      OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tlti",       OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twlei",      OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tlei",       OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twngi",      OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tngi",       OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twnei",      OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tnei",       OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twui",       OPTO(3,TOU),    OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
-{"tui",                OPTO(3,TOU),    OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
-{"twi",                OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
-{"ti",         OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
-
-{"ps_cmpu0",   X  (4,   0),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
-{"vaddubm",    VX (4,   0),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmul10cuq",  VX (4,   1),    VXVB_MASK,   PPCVEC3,       PPCNONE,    {VD, VA}},
-{"vmaxub",     VX (4,   2),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrlb",       VX (4,   4),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpequb",   VXR(4,   6,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpneb",    VXR(4,   7,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vmuloub",    VX (4,   8),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vaddfp",     VX (4,  10),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"psq_lx",     XW (4,   6,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
-{"vmrghb",     VX (4,  12),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"psq_stx",    XW (4,   7,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
-{"vpkuhum",    VX (4,  14),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"mulhhwu",    XRC(4,   8,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"mulhhwu.",   XRC(4,   8,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_sum0",    A  (4,  10,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_sum0.",   A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_sum1",    A  (4,  11,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_sum1.",   A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_muls0",   A  (4,  12,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
-{"machhwu",    XO (4,  12,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_muls0.",  A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
-{"machhwu.",   XO (4,  12,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_muls1",   A  (4,  13,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
-{"ps_muls1.",  A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
-{"ps_madds0",  A  (4,  14,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_madds0.", A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_madds1",  A  (4,  15,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_madds1.", A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"vmhaddshs",  VXA(4,  32),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"vmhraddshs", VXA(4,  33),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"vmladduhm",  VXA(4,  34),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"vmsumudm",   VXA(4,  35),    VXA_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB, VC}},
-{"ps_div",     A  (4,  18,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"vmsumubm",   VXA(4,  36),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"ps_div.",    A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"vmsummbm",   VXA(4,  37),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"vmsumuhm",   VXA(4,  38),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"vmsumuhs",   VXA(4,  39),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"ps_sub",     A  (4,  20,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"vmsumshm",   VXA(4,  40),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"ps_sub.",    A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"vmsumshs",   VXA(4,  41),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"ps_add",     A  (4,  21,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"vsel",       VXA(4,  42),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"ps_add.",    A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"vperm",      VXA(4,  43),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, VC}},
-{"vsldoi",     VXA(4,  44),    VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB, SHB}},
-{"vpermxor",   VXA(4,  45),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
-{"ps_sel",     A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"vmaddfp",    VXA(4,  46),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
-{"ps_sel.",    A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"vnmsubfp",   VXA(4,  47),    VXA_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VC, VB}},
-{"ps_res",     A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
-{"maddhd",     VXA(4,  48),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
-{"ps_res.",    A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
-{"maddhdu",    VXA(4,  49),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
-{"ps_mul",     A  (4,  25,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
-{"ps_mul.",    A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
-{"maddld",     VXA(4,  51),    VXA_MASK,    POWER9,    PPCNONE,        {RT, RA, RB, RC}},
-{"ps_rsqrte",  A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
-{"ps_rsqrte.", A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
-{"ps_msub",    A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_msub.",   A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_madd",    A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"ps_madd.",   A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"vpermr",     VXA(4,  59),    VXA_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB, VC}},
-{"ps_nmsub",   A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"vaddeuqm",   VXA(4,  60),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
-{"ps_nmsub.",  A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"vaddecuq",   VXA(4,  61),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
-{"ps_nmadd",   A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"vsubeuqm",   VXA(4,  62),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
-{"ps_nmadd.",  A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"vsubecuq",   VXA(4,  63),    VXA_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB, VC}},
-{"ps_cmpo0",   X  (4,  32),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
-{"vadduhm",    VX (4,  64),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmul10ecuq", VX (4,  65),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"vmaxuh",     VX (4,  66),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrlh",       VX (4,  68),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpequh",   VXR(4,  70,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpneh",    VXR(4,  71,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vmulouh",    VX (4,  72),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vsubfp",     VX (4,  74),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"psq_lux",    XW (4,  38,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
-{"vmrghh",     VX (4,  76),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"psq_stux",   XW (4,  39,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
-{"vpkuwum",    VX (4,  78),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"ps_neg",     XRC(4,  40,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
-{"mulhhw",     XRC(4,  40,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_neg.",    XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
-{"mulhhw.",    XRC(4,  40,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"machhw",     XO (4,  44,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"machhw.",    XO (4,  44,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmachhw",    XO (4,  46,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmachhw.",   XO (4,  46,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_cmpu1",   X  (4,  64),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
-{"vadduwm",    VX (4,  128),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmaxuw",     VX (4,  130),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrlw",       VX (4,  132),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrlwmi",     VX (4,  133),   VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"vcmpequw",   VXR(4,  134,0), VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpnew",    VXR(4,  135,0), VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vmulouw",    VX (4,  136),   VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vmuluwm",    VX (4,  137),   VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vmrghw",     VX (4,  140),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vpkuhus",    VX (4,  142),   VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"ps_mr",      XRC(4,  72,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
-{"ps_mr.",     XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
-{"machhwsu",   XO (4,  76,0,0),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
-{"machhwsu.",  XO (4,  76,0,1),XO_MASK,     MULHW|PPCVLE,  PPCNONE,    {RT, RA, RB}},
-{"ps_cmpo1",   X  (4,  96),    XBF_MASK,    PPCPS,     PPCNONE,        {BF, FRA, FRB}},
-{"vaddudm",    VX (4, 192),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vmaxud",     VX (4, 194),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vrld",       VX (4, 196),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vrldmi",     VX (4, 197),    VX_MASK,     PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vcmpeqfp",   VXR(4, 198,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpequd",   VXR(4, 199,0),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vpkuwus",    VX (4, 206),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"machhws",    XO (4, 108,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"machhws.",   XO (4, 108,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmachhws",   XO (4, 110,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmachhws.",  XO (4, 110,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vadduqm",    VX (4, 256),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vmaxsb",     VX (4, 258),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vslb",       VX (4, 260),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpnezb",   VXR(4, 263,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vmulosb",    VX (4, 264),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrefp",      VX (4, 266),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"vmrglb",     VX (4, 268),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vpkshus",    VX (4, 270),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"ps_nabs",    XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
-{"mulchwu",    XRC(4, 136,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_nabs.",   XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
-{"mulchwu.",   XRC(4, 136,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"macchwu",    XO (4, 140,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"macchwu.",   XO (4, 140,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vaddcuq",    VX (4, 320),    VX_MASK,     PPCVEC2,      PPCNONE,     {VD, VA, VB}},
-{"vmaxsh",     VX (4, 322),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vslh",       VX (4, 324),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpnezh",   VXR(4, 327,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vmulosh",    VX (4, 328),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrsqrtefp",  VX (4, 330),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"vmrglh",     VX (4, 332),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vpkswus",    VX (4, 334),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"mulchw",     XRC(4, 168,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"mulchw.",    XRC(4, 168,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"macchw",     XO (4, 172,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"macchw.",    XO (4, 172,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmacchw",    XO (4, 174,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmacchw.",   XO (4, 174,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vaddcuw",    VX (4, 384),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmaxsw",     VX (4, 386),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vslw",       VX (4, 388),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrlwnm",     VX (4, 389),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"vcmpnezw",   VXR(4, 391,0),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vmulosw",    VX (4, 392),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vexptefp",   VX (4, 394),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"vmrglw",     VX (4, 396),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vpkshss",    VX (4, 398),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"macchwsu",   XO (4, 204,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"macchwsu.",  XO (4, 204,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vmaxsd",     VX (4, 450),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vsl",                VX (4, 452),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrldnm",     VX (4, 453),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"vcmpgefp",   VXR(4, 454,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vlogefp",    VX (4, 458),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"vpkswss",    VX (4, 462),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"macchws",    XO (4, 236,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"macchws.",   XO (4, 236,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmacchws",   XO (4, 238,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmacchws.",  XO (4, 238,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evaddw",     VX (4, 512),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vaddubs",    VX (4, 512),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmul10uq",   VX (4, 513),    VXVB_MASK,   PPCVEC3,       PPCNONE,    {VD, VA}},
-{"evaddiw",    VX (4, 514),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB, UIMM}},
-{"vminub",     VX (4, 514),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evsubfw",    VX (4, 516),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evsubw",     VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
-{"vsrb",       VX (4, 516),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evsubifw",   VX (4, 518),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, UIMM, RB}},
-{"evsubiw",    VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
-{"vcmpgtub",   VXR(4, 518,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evabs",      VX (4, 520),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vmuleub",    VX (4, 520),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evneg",      VX (4, 521),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evextsb",    VX (4, 522),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vrfin",      VX (4, 522),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"evextsh",    VX (4, 523),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evrndw",     VX (4, 524),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vspltb",     VX (4, 524),    VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM4}},
-{"vextractub", VX (4, 525),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
-{"evcntlzw",   VX (4, 525),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evcntlsw",   VX (4, 526),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vupkhsb",    VX (4, 526),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"brinc",      VX (4, 527),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"ps_abs",     XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
-{"ps_abs.",    XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
-{"evand",      VX (4, 529),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evandc",     VX (4, 530),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evxor",      VX (4, 534),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmr",       VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
-{"evor",       VX (4, 535),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evnor",      VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evnot",      VX (4, 536),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, BBA}},
-{"get",                APU(4, 268,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
-{"eveqv",      VX (4, 537),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evorc",      VX (4, 539),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evnand",     VX (4, 542),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evsrwu",     VX (4, 544),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evsrws",     VX (4, 545),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evsrwiu",    VX (4, 546),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
-{"evsrwis",    VX (4, 547),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
-{"evslw",      VX (4, 548),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evslwi",     VX (4, 550),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
-{"evrlw",      VX (4, 552),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evsplati",   VX (4, 553),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
-{"evrlwi",     VX (4, 554),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, EVUIMM}},
-{"evsplatfi",  VX (4, 555),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, SIMM}},
-{"evmergehi",  VX (4, 556),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmergelo",  VX (4, 557),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmergehilo",        VX (4, 558),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmergelohi",        VX (4, 559),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evcmpgtu",   VX (4, 560),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"evcmpgts",   VX (4, 561),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"evcmpltu",   VX (4, 562),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"evcmplts",   VX (4, 563),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"evcmpeq",    VX (4, 564),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"cget",       APU(4, 284,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
-{"vadduhs",    VX (4, 576),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmul10euq",  VX (4, 577),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"vminuh",     VX (4, 578),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vsrh",       VX (4, 580),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpgtuh",   VXR(4, 582,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmuleuh",    VX (4, 584),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrfiz",      VX (4, 586),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"vsplth",     VX (4, 588),    VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM3}},
-{"vextractuh", VX (4, 589),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
-{"vupkhsh",    VX (4, 590),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"nget",       APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
-{"evsel",      EVSEL(4,79),    EVSEL_MASK,  PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB, CRFS}},
-{"ncget",      APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
-{"evfsadd",    VX (4, 640),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vadduws",    VX (4, 640),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evfssub",    VX (4, 641),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vminuw",     VX (4, 642),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evfsabs",    VX (4, 644),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vsrw",       VX (4, 644),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evfsnabs",   VX (4, 645),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evfsneg",    VX (4, 646),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vcmpgtuw",   VXR(4, 646,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmuleuw",    VX (4, 648),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evfsmul",    VX (4, 648),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evfsdiv",    VX (4, 649),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vrfip",      VX (4, 650),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"evfscmpgt",  VX (4, 652),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"vspltw",     VX (4, 652),    VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM2}},
-{"vextractuw", VX (4, 653),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
-{"evfscmplt",  VX (4, 653),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"evfscmpeq",  VX (4, 654),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"vupklsb",    VX (4, 654),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"evfscfui",   VX (4, 656),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfscfsi",   VX (4, 657),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfscfuf",   VX (4, 658),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfscfsf",   VX (4, 659),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfsctui",   VX (4, 660),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfsctsi",   VX (4, 661),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfsctuf",   VX (4, 662),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfsctsf",   VX (4, 663),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfsctuiz",  VX (4, 664),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"put",                APU(4, 332,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
-{"evfsctsiz",  VX (4, 666),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
-{"evfststgt",  VX (4, 668),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"evfststlt",  VX (4, 669),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"evfststeq",  VX (4, 670),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"cput",       APU(4, 348,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
-{"efsadd",     VX (4, 704),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"efssub",     VX (4, 705),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vminud",     VX (4, 706),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"efsabs",     VX (4, 708),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
-{"vsr",                VX (4, 708),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"efsnabs",    VX (4, 709),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
-{"efsneg",     VX (4, 710),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
-{"vcmpgtfp",   VXR(4, 710,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpgtud",   VXR(4, 711,0),  VXR_MASK,    PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"efsmul",     VX (4, 712),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"efsdiv",     VX (4, 713),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vrfim",      VX (4, 714),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"efscmpgt",   VX (4, 716),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"vextractd",  VX (4, 717),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
-{"efscmplt",   VX (4, 717),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efscmpeq",   VX (4, 718),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"vupklsh",    VX (4, 718),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"efscfd",     VX (4, 719),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efscfui",    VX (4, 720),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efscfsi",    VX (4, 721),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efscfuf",    VX (4, 722),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efscfsf",    VX (4, 723),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efsctui",    VX (4, 724),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efsctsi",    VX (4, 725),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efsctuf",    VX (4, 726),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efsctsf",    VX (4, 727),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efsctuiz",   VX (4, 728),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"nput",       APU(4, 364,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
-{"efsctsiz",   VX (4, 730),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efststgt",   VX (4, 732),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efststlt",   VX (4, 733),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efststeq",   VX (4, 734),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efdadd",     VX (4, 736),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"efdsub",     VX (4, 737),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"efdcfuid",   VX (4, 738),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdcfsid",   VX (4, 739),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdabs",     VX (4, 740),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
-{"efdnabs",    VX (4, 741),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
-{"efdneg",     VX (4, 742),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA}},
-{"efdmul",     VX (4, 744),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"efddiv",     VX (4, 745),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"efdctuidz",  VX (4, 746),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdctsidz",  VX (4, 747),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdcmpgt",   VX (4, 748),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efdcmplt",   VX (4, 749),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efdcmpeq",   VX (4, 750),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efdcfs",     VX (4, 751),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdcfui",    VX (4, 752),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdcfsi",    VX (4, 753),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdcfuf",    VX (4, 754),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdcfsf",    VX (4, 755),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdctui",    VX (4, 756),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdctsi",    VX (4, 757),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdctuf",    VX (4, 758),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdctsf",    VX (4, 759),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdctuiz",   VX (4, 760),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"ncput",      APU(4, 380,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
-{"efdctsiz",   VX (4, 762),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
-{"efdtstgt",   VX (4, 764),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efdtstlt",   VX (4, 765),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"efdtsteq",   VX (4, 766),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"evlddx",     VX (4, 768),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vaddsbs",    VX (4, 768),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evldd",      VX (4, 769),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
-{"evldwx",     VX (4, 770),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vminsb",     VX (4, 770),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evldw",      VX (4, 771),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
-{"evldhx",     VX (4, 772),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vsrab",      VX (4, 772),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evldh",      VX (4, 773),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
-{"vcmpgtsb",   VXR(4, 774,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evlhhesplatx",VX (4, 776),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vmulesb",    VX (4, 776),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evlhhesplat",        VX (4, 777),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
-{"vcfux",      VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vcuxwfp",    VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"evlhhousplatx",VX(4, 780),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vspltisb",   VX (4, 780),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
-{"vinsertb",   VX (4, 781),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
-{"evlhhousplat",VX (4, 781),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
-{"evlhhossplatx",VX(4, 782),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vpkpx",      VX (4, 782),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evlhhossplat",VX (4, 783),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
-{"mullhwu",    XRC(4, 392,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evlwhex",    VX (4, 784),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"mullhwu.",   XRC(4, 392,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evlwhe",     VX (4, 785),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"evlwhoux",   VX (4, 788),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evlwhou",    VX (4, 789),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"evlwhosx",   VX (4, 790),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evlwhos",    VX (4, 791),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"maclhwu",    XO (4, 396,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evlwwsplatx",        VX (4, 792),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"maclhwu.",   XO (4, 396,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evlwwsplat", VX (4, 793),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"evlwhsplatx",        VX (4, 796),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evlwhsplat", VX (4, 797),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"evstddx",    VX (4, 800),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evstdd",     VX (4, 801),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
-{"evstdwx",    VX (4, 802),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evstdw",     VX (4, 803),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
-{"evstdhx",    VX (4, 804),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evstdh",     VX (4, 805),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_8, RA}},
-{"evstwhex",   VX (4, 816),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evstwhe",    VX (4, 817),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"evstwhox",   VX (4, 820),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evstwho",    VX (4, 821),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"evstwwex",   VX (4, 824),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evstwwe",    VX (4, 825),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"evstwwox",   VX (4, 828),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evstwwo",    VX (4, 829),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_4, RA}},
-{"vaddshs",    VX (4, 832),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"bcdcpsgn.",  VX (4, 833),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"vminsh",     VX (4, 834),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vsrah",      VX (4, 836),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpgtsh",   VXR(4, 838,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmulesh",    VX (4, 840),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcfsx",      VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vcsxwfp",    VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vspltish",   VX (4, 844),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
-{"vinserth",   VX (4, 845),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
-{"vupkhpx",    VX (4, 846),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"mullhw",     XRC(4, 424,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"mullhw.",    XRC(4, 424,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"maclhw",     XO (4, 428,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"maclhw.",    XO (4, 428,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmaclhw",    XO (4, 430,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmaclhw.",   XO (4, 430,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vaddsws",    VX (4, 896),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vminsw",     VX (4, 898),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vsraw",      VX (4, 900),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpgtsw",   VXR(4, 902,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmulesw",    VX (4, 904),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vctuxs",     VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vcfpuxws",   VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vspltisw",   VX (4, 908),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
-{"vinsertw",   VX (4, 909),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
-{"maclhwsu",   XO (4, 460,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"maclhwsu.",  XO (4, 460,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vminsd",     VX (4, 962),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vsrad",      VX (4, 964),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vcmpbfp",    VXR(4, 966,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpgtsd",   VXR(4, 967,0),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vctsxs",     VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vcfpsxws",   VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vinsertd",   VX (4, 973),    VXUIMM4_MASK,PPCVEC3,       PPCNONE,    {VD, VB, UIMM4}},
-{"vupklpx",    VX (4, 974),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"maclhws",    XO (4, 492,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"maclhws.",   XO (4, 492,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmaclhws",   XO (4, 494,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmaclhws.",  XO (4, 494,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vsububm",    VX (4,1024),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"bcdadd.",    VX (4,1025),    VXPS_MASK,   PPCVEC2,       PPCNONE,    {VD, VA, VB, PS}},
-{"vavgub",     VX (4,1026),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vabsdub",    VX (4,1027),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"evmhessf",   VX (4,1027),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vand",       VX (4,1028),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpequb.",  VXR(4,   6,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpneb.",   VXR(4,   7,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"udi0fcm.",   APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"udi0fcm",    APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"evmhossf",   VX (4,1031),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vpmsumb",    VX (4,1032),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmheumi",   VX (4,1032),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhesmi",   VX (4,1033),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vmaxfp",     VX (4,1034),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evmhesmf",   VX (4,1035),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhoumi",   VX (4,1036),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vslo",       VX (4,1036),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evmhosmi",   VX (4,1037),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhosmf",   VX (4,1039),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"machhwuo",   XO (4,  12,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"machhwuo.",  XO (4,  12,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_merge00", XOPS(4,528,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"ps_merge00.",        XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"evmhessfa",  VX (4,1059),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhossfa",  VX (4,1063),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmheumia",  VX (4,1064),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhesmia",  VX (4,1065),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhesmfa",  VX (4,1067),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhoumia",  VX (4,1068),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhosmia",  VX (4,1069),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhosmfa",  VX (4,1071),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vsubuhm",    VX (4,1088),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"bcdsub.",    VX (4,1089),    VXPS_MASK,   PPCVEC2,       PPCNONE,    {VD, VA, VB, PS}},
-{"vavguh",     VX (4,1090),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vabsduh",    VX (4,1091),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vandc",      VX (4,1092),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpequh.",  VXR(4,  70,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"udi1fcm.",   APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"udi1fcm",    APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"vcmpneh.",   VXR(4,  71,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"evmwhssf",   VX (4,1095),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vpmsumh",    VX (4,1096),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmwlumi",   VX (4,1096),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vminfp",     VX (4,1098),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evmwhumi",   VX (4,1100),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vsro",       VX (4,1100),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evmwhsmi",   VX (4,1101),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vpkudum",    VX (4,1102),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmwhsmf",   VX (4,1103),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwssf",    VX (4,1107),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"machhwo",    XO (4,  44,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmwumi",    VX (4,1112),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"machhwo.",   XO (4,  44,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmwsmi",    VX (4,1113),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwsmf",    VX (4,1115),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"nmachhwo",   XO (4,  46,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmachhwo.",  XO (4,  46,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_merge01", XOPS(4,560,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"ps_merge01.",        XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"evmwhssfa",  VX (4,1127),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwlumia",  VX (4,1128),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwhumia",  VX (4,1132),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwhsmia",  VX (4,1133),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwhsmfa",  VX (4,1135),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwssfa",   VX (4,1139),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwumia",   VX (4,1144),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwsmia",   VX (4,1145),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwsmfa",   VX (4,1147),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vsubuwm",    VX (4,1152),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"bcdus.",     VX (4,1153),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"vavguw",     VX (4,1154),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vabsduw",    VX (4,1155),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vmr",                VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VBA}},
-{"vor",                VX (4,1156),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vcmpnew.",   VXR(4, 135,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vpmsumw",    VX (4,1160),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vcmpequw.",  VXR(4, 134,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"udi2fcm.",   APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"udi2fcm",    APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"machhwsuo",  XO (4,  76,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"machhwsuo.", XO (4,  76,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_merge10", XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"ps_merge10.",        XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"vsubudm",    VX (4,1216),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evaddusiaaw",        VX (4,1216),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"bcds.",      VX (4,1217),    VXPS_MASK,   PPCVEC3,       PPCNONE,    {VD, VA, VB, PS}},
-{"evaddssiaaw",        VX (4,1217),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evsubfusiaaw",VX (4,1218),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evsubfssiaaw",VX (4,1219),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evmra",      VX (4,1220),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vxor",       VX (4,1220),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evdivws",    VX (4,1222),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vcmpeqfp.",  VXR(4, 198,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"udi3fcm.",   APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"vcmpequd.",  VXR(4, 199,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"udi3fcm",    APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"evdivwu",    VX (4,1223),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vpmsumd",    VX (4,1224),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evaddumiaaw",        VX (4,1224),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evaddsmiaaw",        VX (4,1225),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evsubfumiaaw",VX (4,1226),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"evsubfsmiaaw",VX (4,1227),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vpkudus",    VX (4,1230),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"machhwso",   XO (4, 108,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"machhwso.",  XO (4, 108,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmachhwso",  XO (4, 110,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmachhwso.", XO (4, 110,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"ps_merge11", XOPS(4,624,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"ps_merge11.",        XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
-{"vsubuqm",    VX (4,1280),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"evmheusiaaw",        VX (4,1280),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"bcdtrunc.",  VX (4,1281),    VXPS_MASK,   PPCVEC3,       PPCNONE,    {VD, VA, VB, PS}},
-{"evmhessiaaw",        VX (4,1281),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vavgsb",     VX (4,1282),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evmhessfaaw",        VX (4,1283),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhousiaaw",        VX (4,1284),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vnot",       VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VBA}},
-{"vnor",       VX (4,1284),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evmhossiaaw",        VX (4,1285),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"udi4fcm.",   APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"udi4fcm",    APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"vcmpnezb.",  VXR(4, 263,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"evmhossfaaw",        VX (4,1287),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmheumiaaw",        VX (4,1288),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vcipher",    VX (4,1288),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vcipherlast",        VX (4,1289),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmhesmiaaw",        VX (4,1289),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhesmfaaw",        VX (4,1291),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vgbbd",      VX (4,1292),    VXVA_MASK,   PPCVEC2,       PPCNONE,    {VD, VB}},
-{"evmhoumiaaw",        VX (4,1292),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhosmiaaw",        VX (4,1293),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhosmfaaw",        VX (4,1295),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"macchwuo",   XO (4, 140,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"macchwuo.",  XO (4, 140,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmhegumiaa",        VX (4,1320),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhegsmiaa",        VX (4,1321),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhegsmfaa",        VX (4,1323),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhogumiaa",        VX (4,1324),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhogsmiaa",        VX (4,1325),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhogsmfaa",        VX (4,1327),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vsubcuq",    VX (4,1344),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmwlusiaaw",        VX (4,1344),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"bcdutrunc.", VX (4,1345),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"evmwlssiaaw",        VX (4,1345),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vavgsh",     VX (4,1346),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vorc",       VX (4,1348),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"udi5fcm.",   APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"udi5fcm",    APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"vcmpnezh.",  VXR(4, 327,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vncipher",   VX (4,1352),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmwlumiaaw",        VX (4,1352),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vncipherlast",VX (4,1353),   VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmwlsmiaaw",        VX (4,1353),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vbpermq",    VX (4,1356),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vpksdus",    VX (4,1358),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmwssfaa",  VX (4,1363),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"macchwo",    XO (4, 172,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmwumiaa",  VX (4,1368),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"macchwo.",   XO (4, 172,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmwsmiaa",  VX (4,1369),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwsmfaa",  VX (4,1371),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"nmacchwo",   XO (4, 174,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmacchwo.",  XO (4, 174,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmheusianw",        VX (4,1408),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vsubcuw",    VX (4,1408),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evmhessianw",        VX (4,1409),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"bcdctsq.",   VXVA(4,1409,0), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"bcdcfsq.",   VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
-{"bcdctz.",    VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
-{"bcdctn.",    VXVA(4,1409,5), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"bcdcfz.",    VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
-{"bcdcfn.",    VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
-{"bcdsetsgn.", VXVA(4,1409,31),VXVAPS_MASK, PPCVEC3,       PPCNONE,    {VD, VB, PS}},
-{"vavgsw",     VX (4,1410),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"evmhessfanw",        VX (4,1411),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vnand",      VX (4,1412),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmhousianw",        VX (4,1412),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhossianw",        VX (4,1413),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"udi6fcm.",   APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"udi6fcm",    APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"vcmpnezw.",  VXR(4, 391,1),  VXR_MASK,    PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"evmhossfanw",        VX (4,1415),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmheumianw",        VX (4,1416),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhesmianw",        VX (4,1417),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhesmfanw",        VX (4,1419),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhoumianw",        VX (4,1420),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhosmianw",        VX (4,1421),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhosmfanw",        VX (4,1423),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"macchwsuo",  XO (4, 204,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"macchwsuo.", XO (4, 204,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmhegumian",        VX (4,1448),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhegsmian",        VX (4,1449),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhegsmfan",        VX (4,1451),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhogumian",        VX (4,1452),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhogsmian",        VX (4,1453),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmhogsmfan",        VX (4,1455),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwlusianw",        VX (4,1472),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"bcdsr.",     VX (4,1473),    VXPS_MASK,   PPCVEC3,       PPCNONE,    {VD, VA, VB, PS}},
-{"evmwlssianw",        VX (4,1473),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vsld",       VX (4,1476),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"vcmpgefp.",  VXR(4, 454,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"udi7fcm.",   APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"udi7fcm",    APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
-{"vsbox",      VX (4,1480),    VXVB_MASK,   PPCVEC2,       PPCNONE,    {VD, VA}},
-{"evmwlumianw",        VX (4,1480),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwlsmianw",        VX (4,1481),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vbpermd",    VX (4,1484),    VX_MASK,     PPCVEC3,       PPCNONE,    {VD, VA, VB}},
-{"vpksdss",    VX (4,1486),    VX_MASK,     PPCVEC2,       PPCNONE,    {VD, VA, VB}},
-{"evmwssfan",  VX (4,1491),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"macchwso",   XO (4, 236,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmwumian",  VX (4,1496),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"macchwso.",  XO (4, 236,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"evmwsmian",  VX (4,1497),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"evmwsmfan",  VX (4,1499),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"nmacchwso",  XO (4, 238,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmacchwso.", XO (4, 238,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vsububs",    VX (4,1536),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vclzlsbb",   VXVA(4,1538,0), VXVA_MASK,   PPCVEC3,       PPCNONE,    {RT, VB}},
-{"vctzlsbb",   VXVA(4,1538,1), VXVA_MASK,   PPCVEC3,       PPCNONE,    {RT, VB}},
-{"vnegw",      VXVA(4,1538,6), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vnegd",      VXVA(4,1538,7), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vprtybw",    VXVA(4,1538,8), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vprtybd",    VXVA(4,1538,9), VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vprtybq",    VXVA(4,1538,10),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vextsb2w",   VXVA(4,1538,16),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vextsh2w",   VXVA(4,1538,17),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vextsb2d",   VXVA(4,1538,24),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vextsh2d",   VXVA(4,1538,25),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vextsw2d",   VXVA(4,1538,26),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vctzb",      VXVA(4,1538,28),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vctzh",      VXVA(4,1538,29),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vctzw",      VXVA(4,1538,30),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"vctzd",      VXVA(4,1538,31),VXVA_MASK,   PPCVEC3,       PPCNONE,    {VD, VB}},
-{"mfvscr",     VX (4,1540),    VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD}},
-{"vcmpgtub.",  VXR(4, 518,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"attn",       X(0,256),       X_MASK,   POWER4|PPCA2, PPC476|PPCVLE,  {0}},
+{"tdlgti",     OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdllti",     OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdeqi",      OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdlgei",     OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdlnli",     OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdllei",     OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdlngi",     OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdgti",      OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdgei",      OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdnli",      OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdlti",      OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdlei",      OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdngi",      OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdnei",      OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdui",       OPTO(2,TOU),    OPTO_MASK,   PPC64,     PPCVLE,         {RA, SI}},
+{"tdi",                OP(2),          OP_MASK,     PPC64,     PPCVLE,         {TO, RA, SI}},
+
+{"twlgti",     OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twllti",     OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tllti",      OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"tweqi",      OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"teqi",       OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twlgei",     OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twlnli",     OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twllei",     OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tllei",      OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twlngi",     OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twgti",      OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tgti",       OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twgei",      OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tgei",       OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twnli",      OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tnli",       OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twlti",      OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tlti",       OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twlei",      OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tlei",       OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twngi",      OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tngi",       OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twnei",      OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tnei",       OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twui",       OPTO(3,TOU),    OPTO_MASK,   PPCCOM,    PPCVLE,         {RA, SI}},
+{"tui",                OPTO(3,TOU),    OPTO_MASK,   PWRCOM,    PPCVLE,         {RA, SI}},
+{"twi",                OP(3),          OP_MASK,     PPCCOM,    PPCVLE,         {TO, RA, SI}},
+{"ti",         OP(3),          OP_MASK,     PWRCOM,    PPCVLE,         {TO, RA, SI}},
+
+{"ps_cmpu0",   X  (4,   0),    XBF_MASK,    PPCPS,     0,              {BF, FRA, FRB}},
+{"vaddubm",    VX (4,   0),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vmul10cuq",  VX (4,   1),    VXVB_MASK,   PPCVEC3,   0,              {VD, VA}},
+{"vmaxub",     VX (4,   2),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrlb",       VX (4,   4),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpequb",   VXR(4,   6,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpneb",    VXR(4,   7,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"vmuloub",    VX (4,   8),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vaddfp",     VX (4,  10),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"psq_lx",     XW (4,   6,0),  XW_MASK,     PPCPS,     0,              {FRT,RA,RB,PSWM,PSQM}},
+{"vmrghb",     VX (4,  12),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"psq_stx",    XW (4,   7,0),  XW_MASK,     PPCPS,     0,              {FRS,RA,RB,PSWM,PSQM}},
+{"vpkuhum",    VX (4,  14),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"mulhhwu",    XRC(4,   8,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"mulhhwu.",   XRC(4,   8,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"ps_sum0",    A  (4,  10,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_sum0.",   A  (4,  10,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_sum1",    A  (4,  11,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_sum1.",   A  (4,  11,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_muls0",   A  (4,  12,0),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
+{"machhwu",    XO (4,  12,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"ps_muls0.",  A  (4,  12,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
+{"machhwu.",   XO (4,  12,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"ps_muls1",   A  (4,  13,0),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
+{"ps_muls1.",  A  (4,  13,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
+{"ps_madds0",  A  (4,  14,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_madds0.", A  (4,  14,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_madds1",  A  (4,  15,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_madds1.", A  (4,  15,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"vmhaddshs",  VXA(4,  32),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"vmhraddshs", VXA(4,  33),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"vmladduhm",  VXA(4,  34),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"vmsumudm",   VXA(4,  35),    VXA_MASK,    PPCVEC3,   0,              {VD, VA, VB, VC}},
+{"ps_div",     A  (4,  18,0),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"vmsumubm",   VXA(4,  36),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"ps_div.",    A  (4,  18,1),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"vmsummbm",   VXA(4,  37),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"vmsumuhm",   VXA(4,  38),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"vmsumuhs",   VXA(4,  39),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"ps_sub",     A  (4,  20,0),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"vmsumshm",   VXA(4,  40),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"ps_sub.",    A  (4,  20,1),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"vmsumshs",   VXA(4,  41),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"ps_add",     A  (4,  21,0),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"vsel",       VXA(4,  42),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"ps_add.",    A  (4,  21,1),  AFRC_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"vperm",      VXA(4,  43),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VB, VC}},
+{"vsldoi",     VXA(4,  44),    VXASHB_MASK, PPCVEC,    0,              {VD, VA, VB, SHB}},
+{"vpermxor",   VXA(4,  45),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
+{"ps_sel",     A  (4,  23,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"vmaddfp",    VXA(4,  46),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VC, VB}},
+{"ps_sel.",    A  (4,  23,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"vnmsubfp",   VXA(4,  47),    VXA_MASK,    PPCVEC,    0,              {VD, VA, VC, VB}},
+{"ps_res",     A  (4,  24,0), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
+{"maddhd",     VXA(4,  48),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
+{"ps_res.",    A  (4,  24,1), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
+{"maddhdu",    VXA(4,  49),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
+{"ps_mul",     A  (4,  25,0),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
+{"ps_mul.",    A  (4,  25,1),  AFRB_MASK,   PPCPS,     0,              {FRT, FRA, FRC}},
+{"maddld",     VXA(4,  51),    VXA_MASK,    POWER9,    0,              {RT, RA, RB, RC}},
+{"ps_rsqrte",  A  (4,  26,0), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
+{"ps_rsqrte.", A  (4,  26,1), AFRAFRC_MASK, PPCPS,     0,              {FRT, FRB}},
+{"ps_msub",    A  (4,  28,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_msub.",   A  (4,  28,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_madd",    A  (4,  29,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"ps_madd.",   A  (4,  29,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"vpermr",     VXA(4,  59),    VXA_MASK,    PPCVEC3,   0,              {VD, VA, VB, VC}},
+{"ps_nmsub",   A  (4,  30,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"vaddeuqm",   VXA(4,  60),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
+{"ps_nmsub.",  A  (4,  30,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"vaddecuq",   VXA(4,  61),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
+{"ps_nmadd",   A  (4,  31,0),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"vsubeuqm",   VXA(4,  62),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
+{"ps_nmadd.",  A  (4,  31,1),  A_MASK,      PPCPS,     0,              {FRT, FRA, FRC, FRB}},
+{"vsubecuq",   VXA(4,  63),    VXA_MASK,    PPCVEC2,   0,              {VD, VA, VB, VC}},
+{"ps_cmpo0",   X  (4,  32),    XBF_MASK,    PPCPS,     0,              {BF, FRA, FRB}},
+{"vadduhm",    VX (4,  64),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vmul10ecuq", VX (4,  65),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vmaxuh",     VX (4,  66),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrlh",       VX (4,  68),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpequh",   VXR(4,  70,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpneh",    VXR(4,  71,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"vmulouh",    VX (4,  72),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vsubfp",     VX (4,  74),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"psq_lux",    XW (4,  38,0),  XW_MASK,     PPCPS,     0,              {FRT,RA,RB,PSWM,PSQM}},
+{"vmrghh",     VX (4,  76),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"psq_stux",   XW (4,  39,0),  XW_MASK,     PPCPS,     0,              {FRS,RA,RB,PSWM,PSQM}},
+{"vpkuwum",    VX (4,  78),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"ps_neg",     XRC(4,  40,0),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
+{"mulhhw",     XRC(4,  40,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"ps_neg.",    XRC(4,  40,1),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
+{"mulhhw.",    XRC(4,  40,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"machhw",     XO (4,  44,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"machhw.",    XO (4,  44,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmachhw",    XO (4,  46,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmachhw.",   XO (4,  46,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"ps_cmpu1",   X  (4,  64),    XBF_MASK,    PPCPS,     0,              {BF, FRA, FRB}},
+{"vadduwm",    VX (4,  128),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vmaxuw",     VX (4,  130),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrlw",       VX (4,  132),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrlwmi",     VX (4,  133),   VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vcmpequw",   VXR(4,  134,0), VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpnew",    VXR(4,  135,0), VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"vmulouw",    VX (4,  136),   VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vmuluwm",    VX (4,  137),   VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vmrghw",     VX (4,  140),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vpkuhus",    VX (4,  142),   VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"ps_mr",      XRC(4,  72,0),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
+{"ps_mr.",     XRC(4,  72,1),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
+{"machhwsu",   XO (4,  76,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"machhwsu.",  XO (4,  76,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"ps_cmpo1",   X  (4,  96),    XBF_MASK,    PPCPS,     0,              {BF, FRA, FRB}},
+{"vaddudm",    VX (4, 192),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vmaxud",     VX (4, 194),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vrld",       VX (4, 196),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vrldmi",     VX (4, 197),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vcmpeqfp",   VXR(4, 198,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpequd",   VXR(4, 199,0),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
+{"vpkuwus",    VX (4, 206),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"machhws",    XO (4, 108,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"machhws.",   XO (4, 108,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmachhws",   XO (4, 110,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmachhws.",  XO (4, 110,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vadduqm",    VX (4, 256),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vmaxsb",     VX (4, 258),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vslb",       VX (4, 260),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpnezb",   VXR(4, 263,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"vmulosb",    VX (4, 264),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrefp",      VX (4, 266),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"vmrglb",     VX (4, 268),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vpkshus",    VX (4, 270),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"ps_nabs",    XRC(4, 136,0),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
+{"mulchwu",    XRC(4, 136,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"ps_nabs.",   XRC(4, 136,1),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
+{"mulchwu.",   XRC(4, 136,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"macchwu",    XO (4, 140,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"macchwu.",   XO (4, 140,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vaddcuq",    VX (4, 320),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vmaxsh",     VX (4, 322),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vslh",       VX (4, 324),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpnezh",   VXR(4, 327,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"vmulosh",    VX (4, 328),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrsqrtefp",  VX (4, 330),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"vmrglh",     VX (4, 332),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vpkswus",    VX (4, 334),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"mulchw",     XRC(4, 168,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"mulchw.",    XRC(4, 168,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"macchw",     XO (4, 172,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"macchw.",    XO (4, 172,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmacchw",    XO (4, 174,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmacchw.",   XO (4, 174,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vaddcuw",    VX (4, 384),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vmaxsw",     VX (4, 386),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vslw",       VX (4, 388),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrlwnm",     VX (4, 389),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vcmpnezw",   VXR(4, 391,0),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"vmulosw",    VX (4, 392),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vexptefp",   VX (4, 394),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"vmrglw",     VX (4, 396),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vpkshss",    VX (4, 398),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"macchwsu",   XO (4, 204,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"macchwsu.",  XO (4, 204,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vmaxsd",     VX (4, 450),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vsl",                VX (4, 452),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrldnm",     VX (4, 453),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vcmpgefp",   VXR(4, 454,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vlogefp",    VX (4, 458),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"vpkswss",    VX (4, 462),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"macchws",    XO (4, 236,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"macchws.",   XO (4, 236,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmacchws",   XO (4, 238,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmacchws.",  XO (4, 238,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evaddw",     VX (4, 512),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vaddubs",    VX (4, 512),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vmul10uq",   VX (4, 513),    VXVB_MASK,   PPCVEC3,   0,              {VD, VA}},
+{"evaddiw",    VX (4, 514),    VX_MASK,     PPCSPE,    0,              {RS, RB, UIMM}},
+{"vminub",     VX (4, 514),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evsubfw",    VX (4, 516),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evsubw",     VX (4, 516),    VX_MASK,     PPCSPE,    0,              {RS, RB, RA}},
+{"vsrb",       VX (4, 516),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evsubifw",   VX (4, 518),    VX_MASK,     PPCSPE,    0,              {RS, UIMM, RB}},
+{"evsubiw",    VX (4, 518),    VX_MASK,     PPCSPE,    0,              {RS, RB, UIMM}},
+{"vcmpgtub",   VXR(4, 518,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"evabs",      VX (4, 520),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vmuleub",    VX (4, 520),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evneg",      VX (4, 521),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evextsb",    VX (4, 522),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vrfin",      VX (4, 522),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"evextsh",    VX (4, 523),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evrndw",     VX (4, 524),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vspltb",     VX (4, 524),   VXUIMM4_MASK, PPCVEC,    0,              {VD, VB, UIMM4}},
+{"vextractub", VX (4, 525),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
+{"evcntlzw",   VX (4, 525),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evcntlsw",   VX (4, 526),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vupkhsb",    VX (4, 526),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"brinc",      VX (4, 527),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"ps_abs",     XRC(4, 264,0),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
+{"ps_abs.",    XRC(4, 264,1),  XRA_MASK,    PPCPS,     0,              {FRT, FRB}},
+{"evand",      VX (4, 529),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evandc",     VX (4, 530),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evxor",      VX (4, 534),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmr",       VX (4, 535),    VX_MASK,     PPCSPE,    0,              {RS, RA, BBA}},
+{"evor",       VX (4, 535),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evnor",      VX (4, 536),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evnot",      VX (4, 536),    VX_MASK,     PPCSPE,    0,              {RS, RA, BBA}},
+{"get",                APU(4, 268,0),  APU_RA_MASK, PPC405,    0,              {RT, FSL}},
+{"eveqv",      VX (4, 537),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evorc",      VX (4, 539),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evnand",     VX (4, 542),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evsrwu",     VX (4, 544),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evsrws",     VX (4, 545),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evsrwiu",    VX (4, 546),    VX_MASK,     PPCSPE,    0,              {RS, RA, EVUIMM}},
+{"evsrwis",    VX (4, 547),    VX_MASK,     PPCSPE,    0,              {RS, RA, EVUIMM}},
+{"evslw",      VX (4, 548),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evslwi",     VX (4, 550),    VX_MASK,     PPCSPE,    0,              {RS, RA, EVUIMM}},
+{"evrlw",      VX (4, 552),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evsplati",   VX (4, 553),    VX_MASK,     PPCSPE,    0,              {RS, SIMM}},
+{"evrlwi",     VX (4, 554),    VX_MASK,     PPCSPE,    0,              {RS, RA, EVUIMM}},
+{"evsplatfi",  VX (4, 555),    VX_MASK,     PPCSPE,    0,              {RS, SIMM}},
+{"evmergehi",  VX (4, 556),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmergelo",  VX (4, 557),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmergehilo",        VX (4, 558),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmergelohi",        VX (4, 559),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evcmpgtu",   VX (4, 560),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"evcmpgts",   VX (4, 561),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"evcmpltu",   VX (4, 562),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"evcmplts",   VX (4, 563),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"evcmpeq",    VX (4, 564),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"cget",       APU(4, 284,0),  APU_RA_MASK, PPC405,    0,              {RT, FSL}},
+{"vadduhs",    VX (4, 576),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vmul10euq",  VX (4, 577),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vminuh",     VX (4, 578),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vsrh",       VX (4, 580),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpgtuh",   VXR(4, 582,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vmuleuh",    VX (4, 584),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vrfiz",      VX (4, 586),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"vsplth",     VX (4, 588),   VXUIMM3_MASK, PPCVEC,    0,              {VD, VB, UIMM3}},
+{"vextractuh", VX (4, 589),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
+{"vupkhsh",    VX (4, 590),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"nget",       APU(4, 300,0),  APU_RA_MASK, PPC405,    0,              {RT, FSL}},
+{"evsel",      EVSEL(4,79),    EVSEL_MASK,  PPCSPE,    0,              {RS, RA, RB, CRFS}},
+{"ncget",      APU(4, 316,0),  APU_RA_MASK, PPC405,    0,              {RT, FSL}},
+{"evfsadd",    VX (4, 640),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vadduws",    VX (4, 640),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evfssub",    VX (4, 641),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vminuw",     VX (4, 642),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evfsabs",    VX (4, 644),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vsrw",       VX (4, 644),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evfsnabs",   VX (4, 645),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evfsneg",    VX (4, 646),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vcmpgtuw",   VXR(4, 646,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vmuleuw",    VX (4, 648),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evfsmul",    VX (4, 648),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evfsdiv",    VX (4, 649),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vrfip",      VX (4, 650),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"evfscmpgt",  VX (4, 652),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"vspltw",     VX (4, 652),   VXUIMM2_MASK, PPCVEC,    0,              {VD, VB, UIMM2}},
+{"vextractuw", VX (4, 653),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
+{"evfscmplt",  VX (4, 653),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"evfscmpeq",  VX (4, 654),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"vupklsb",    VX (4, 654),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"evfscfui",   VX (4, 656),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfscfsi",   VX (4, 657),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfscfuf",   VX (4, 658),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfscfsf",   VX (4, 659),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfsctui",   VX (4, 660),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfsctsi",   VX (4, 661),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfsctuf",   VX (4, 662),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfsctsf",   VX (4, 663),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfsctuiz",  VX (4, 664),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"put",                APU(4, 332,0),  APU_RT_MASK, PPC405,    0,              {RA, FSL}},
+{"evfsctsiz",  VX (4, 666),    VX_MASK,     PPCSPE,    0,              {RS, RB}},
+{"evfststgt",  VX (4, 668),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"evfststlt",  VX (4, 669),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"evfststeq",  VX (4, 670),    VX_MASK,     PPCSPE,    0,              {CRFD, RA, RB}},
+{"cput",       APU(4, 348,0),  APU_RT_MASK, PPC405,    0,              {RA, FSL}},
+{"efsadd",     VX (4, 704),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
+{"efssub",     VX (4, 705),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
+{"vminud",     VX (4, 706),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"efsabs",     VX (4, 708),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
+{"vsr",                VX (4, 708),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"efsnabs",    VX (4, 709),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
+{"efsneg",     VX (4, 710),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
+{"vcmpgtfp",   VXR(4, 710,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpgtud",   VXR(4, 711,0),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
+{"efsmul",     VX (4, 712),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
+{"efsdiv",     VX (4, 713),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
+{"vrfim",      VX (4, 714),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"efscmpgt",   VX (4, 716),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"vextractd",  VX (4, 717),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
+{"efscmplt",   VX (4, 717),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efscmpeq",   VX (4, 718),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"vupklsh",    VX (4, 718),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"efscfd",     VX (4, 719),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efscfui",    VX (4, 720),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efscfsi",    VX (4, 721),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efscfuf",    VX (4, 722),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efscfsf",    VX (4, 723),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efsctui",    VX (4, 724),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efsctsi",    VX (4, 725),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efsctuf",    VX (4, 726),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efsctsf",    VX (4, 727),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efsctuiz",   VX (4, 728),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"nput",       APU(4, 364,0),  APU_RT_MASK, PPC405,    0,              {RA, FSL}},
+{"efsctsiz",   VX (4, 730),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efststgt",   VX (4, 732),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efststlt",   VX (4, 733),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efststeq",   VX (4, 734),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efdadd",     VX (4, 736),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
+{"efdsub",     VX (4, 737),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
+{"efdcfuid",   VX (4, 738),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdcfsid",   VX (4, 739),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdabs",     VX (4, 740),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
+{"efdnabs",    VX (4, 741),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
+{"efdneg",     VX (4, 742),    VX_MASK,     PPCEFS,    0,              {RS, RA}},
+{"efdmul",     VX (4, 744),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
+{"efddiv",     VX (4, 745),    VX_MASK,     PPCEFS,    0,              {RS, RA, RB}},
+{"efdctuidz",  VX (4, 746),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdctsidz",  VX (4, 747),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdcmpgt",   VX (4, 748),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efdcmplt",   VX (4, 749),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efdcmpeq",   VX (4, 750),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efdcfs",     VX (4, 751),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdcfui",    VX (4, 752),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdcfsi",    VX (4, 753),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdcfuf",    VX (4, 754),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdcfsf",    VX (4, 755),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdctui",    VX (4, 756),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdctsi",    VX (4, 757),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdctuf",    VX (4, 758),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdctsf",    VX (4, 759),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdctuiz",   VX (4, 760),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"ncput",      APU(4, 380,0),  APU_RT_MASK, PPC405,    0,              {RA, FSL}},
+{"efdctsiz",   VX (4, 762),    VX_MASK,     PPCEFS,    0,              {RS, RB}},
+{"efdtstgt",   VX (4, 764),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efdtstlt",   VX (4, 765),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"efdtsteq",   VX (4, 766),    VX_MASK,     PPCEFS,    0,              {CRFD, RA, RB}},
+{"evlddx",     VX (4, 768),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vaddsbs",    VX (4, 768),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evldd",      VX (4, 769),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
+{"evldwx",     VX (4, 770),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vminsb",     VX (4, 770),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evldw",      VX (4, 771),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
+{"evldhx",     VX (4, 772),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vsrab",      VX (4, 772),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evldh",      VX (4, 773),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
+{"vcmpgtsb",   VXR(4, 774,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"evlhhesplatx",VX (4, 776),   VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vmulesb",    VX (4, 776),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evlhhesplat",        VX (4, 777),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_2, RA}},
+{"vcfux",      VX (4, 778),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
+{"vcuxwfp",    VX (4, 778),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
+{"evlhhousplatx",VX(4, 780),   VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vspltisb",   VX (4, 780),    VXVB_MASK,   PPCVEC,    0,              {VD, SIMM}},
+{"vinsertb",   VX (4, 781),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
+{"evlhhousplat",VX (4, 781),   VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_2, RA}},
+{"evlhhossplatx",VX(4, 782),   VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vpkpx",      VX (4, 782),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evlhhossplat",VX (4, 783),   VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_2, RA}},
+{"mullhwu",    XRC(4, 392,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"evlwhex",    VX (4, 784),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"mullhwu.",   XRC(4, 392,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"evlwhe",     VX (4, 785),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"evlwhoux",   VX (4, 788),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evlwhou",    VX (4, 789),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"evlwhosx",   VX (4, 790),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evlwhos",    VX (4, 791),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"maclhwu",    XO (4, 396,0,0),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
+{"evlwwsplatx",        VX (4, 792),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"maclhwu.",   XO (4, 396,0,1),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
+{"evlwwsplat", VX (4, 793),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"evlwhsplatx",        VX (4, 796),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evlwhsplat", VX (4, 797),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"evstddx",    VX (4, 800),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evstdd",     VX (4, 801),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
+{"evstdwx",    VX (4, 802),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evstdw",     VX (4, 803),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
+{"evstdhx",    VX (4, 804),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evstdh",     VX (4, 805),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_8, RA}},
+{"evstwhex",   VX (4, 816),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evstwhe",    VX (4, 817),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"evstwhox",   VX (4, 820),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evstwho",    VX (4, 821),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"evstwwex",   VX (4, 824),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evstwwe",    VX (4, 825),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"evstwwox",   VX (4, 828),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evstwwo",    VX (4, 829),    VX_MASK,     PPCSPE,    0,              {RS, EVUIMM_4, RA}},
+{"vaddshs",    VX (4, 832),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"bcdcpsgn.",  VX (4, 833),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vminsh",     VX (4, 834),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vsrah",      VX (4, 836),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpgtsh",   VXR(4, 838,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vmulesh",    VX (4, 840),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcfsx",      VX (4, 842),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
+{"vcsxwfp",    VX (4, 842),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
+{"vspltish",   VX (4, 844),    VXVB_MASK,   PPCVEC,    0,              {VD, SIMM}},
+{"vinserth",   VX (4, 845),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
+{"vupkhpx",    VX (4, 846),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"mullhw",     XRC(4, 424,0),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"mullhw.",    XRC(4, 424,1),  X_MASK,      MULHW,     0,              {RT, RA, RB}},
+{"maclhw",     XO (4, 428,0,0),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
+{"maclhw.",    XO (4, 428,0,1),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
+{"nmaclhw",    XO (4, 430,0,0),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
+{"nmaclhw.",   XO (4, 430,0,1),XO_MASK,     MULHW,     0,              {RT, RA, RB}},
+{"vaddsws",    VX (4, 896),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vminsw",     VX (4, 898),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vsraw",      VX (4, 900),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpgtsw",   VXR(4, 902,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vmulesw",    VX (4, 904),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vctuxs",     VX (4, 906),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
+{"vcfpuxws",   VX (4, 906),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
+{"vspltisw",   VX (4, 908),    VXVB_MASK,   PPCVEC,    0,              {VD, SIMM}},
+{"vinsertw",   VX (4, 909),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
+{"maclhwsu",   XO (4, 460,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"maclhwsu.",  XO (4, 460,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vminsd",     VX (4, 962),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vsrad",      VX (4, 964),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vcmpbfp",    VXR(4, 966,0),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpgtsd",   VXR(4, 967,0),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
+{"vctsxs",     VX (4, 970),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
+{"vcfpsxws",   VX (4, 970),    VX_MASK,     PPCVEC,    0,              {VD, VB, UIMM}},
+{"vinsertd",   VX (4, 973),   VXUIMM4_MASK, PPCVEC3,   0,              {VD, VB, UIMM4}},
+{"vupklpx",    VX (4, 974),    VXVA_MASK,   PPCVEC,    0,              {VD, VB}},
+{"maclhws",    XO (4, 492,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"maclhws.",   XO (4, 492,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmaclhws",   XO (4, 494,0,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmaclhws.",  XO (4, 494,0,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vsububm",    VX (4,1024),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"bcdadd.",    VX (4,1025),    VXPS_MASK,   PPCVEC2,   0,              {VD, VA, VB, PS}},
+{"vavgub",     VX (4,1026),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vabsdub",    VX (4,1027),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmhessf",   VX (4,1027),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vand",       VX (4,1028),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpequb.",  VXR(4,   6,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpneb.",   VXR(4,   7,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"udi0fcm.",   APU(4, 515,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"udi0fcm",    APU(4, 515,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"evmhossf",   VX (4,1031),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vpmsumb",    VX (4,1032),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmheumi",   VX (4,1032),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhesmi",   VX (4,1033),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vmaxfp",     VX (4,1034),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evmhesmf",   VX (4,1035),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhoumi",   VX (4,1036),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vslo",       VX (4,1036),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evmhosmi",   VX (4,1037),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhosmf",   VX (4,1039),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"machhwuo",   XO (4,  12,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"machhwuo.",  XO (4,  12,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"ps_merge00", XOPS(4,528,0),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"ps_merge00.",        XOPS(4,528,1),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"evmhessfa",  VX (4,1059),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhossfa",  VX (4,1063),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmheumia",  VX (4,1064),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhesmia",  VX (4,1065),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhesmfa",  VX (4,1067),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhoumia",  VX (4,1068),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhosmia",  VX (4,1069),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhosmfa",  VX (4,1071),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vsubuhm",    VX (4,1088),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"bcdsub.",    VX (4,1089),    VXPS_MASK,   PPCVEC2,   0,              {VD, VA, VB, PS}},
+{"vavguh",     VX (4,1090),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vabsduh",    VX (4,1091),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vandc",      VX (4,1092),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpequh.",  VXR(4,  70,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"udi1fcm.",   APU(4, 547,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"udi1fcm",    APU(4, 547,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"vcmpneh.",   VXR(4,  71,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"evmwhssf",   VX (4,1095),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vpmsumh",    VX (4,1096),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmwlumi",   VX (4,1096),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vminfp",     VX (4,1098),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evmwhumi",   VX (4,1100),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vsro",       VX (4,1100),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evmwhsmi",   VX (4,1101),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vpkudum",    VX (4,1102),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmwhsmf",   VX (4,1103),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwssf",    VX (4,1107),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"machhwo",    XO (4,  44,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmwumi",    VX (4,1112),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"machhwo.",   XO (4,  44,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmwsmi",    VX (4,1113),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwsmf",    VX (4,1115),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"nmachhwo",   XO (4,  46,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmachhwo.",  XO (4,  46,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"ps_merge01", XOPS(4,560,0),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"ps_merge01.",        XOPS(4,560,1),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"evmwhssfa",  VX (4,1127),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwlumia",  VX (4,1128),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwhumia",  VX (4,1132),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwhsmia",  VX (4,1133),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwhsmfa",  VX (4,1135),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwssfa",   VX (4,1139),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwumia",   VX (4,1144),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwsmia",   VX (4,1145),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwsmfa",   VX (4,1147),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vsubuwm",    VX (4,1152),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"bcdus.",     VX (4,1153),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vavguw",     VX (4,1154),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vabsduw",    VX (4,1155),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vmr",                VX (4,1156),    VX_MASK,     PPCVEC,    0,              {VD, VA, VBA}},
+{"vor",                VX (4,1156),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vcmpnew.",   VXR(4, 135,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"vpmsumw",    VX (4,1160),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vcmpequw.",  VXR(4, 134,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"udi2fcm.",   APU(4, 579,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"udi2fcm",    APU(4, 579,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"machhwsuo",  XO (4,  76,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"machhwsuo.", XO (4,  76,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"ps_merge10", XOPS(4,592,0),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"ps_merge10.",        XOPS(4,592,1),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"vsubudm",    VX (4,1216),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evaddusiaaw",        VX (4,1216),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"bcds.",      VX (4,1217),    VXPS_MASK,   PPCVEC3,   0,              {VD, VA, VB, PS}},
+{"evaddssiaaw",        VX (4,1217),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evsubfusiaaw",VX (4,1218),   VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evsubfssiaaw",VX (4,1219),   VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evmra",      VX (4,1220),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vxor",       VX (4,1220),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evdivws",    VX (4,1222),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vcmpeqfp.",  VXR(4, 198,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"udi3fcm.",   APU(4, 611,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"vcmpequd.",  VXR(4, 199,1),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
+{"udi3fcm",    APU(4, 611,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"evdivwu",    VX (4,1223),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vpmsumd",    VX (4,1224),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evaddumiaaw",        VX (4,1224),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evaddsmiaaw",        VX (4,1225),    VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evsubfumiaaw",VX (4,1226),   VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"evsubfsmiaaw",VX (4,1227),   VX_MASK,     PPCSPE,    0,              {RS, RA}},
+{"vpkudus",    VX (4,1230),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"machhwso",   XO (4, 108,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"machhwso.",  XO (4, 108,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmachhwso",  XO (4, 110,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmachhwso.", XO (4, 110,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"ps_merge11", XOPS(4,624,0),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"ps_merge11.",        XOPS(4,624,1),  XOPS_MASK,   PPCPS,     0,              {FRT, FRA, FRB}},
+{"vsubuqm",    VX (4,1280),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmheusiaaw",        VX (4,1280),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"bcdtrunc.",  VX (4,1281),    VXPS_MASK,   PPCVEC3,   0,              {VD, VA, VB, PS}},
+{"evmhessiaaw",        VX (4,1281),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vavgsb",     VX (4,1282),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evmhessfaaw",        VX (4,1283),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhousiaaw",        VX (4,1284),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vnot",       VX (4,1284),    VX_MASK,     PPCVEC,    0,              {VD, VA, VBA}},
+{"vnor",       VX (4,1284),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evmhossiaaw",        VX (4,1285),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"udi4fcm.",   APU(4, 643,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"udi4fcm",    APU(4, 643,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"vcmpnezb.",  VXR(4, 263,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"evmhossfaaw",        VX (4,1287),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmheumiaaw",        VX (4,1288),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vcipher",    VX (4,1288),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vcipherlast",        VX (4,1289),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmhesmiaaw",        VX (4,1289),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhesmfaaw",        VX (4,1291),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vgbbd",      VX (4,1292),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"evmhoumiaaw",        VX (4,1292),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhosmiaaw",        VX (4,1293),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhosmfaaw",        VX (4,1295),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"macchwuo",   XO (4, 140,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"macchwuo.",  XO (4, 140,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmhegumiaa",        VX (4,1320),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhegsmiaa",        VX (4,1321),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhegsmfaa",        VX (4,1323),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhogumiaa",        VX (4,1324),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhogsmiaa",        VX (4,1325),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhogsmfaa",        VX (4,1327),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vsubcuq",    VX (4,1344),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmwlusiaaw",        VX (4,1344),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"bcdutrunc.", VX (4,1345),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"evmwlssiaaw",        VX (4,1345),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vavgsh",     VX (4,1346),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vorc",       VX (4,1348),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"udi5fcm.",   APU(4, 675,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"udi5fcm",    APU(4, 675,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"vcmpnezh.",  VXR(4, 327,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"vncipher",   VX (4,1352),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmwlumiaaw",        VX (4,1352),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vncipherlast",VX (4,1353),   VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmwlsmiaaw",        VX (4,1353),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vbpermq",    VX (4,1356),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vpksdus",    VX (4,1358),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmwssfaa",  VX (4,1363),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"macchwo",    XO (4, 172,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmwumiaa",  VX (4,1368),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"macchwo.",   XO (4, 172,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmwsmiaa",  VX (4,1369),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwsmfaa",  VX (4,1371),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"nmacchwo",   XO (4, 174,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmacchwo.",  XO (4, 174,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmheusianw",        VX (4,1408),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vsubcuw",    VX (4,1408),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evmhessianw",        VX (4,1409),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"bcdctsq.",   VXVA(4,1409,0), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
+{"bcdcfsq.",   VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3,   0,              {VD, VB, PS}},
+{"bcdctz.",    VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3,   0,              {VD, VB, PS}},
+{"bcdctn.",    VXVA(4,1409,5), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
+{"bcdcfz.",    VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3,   0,              {VD, VB, PS}},
+{"bcdcfn.",    VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3,   0,              {VD, VB, PS}},
+{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3,  0,              {VD, VB, PS}},
+{"vavgsw",     VX (4,1410),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"evmhessfanw",        VX (4,1411),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vnand",      VX (4,1412),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmhousianw",        VX (4,1412),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhossianw",        VX (4,1413),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"udi6fcm.",   APU(4, 707,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"udi6fcm",    APU(4, 707,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"vcmpnezw.",  VXR(4, 391,1),  VXR_MASK,    PPCVEC3,   0,              {VD, VA, VB}},
+{"evmhossfanw",        VX (4,1415),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmheumianw",        VX (4,1416),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhesmianw",        VX (4,1417),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhesmfanw",        VX (4,1419),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhoumianw",        VX (4,1420),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhosmianw",        VX (4,1421),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhosmfanw",        VX (4,1423),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"macchwsuo",  XO (4, 204,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"macchwsuo.", XO (4, 204,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmhegumian",        VX (4,1448),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhegsmian",        VX (4,1449),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhegsmfan",        VX (4,1451),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhogumian",        VX (4,1452),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhogsmian",        VX (4,1453),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmhogsmfan",        VX (4,1455),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwlusianw",        VX (4,1472),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"bcdsr.",     VX (4,1473),    VXPS_MASK,   PPCVEC3,   0,              {VD, VA, VB, PS}},
+{"evmwlssianw",        VX (4,1473),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vsld",       VX (4,1476),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vcmpgefp.",  VXR(4, 454,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"udi7fcm.",   APU(4, 739,0),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"udi7fcm",    APU(4, 739,1),  APU_MASK, PPC405|PPC440, PPC476,        {URT, URA, URB}},
+{"vsbox",      VX (4,1480),    VXVB_MASK,   PPCVEC2,   0,              {VD, VA}},
+{"evmwlumianw",        VX (4,1480),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwlsmianw",        VX (4,1481),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"vbpermd",    VX (4,1484),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vpksdss",    VX (4,1486),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"evmwssfan",  VX (4,1491),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"macchwso",   XO (4, 236,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmwumian",  VX (4,1496),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"macchwso.",  XO (4, 236,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"evmwsmian",  VX (4,1497),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"evmwsmfan",  VX (4,1499),    VX_MASK,     PPCSPE,    0,              {RS, RA, RB}},
+{"nmacchwso",  XO (4, 238,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmacchwso.", XO (4, 238,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vsububs",    VX (4,1536),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vclzlsbb",   VXVA(4,1538,0), VXVA_MASK,   PPCVEC3,   0,              {RT, VB}},
+{"vctzlsbb",   VXVA(4,1538,1), VXVA_MASK,   PPCVEC3,   0,              {RT, VB}},
+{"vnegw",      VXVA(4,1538,6), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
+{"vnegd",      VXVA(4,1538,7), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
+{"vprtybw",    VXVA(4,1538,8), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
+{"vprtybd",    VXVA(4,1538,9), VXVA_MASK,   PPCVEC3,   0,              {VD, VB}},
+{"vprtybq",    VXVA(4,1538,10), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vextsb2w",   VXVA(4,1538,16), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vextsh2w",   VXVA(4,1538,17), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vextsb2d",   VXVA(4,1538,24), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vextsh2d",   VXVA(4,1538,25), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vextsw2d",   VXVA(4,1538,26), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vctzb",      VXVA(4,1538,28), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vctzh",      VXVA(4,1538,29), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vctzw",      VXVA(4,1538,30), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"vctzd",      VXVA(4,1538,31), VXVA_MASK,  PPCVEC3,   0,              {VD, VB}},
+{"mfvscr",     VX (4,1540),    VXVAVB_MASK, PPCVEC,    0,              {VD}},
+{"vcmpgtub.",  VXR(4, 518,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
 {"udi8fcm.",   APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"udi8fcm",    APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"vsum4ubs",   VX (4,1544),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vextublx",   VX (4,1549),    VX_MASK,     PPCVEC3,       PPCNONE,    {RT, RA, VB}},
-{"vsubuhs",    VX (4,1600),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"mtvscr",     VX (4,1604),    VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE,    {VB}},
-{"vcmpgtuh.",  VXR(4, 582,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vsum4shs",   VX (4,1608),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"vsum4ubs",   VX (4,1544),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vextublx",   VX (4,1549),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
+{"vsubuhs",    VX (4,1600),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"mtvscr",     VX (4,1604),    VXVDVA_MASK, PPCVEC,    0,              {VB}},
+{"vcmpgtuh.",  VXR(4, 582,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vsum4shs",   VX (4,1608),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
 {"udi9fcm.",   APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"udi9fcm",    APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"vextuhlx",   VX (4,1613),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
-{"vupkhsw",    VX (4,1614),    VXVA_MASK,   PPCVEC2,       PPCNONE,    {VD, VB}},
-{"vsubuws",    VX (4,1664),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vshasigmaw", VX (4,1666),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, ST, SIX}},
-{"veqv",       VX (4,1668),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vcmpgtuw.",  VXR(4, 646,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"vextuhlx",   VX (4,1613),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
+{"vupkhsw",    VX (4,1614),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vsubuws",    VX (4,1664),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vshasigmaw", VX (4,1666),    VX_MASK,     PPCVEC2,   0,              {VD, VA, ST, SIX}},
+{"veqv",       VX (4,1668),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vcmpgtuw.",  VXR(4, 646,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
 {"udi10fcm.",  APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"udi10fcm",   APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"vsum2sws",   VX (4,1672),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmrgow",     VX (4,1676),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vextuwlx",   VX (4,1677),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
-{"vshasigmad", VX (4,1730),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, ST, SIX}},
-{"vsrd",       VX (4,1732),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vcmpgtfp.",  VXR(4, 710,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"vsum2sws",   VX (4,1672),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vmrgow",     VX (4,1676),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vextuwlx",   VX (4,1677),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
+{"vshasigmad", VX (4,1730),    VX_MASK,     PPCVEC2,   0,              {VD, VA, ST, SIX}},
+{"vsrd",       VX (4,1732),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vcmpgtfp.",  VXR(4, 710,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
 {"udi11fcm.",  APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"vcmpgtud.",  VXR(4, 711,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
+{"vcmpgtud.",  VXR(4, 711,1),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
 {"udi11fcm",   APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"vupklsw",    VX (4,1742),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vsubsbs",    VX (4,1792),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vclzb",      VX (4,1794),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vpopcntb",   VX (4,1795),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vsrv",       VX (4,1796),    VX_MASK,     PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vcmpgtsb.",  VXR(4, 774,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"vupklsw",    VX (4,1742),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vsubsbs",    VX (4,1792),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vclzb",      VX (4,1794),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vpopcntb",   VX (4,1795),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vsrv",       VX (4,1796),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vcmpgtsb.",  VXR(4, 774,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
 {"udi12fcm.",  APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"udi12fcm",   APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"vsum4sbs",   VX (4,1800),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vextubrx",   VX (4,1805),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
-{"maclhwuo",   XO (4, 396,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"maclhwuo.",  XO (4, 396,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vsubshs",    VX (4,1856),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vclzh",      VX (4,1858),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vpopcnth",   VX (4,1859),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vslv",       VX (4,1860),    VX_MASK,     PPCVEC3,   PPCNONE,        {VD, VA, VB}},
-{"vcmpgtsh.",  VXR(4, 838,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vextuhrx",   VX (4,1869),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
+{"vsum4sbs",   VX (4,1800),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vextubrx",   VX (4,1805),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
+{"maclhwuo",   XO (4, 396,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"maclhwuo.",  XO (4, 396,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vsubshs",    VX (4,1856),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vclzh",      VX (4,1858),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vpopcnth",   VX (4,1859),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vslv",       VX (4,1860),    VX_MASK,     PPCVEC3,   0,              {VD, VA, VB}},
+{"vcmpgtsh.",  VXR(4, 838,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
+{"vextuhrx",   VX (4,1869),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
 {"udi13fcm.",  APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"udi13fcm",   APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"maclhwo",    XO (4, 428,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"maclhwo.",   XO (4, 428,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmaclhwo",   XO (4, 430,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmaclhwo.",  XO (4, 430,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vsubsws",    VX (4,1920),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vclzw",      VX (4,1922),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vpopcntw",   VX (4,1923),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vcmpgtsw.",  VXR(4, 902,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
+{"maclhwo",    XO (4, 428,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"maclhwo.",   XO (4, 428,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmaclhwo",   XO (4, 430,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmaclhwo.",  XO (4, 430,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vsubsws",    VX (4,1920),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vclzw",      VX (4,1922),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vpopcntw",   VX (4,1923),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vcmpgtsw.",  VXR(4, 902,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
 {"udi14fcm.",  APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"udi14fcm",   APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"vsumsws",    VX (4,1928),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vmrgew",     VX (4,1932),    VX_MASK,     PPCVEC2,   PPCNONE,        {VD, VA, VB}},
-{"vextuwrx",   VX (4,1933),    VX_MASK,     PPCVEC3,   PPCNONE,        {RT, RA, VB}},
-{"maclhwsuo",  XO (4, 460,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"maclhwsuo.", XO (4, 460,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"vclzd",      VX (4,1986),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vpopcntd",   VX (4,1987),    VXVA_MASK,   PPCVEC2,   PPCNONE,        {VD, VB}},
-{"vcmpbfp.",   VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
+{"vsumsws",    VX (4,1928),    VX_MASK,     PPCVEC,    0,              {VD, VA, VB}},
+{"vmrgew",     VX (4,1932),    VX_MASK,     PPCVEC2,   0,              {VD, VA, VB}},
+{"vextuwrx",   VX (4,1933),    VX_MASK,     PPCVEC3,   0,              {RT, RA, VB}},
+{"maclhwsuo",  XO (4, 460,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"maclhwsuo.", XO (4, 460,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"vclzd",      VX (4,1986),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vpopcntd",   VX (4,1987),    VXVA_MASK,   PPCVEC2,   0,              {VD, VB}},
+{"vcmpbfp.",   VXR(4, 966,1),  VXR_MASK,    PPCVEC,    0,              {VD, VA, VB}},
 {"udi15fcm.",  APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"vcmpgtsd.",  VXR(4, 967,1),  VXR_MASK,    PPCVEC2,   PPCNONE,        {VD, VA, VB}},
+{"vcmpgtsd.",  VXR(4, 967,1),  VXR_MASK,    PPCVEC2,   0,              {VD, VA, VB}},
 {"udi15fcm",   APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
-{"maclhwso",   XO (4, 492,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"maclhwso.",  XO (4, 492,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmaclhwso",  XO (4, 494,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"nmaclhwso.", XO (4, 494,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"dcbz_l",     X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
-
-{"mulli",      OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
-{"muli",       OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
-
-{"subfic",     OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
-{"sfi",                OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
-
-{"dozi",       OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
-
-{"cmplwi",     OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UISIGNOPT}},
-{"cmpldi",     OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UISIGNOPT}},
-{"cmpli",      OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UISIGNOPT}},
-{"cmpli",      OP(10),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, UISIGNOPT}},
-
-{"cmpwi",      OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
-{"cmpdi",      OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
-{"cmpi",       OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
-{"cmpi",       OP(11),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, SI}},
-
-{"addic",      OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
-{"ai",         OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
-{"subic",      OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
-
-{"addic.",     OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
-{"ai.",                OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
-{"subic.",     OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
-
-{"li",         OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
-{"lil",                OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
-{"addi",       OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
-{"cal",                OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
-{"subi",       OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
-{"la",         OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
-
-{"lis",                OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
-{"liu",                OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
-{"addis",      OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
-{"cau",                OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
-{"subis",      OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSISIGNOPT}},
-
-{"bdnz-",    BBO(16,BODNZ,0,0),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
-{"bdnz+",    BBO(16,BODNZ,0,0),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
-{"bdnz",     BBO(16,BODNZ,0,0),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
-{"bdn",      BBO(16,BODNZ,0,0),                BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
-{"bdnzl-",   BBO(16,BODNZ,0,1),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
-{"bdnzl+",   BBO(16,BODNZ,0,1),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
-{"bdnzl",    BBO(16,BODNZ,0,1),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
-{"bdnl",     BBO(16,BODNZ,0,1),                BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
-{"bdnza-",   BBO(16,BODNZ,1,0),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
-{"bdnza+",   BBO(16,BODNZ,1,0),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
-{"bdnza",    BBO(16,BODNZ,1,0),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
-{"bdna",     BBO(16,BODNZ,1,0),                BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
-{"bdnzla-",  BBO(16,BODNZ,1,1),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
-{"bdnzla+",  BBO(16,BODNZ,1,1),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
-{"bdnzla",   BBO(16,BODNZ,1,1),                BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
-{"bdnla",    BBO(16,BODNZ,1,1),                BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
-{"bdz-",     BBO(16,BODZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
-{"bdz+",     BBO(16,BODZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
-{"bdz",      BBO(16,BODZ,0,0),         BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
-{"bdzl-",    BBO(16,BODZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
-{"bdzl+",    BBO(16,BODZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
-{"bdzl",     BBO(16,BODZ,0,1),         BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
-{"bdza-",    BBO(16,BODZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
-{"bdza+",    BBO(16,BODZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
-{"bdza",     BBO(16,BODZ,1,0),         BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
-{"bdzla-",   BBO(16,BODZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
-{"bdzla+",   BBO(16,BODZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
-{"bdzla",    BBO(16,BODZ,1,1),         BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
-
-{"bge-",     BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bge+",     BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bge",      BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bnl-",     BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bnl+",     BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bnl",      BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bgel-",    BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bgel+",    BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bgel",     BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bnll-",    BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bnll+",    BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bnll",     BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bgea-",    BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bgea+",    BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bgea",     BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bnla-",    BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnla+",    BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnla",     BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bgela-",   BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bgela+",   BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bgela",    BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bnlla-",   BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnlla+",   BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnlla",    BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"ble-",     BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"ble+",     BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"ble",      BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bng-",     BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bng+",     BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bng",      BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"blel-",    BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"blel+",    BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"blel",     BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bngl-",    BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bngl+",    BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bngl",     BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"blea-",    BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"blea+",    BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"blea",     BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bnga-",    BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnga+",    BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnga",     BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"blela-",   BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"blela+",   BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"blela",    BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bngla-",   BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bngla+",   BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bngla",    BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bne-",     BBOCB(16,BOF,CBEQ,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bne+",     BBOCB(16,BOF,CBEQ,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bne",      BBOCB(16,BOF,CBEQ,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bnel-",    BBOCB(16,BOF,CBEQ,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bnel+",    BBOCB(16,BOF,CBEQ,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bnel",     BBOCB(16,BOF,CBEQ,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bnea-",    BBOCB(16,BOF,CBEQ,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnea+",    BBOCB(16,BOF,CBEQ,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnea",     BBOCB(16,BOF,CBEQ,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bnela-",   BBOCB(16,BOF,CBEQ,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnela+",   BBOCB(16,BOF,CBEQ,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnela",    BBOCB(16,BOF,CBEQ,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bns-",     BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bns+",     BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bns",      BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bnu-",     BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bnu+",     BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bnu",      BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
-{"bnsl-",    BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bnsl+",    BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bnsl",     BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bnul-",    BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bnul+",    BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bnul",     BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
-{"bnsa-",    BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnsa+",    BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnsa",     BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bnua-",    BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnua+",    BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnua",     BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
-{"bnsla-",   BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnsla+",   BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnsla",    BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bnula-",   BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bnula+",   BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bnula",    BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
-
-{"blt-",     BBOCB(16,BOT,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"blt+",     BBOCB(16,BOT,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"blt",      BBOCB(16,BOT,CBLT,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bltl-",    BBOCB(16,BOT,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bltl+",    BBOCB(16,BOT,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bltl",     BBOCB(16,BOT,CBLT,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"blta-",    BBOCB(16,BOT,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"blta+",    BBOCB(16,BOT,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"blta",     BBOCB(16,BOT,CBLT,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bltla-",   BBOCB(16,BOT,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bltla+",   BBOCB(16,BOT,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bltla",    BBOCB(16,BOT,CBLT,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bgt-",     BBOCB(16,BOT,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bgt+",     BBOCB(16,BOT,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bgt",      BBOCB(16,BOT,CBGT,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bgtl-",    BBOCB(16,BOT,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bgtl+",    BBOCB(16,BOT,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bgtl",     BBOCB(16,BOT,CBGT,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bgta-",    BBOCB(16,BOT,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bgta+",    BBOCB(16,BOT,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bgta",     BBOCB(16,BOT,CBGT,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bgtla-",   BBOCB(16,BOT,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bgtla+",   BBOCB(16,BOT,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bgtla",    BBOCB(16,BOT,CBGT,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"beq-",     BBOCB(16,BOT,CBEQ,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"beq+",     BBOCB(16,BOT,CBEQ,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"beq",      BBOCB(16,BOT,CBEQ,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"beql-",    BBOCB(16,BOT,CBEQ,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"beql+",    BBOCB(16,BOT,CBEQ,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"beql",     BBOCB(16,BOT,CBEQ,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"beqa-",    BBOCB(16,BOT,CBEQ,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"beqa+",    BBOCB(16,BOT,CBEQ,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"beqa",     BBOCB(16,BOT,CBEQ,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"beqla-",   BBOCB(16,BOT,CBEQ,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"beqla+",   BBOCB(16,BOT,CBEQ,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"beqla",    BBOCB(16,BOT,CBEQ,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bso-",     BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bso+",     BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bso",      BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bun-",     BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bun+",     BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bun",      BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
-{"bsol-",    BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bsol+",    BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bsol",     BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
-{"bunl-",    BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
-{"bunl+",    BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
-{"bunl",     BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
-{"bsoa-",    BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bsoa+",    BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bsoa",     BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"buna-",    BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"buna+",    BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"buna",     BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
-{"bsola-",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bsola+",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bsola",    BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
-{"bunla-",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
-{"bunla+",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
-{"bunla",    BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
-
-{"bdnzf-",   BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
-{"bdnzf+",   BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
-{"bdnzf",    BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdnzfl-",  BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
-{"bdnzfl+",  BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
-{"bdnzfl",   BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdnzfa-",  BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
-{"bdnzfa+",  BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
-{"bdnzfa",   BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdnzfla-", BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
-{"bdnzfla+", BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
-{"bdnzfla",  BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdzf-",    BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
-{"bdzf+",    BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
-{"bdzf",     BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdzfl-",   BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
-{"bdzfl+",   BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
-{"bdzfl",    BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdzfa-",   BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
-{"bdzfa+",   BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
-{"bdzfa",    BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdzfla-",  BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
-{"bdzfla+",  BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
-{"bdzfla",   BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-
-{"bf-",      BBO(16,BOF,0,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
-{"bf+",      BBO(16,BOF,0,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
-{"bf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
-{"bbf",      BBO(16,BOF,0,0),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
-{"bfl-",     BBO(16,BOF,0,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
-{"bfl+",     BBO(16,BOF,0,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
-{"bfl",      BBO(16,BOF,0,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
-{"bbfl",     BBO(16,BOF,0,1),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
-{"bfa-",     BBO(16,BOF,1,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
-{"bfa+",     BBO(16,BOF,1,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
-{"bfa",      BBO(16,BOF,1,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bbfa",     BBO(16,BOF,1,0),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
-{"bfla-",    BBO(16,BOF,1,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
-{"bfla+",    BBO(16,BOF,1,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
-{"bfla",     BBO(16,BOF,1,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bbfla",    BBO(16,BOF,1,1),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
-
-{"bdnzt-",   BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
-{"bdnzt+",   BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
-{"bdnzt",    BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdnztl-",  BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
-{"bdnztl+",  BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
-{"bdnztl",   BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdnzta-",  BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
-{"bdnzta+",  BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
-{"bdnzta",   BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdnztla-", BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
-{"bdnztla+", BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
-{"bdnztla",  BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdzt-",    BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
-{"bdzt+",    BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
-{"bdzt",     BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdztl-",   BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDM}},
-{"bdztl+",   BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDP}},
-{"bdztl",    BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
-{"bdzta-",   BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
-{"bdzta+",   BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
-{"bdzta",    BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bdztla-",  BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDMA}},
-{"bdztla+",  BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2,        {BI, BDPA}},
-{"bdztla",   BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
-
-{"bt-",      BBO(16,BOT,0,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
-{"bt+",      BBO(16,BOT,0,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
-{"bt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
-{"bbt",      BBO(16,BOT,0,0),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
-{"btl-",     BBO(16,BOT,0,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
-{"btl+",     BBO(16,BOT,0,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
-{"btl",      BBO(16,BOT,0,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
-{"bbtl",     BBO(16,BOT,0,1),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
-{"bta-",     BBO(16,BOT,1,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
-{"bta+",     BBO(16,BOT,1,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
-{"bta",      BBO(16,BOT,1,0),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bbta",     BBO(16,BOT,1,0),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
-{"btla-",    BBO(16,BOT,1,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
-{"btla+",    BBO(16,BOT,1,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
-{"btla",     BBO(16,BOT,1,1),          BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
-{"bbtla",    BBO(16,BOT,1,1),          BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
-
-{"bc-",                B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
-{"bc+",                B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
-{"bc",         B(16,0,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
-{"bcl-",       B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
-{"bcl+",       B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
-{"bcl",                B(16,0,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
-{"bca-",       B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
-{"bca+",       B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
-{"bca",                B(16,1,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
-{"bcla-",      B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
-{"bcla+",      B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
-{"bcla",       B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
-
-{"svc",                SC(17,0,0),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
-{"svcl",       SC(17,0,1),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
-{"sc",         SC(17,1,0),     SC_MASK,     PPC,       PPCNONE,        {LEV}},
-{"svca",       SC(17,1,0),     SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
-{"svcla",      SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
-
-{"b",          B(18,0,0),      B_MASK,      COM,       PPCNONE,        {LI}},
-{"bl",         B(18,0,1),      B_MASK,      COM,       PPCNONE,        {LI}},
-{"ba",         B(18,1,0),      B_MASK,      COM,       PPCNONE,        {LIA}},
-{"bla",                B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
-
-{"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM,        PPCNONE,        {BF, BFA}},
-
-{"addpcis",   DX(19,2),                DX_MASK,     POWER9,    PPCNONE,        {RT, DXD}},
-{"subpcis",   DX(19,2),                DX_MASK,     POWER9,    PPCNONE,        {RT, NDXD}},
-
-{"bdnzlr",   XLO(19,BODNZ,16,0),       XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"bdnzlr-",  XLO(19,BODNZ,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
-{"bdnzlrl",  XLO(19,BODNZ,16,1),       XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"bdnzlrl-", XLO(19,BODNZ,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
-{"bdnzlr+",  XLO(19,BODNZP,16,0),      XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
-{"bdnzlrl+", XLO(19,BODNZP,16,1),      XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
-{"bdzlr",    XLO(19,BODZ,16,0),                XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"bdzlr-",   XLO(19,BODZ,16,0),                XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
-{"bdzlrl",   XLO(19,BODZ,16,1),                XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"bdzlrl-",  XLO(19,BODZ,16,1),                XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
-{"bdzlr+",   XLO(19,BODZP,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
-{"bdzlrl+",  XLO(19,BODZP,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2,        {0}},
-{"blr",      XLO(19,BOU,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"br",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
-{"blrl",     XLO(19,BOU,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
-{"brl",      XLO(19,BOU,16,1),         XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
-{"bdnzlr-",  XLO(19,BODNZM4,16,0),     XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
-{"bdnzlrl-", XLO(19,BODNZM4,16,1),     XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
-{"bdnzlr+",  XLO(19,BODNZP4,16,0),     XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
-{"bdnzlrl+", XLO(19,BODNZP4,16,1),     XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
-{"bdzlr-",   XLO(19,BODZM4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
-{"bdzlrl-",  XLO(19,BODZM4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
-{"bdzlr+",   XLO(19,BODZP4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
-{"bdzlrl+",  XLO(19,BODZP4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCNONE,       {0}},
-
-{"bgelr",    XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgelr-",   XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bger",     XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnllr",    XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnllr-",   XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnlr",     XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bgelrl",   XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgerl",    XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnllrl",   XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnlrl",    XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"blelr",    XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"blelr-",   XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bler",     XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnglr",    XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnglr-",   XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bngr",     XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"blelrl",   XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"blelrl-",  XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"blerl",    XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnglrl",   XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bngrl",    XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnelr",    XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bner",     XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnerl",    XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnslr",    XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnslr-",   XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnsr",     XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnulr",    XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnulr-",   XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnslrl",   XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnsrl",    XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bnulrl",   XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgelr+",   XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnllr+",   XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"blelr+",   XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnglr+",   XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"blelrl+",  XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnslr+",   XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnulr+",   XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"blelr-",   XLOCB(19,BOFM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"blelr+",   XLOCB(19,BOFP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bltlr",    XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bltlr-",   XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltr",     XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bltlrl",   XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltrl",    XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bgtlr",    XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgtr",     XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgtrl",    XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"beqlr",    XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"beqr",     XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"beqrl",    XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bsolr",    XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bsolr-",   XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsor",     XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bunlr",    XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bunlr-",   XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsolrl",   XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsorl",    XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
-{"bunlrl",   XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltlr+",   XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsolr+",   XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bunlr+",   XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-
-{"bdnzflr",  XLO(19,BODNZF,16,0),      XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdnzflr-", XLO(19,BODNZF,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdnzflrl", XLO(19,BODNZF,16,1),      XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdnzflrl-",XLO(19,BODNZF,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdnzflr+", XLO(19,BODNZFP,16,0),     XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdnzflrl+",XLO(19,BODNZFP,16,1),     XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdzflr",   XLO(19,BODZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdzflr-",  XLO(19,BODZF,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdzflrl",  XLO(19,BODZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdzflrl-", XLO(19,BODZF,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdzflr+",  XLO(19,BODZFP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdzflrl+", XLO(19,BODZFP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bflr",     XLO(19,BOF,16,0),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bflr-",    XLO(19,BOF,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bbfr",     XLO(19,BOF,16,0),         XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
-{"bflrl",    XLO(19,BOF,16,1),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bflrl-",   XLO(19,BOF,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bbfrl",    XLO(19,BOF,16,1),         XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
-{"bflr+",    XLO(19,BOFP,16,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bflrl+",   XLO(19,BOFP,16,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bflr-",    XLO(19,BOFM4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"bflrl-",   XLO(19,BOFM4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"bflr+",    XLO(19,BOFP4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"bflrl+",   XLO(19,BOFP4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"bdnztlr",  XLO(19,BODNZT,16,0),      XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdnztlr-", XLO(19,BODNZT,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdnztlrl", XLO(19,BODNZT,16,1),      XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdnztlrl-",XLO(19,BODNZT,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdnztlr+", XLO(19,BODNZTP,16,0),     XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdnztlrl+",XLO(19,BODNZTP,16,1),     XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdztlr",   XLO(19,BODZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdztlr-",  XLO(19,BODZT,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdztlrl",  XLO(19,BODZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bdztlrl-", XLO(19,BODZT,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdztlr+",  XLO(19,BODZTP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bdztlrl+", XLO(19,BODZTP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"btlr",     XLO(19,BOT,16,0),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"btlr-",    XLO(19,BOT,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bbtr",     XLO(19,BOT,16,0),         XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
-{"btlrl",    XLO(19,BOT,16,1),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"btlrl-",   XLO(19,BOT,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bbtrl",    XLO(19,BOT,16,1),         XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
-{"btlr+",    XLO(19,BOTP,16,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"btlrl+",   XLO(19,BOTP,16,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"btlr-",    XLO(19,BOTM4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"btlrl-",   XLO(19,BOTM4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"btlr+",    XLO(19,BOTP4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"btlrl+",   XLO(19,BOTP4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-
-{"bclr-",    XLYLK(19,16,0,0),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
-{"bclrl-",   XLYLK(19,16,0,1),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
-{"bclr+",    XLYLK(19,16,1,0),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
-{"bclrl+",   XLYLK(19,16,1,1),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
-{"bclr",     XLLK(19,16,0),            XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
-{"bcr",      XLLK(19,16,0),            XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
-{"bclrl",    XLLK(19,16,1),            XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
-{"bcrl",     XLLK(19,16,1),            XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
-
-{"rfid",       XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
-
-{"crnot",      XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
-{"crnor",      XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-{"rfmci",      X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
-
-{"rfdi",       XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
-{"rfi",                XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
-{"rfci",       XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
-
-{"rfsvc",      XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
-
-{"rfgi",       XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
-
-{"crandc",     XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-
-{"rfebb",      XL(19,146),     XLS_MASK,    POWER8,    PPCNONE,        {SXL}},
-
-{"isync",      XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
-{"ics",                XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
-
-{"crclr",      XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
-{"crxor",      XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-
-{"dnh",                X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
-
-{"crnand",     XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-
-{"crand",      XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-
-{"hrfid",      XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
-
-{"crset",      XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
-{"creqv",      XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-
-{"urfid",      XL(19,306),     0xffffffff,  POWER9,    PPCNONE,        {0}},
-{"stop",       XL(19,370),     0xffffffff,  POWER9,    PPCNONE,        {0}},
-
-{"doze",       XL(19,402),     0xffffffff,  POWER6,    POWER9,         {0}},
-
-{"crorc",      XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-
-{"nap",                XL(19,434),     0xffffffff,  POWER6,    POWER9,         {0}},
-
-{"crmove",     XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
-{"cror",       XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
-
-{"sleep",      XL(19,466),     0xffffffff,  POWER6,    POWER9,         {0}},
-{"rvwinkle",   XL(19,498),     0xffffffff,  POWER6,    POWER9,         {0}},
-
-{"bctr",    XLO(19,BOU,528,0),         XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
-{"bctrl",   XLO(19,BOU,528,1),         XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
-
-{"bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"blectr-", XLOCB(19,BOFM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"blectr+", XLOCB(19,BOFP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
-{"bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2,        {CR}},
-{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCNONE,       {CR}},
-
-{"bfctr",   XLO(19,BOF,528,0),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bfctr-",  XLO(19,BOF,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bfctrl",  XLO(19,BOF,528,1),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"bfctrl-", XLO(19,BOF,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bfctr+",  XLO(19,BOFP,528,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bfctrl+", XLO(19,BOFP,528,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"bfctr-",  XLO(19,BOFM4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"bfctrl-", XLO(19,BOFM4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"bfctr+",  XLO(19,BOFP4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"bfctrl+", XLO(19,BOFP4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"btctr",   XLO(19,BOT,528,0),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"btctr-",  XLO(19,BOT,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"btctrl",  XLO(19,BOT,528,1),         XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
-{"btctrl-", XLO(19,BOT,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"btctr+",  XLO(19,BOTP,528,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"btctrl+", XLO(19,BOTP,528,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2,        {BI}},
-{"btctr-",  XLO(19,BOTM4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"btctrl-", XLO(19,BOTM4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"btctr+",  XLO(19,BOTP4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-{"btctrl+", XLO(19,BOTP4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCNONE,       {BI}},
-
-{"bcctr-",  XLYLK(19,528,0,0),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
-{"bcctrl-", XLYLK(19,528,0,1),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
-{"bcctr+",  XLYLK(19,528,1,0),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
-{"bcctrl+", XLYLK(19,528,1,1),         XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
-{"bcctr",   XLLK(19,528,0),            XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
-{"bcc",     XLLK(19,528,0),            XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
-{"bcctrl",  XLLK(19,528,1),            XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
-{"bccl",    XLLK(19,528,1),            XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
-
-{"bctar-",  XLYLK(19,560,0,0),         XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
-{"bctarl-", XLYLK(19,560,0,1),         XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
-{"bctar+",  XLYLK(19,560,1,0),         XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
-{"bctarl+", XLYLK(19,560,1,1),         XLYBB_MASK,    POWER8,   PPCNONE,       {BOE, BI}},
-{"bctar",   XLLK(19,560,0),            XLBH_MASK,     POWER8,   PPCNONE,       {BO, BI, BH}},
-{"bctarl",  XLLK(19,560,1),            XLBH_MASK,     POWER8,   PPCNONE,       {BO, BI, BH}},
-
-{"rlwimi",     M(20,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
-{"rlimi",      M(20,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
-
-{"rlwimi.",    M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
-{"rlimi.",     M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
-
-{"rotlwi",     MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
-{"clrlwi",     MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
-{"rlwinm",     M(21,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
-{"rlinm",      M(21,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
-{"rotlwi.",    MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
-{"clrlwi.",    MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
-{"rlwinm.",    M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
-{"rlinm.",     M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
-
-{"rlmi",       M(22,0),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
-{"rlmi.",      M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
-
-{"rotlw",      MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
-{"rlwnm",      M(23,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
-{"rlnm",       M(23,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
-{"rotlw.",     MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
-{"rlwnm.",     M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
-{"rlnm.",      M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
-
-{"nop",                OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
-{"ori",                OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
-{"oril",       OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
-
-{"oris",       OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
-{"oriu",       OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
-
-{"xnop",       OP(26),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
-{"xori",       OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
-{"xoril",      OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
-
-{"xoris",      OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
-{"xoriu",      OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
-
-{"andi.",      OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
-{"andil.",     OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
-
-{"andis.",     OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
-{"andiu.",     OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
-
-{"rotldi",     MD(30,0,0),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
-{"clrldi",     MD(30,0,0),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
-{"rldicl",     MD(30,0,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
-{"rotldi.",    MD(30,0,1),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
-{"clrldi.",    MD(30,0,1),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
-{"rldicl.",    MD(30,0,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
-
-{"rldicr",     MD(30,1,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
-{"rldicr.",    MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
-
-{"rldic",      MD(30,2,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
-{"rldic.",     MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
-
-{"rldimi",     MD(30,3,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
-{"rldimi.",    MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
-
-{"rotld",      MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
-{"rldcl",      MDS(30,8,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
-{"rotld.",     MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
-{"rldcl.",     MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
-
-{"rldcr",      MDS(30,9,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
-{"rldcr.",     MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
-
-{"cmpw",       XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
-{"cmpd",       XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
-{"cmp",                X(31,0),        XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
+{"maclhwso",   XO (4, 492,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"maclhwso.",  XO (4, 492,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmaclhwso",  XO (4, 494,1,0), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"nmaclhwso.", XO (4, 494,1,1), XO_MASK,    MULHW,     0,              {RT, RA, RB}},
+{"dcbz_l",     X  (4,1014),    XRT_MASK,    PPCPS,     0,              {RA, RB}},
+
+{"mulli",      OP(7),          OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, SI}},
+{"muli",       OP(7),          OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA, SI}},
+
+{"subfic",     OP(8),          OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, SI}},
+{"sfi",                OP(8),          OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA, SI}},
+
+{"dozi",       OP(9),          OP_MASK,     M601,      PPCVLE,         {RT, RA, SI}},
+
+{"cmplwi",     OPL(10,0),      OPL_MASK,    PPCCOM,    PPCVLE,         {OBF, RA, UISIGNOPT}},
+{"cmpldi",     OPL(10,1),      OPL_MASK,    PPC64,     PPCVLE,         {OBF, RA, UISIGNOPT}},
+{"cmpli",      OP(10),         OP_MASK,     PPC,       PPCVLE,         {BF, L, RA, UISIGNOPT}},
+{"cmpli",      OP(10),         OP_MASK,     PWRCOM,    PPC|PPCVLE,     {BF, RA, UISIGNOPT}},
+
+{"cmpwi",      OPL(11,0),      OPL_MASK,    PPCCOM,    PPCVLE,         {OBF, RA, SI}},
+{"cmpdi",      OPL(11,1),      OPL_MASK,    PPC64,     PPCVLE,         {OBF, RA, SI}},
+{"cmpi",       OP(11),         OP_MASK,     PPC,       PPCVLE,         {BF, L, RA, SI}},
+{"cmpi",       OP(11),         OP_MASK,     PWRCOM,    PPC|PPCVLE,     {BF, RA, SI}},
+
+{"addic",      OP(12),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, SI}},
+{"ai",         OP(12),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA, SI}},
+{"subic",      OP(12),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, NSI}},
+
+{"addic.",     OP(13),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, SI}},
+{"ai.",                OP(13),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA, SI}},
+{"subic.",     OP(13),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA, NSI}},
+
+{"li",         OP(14),         DRA_MASK,    PPCCOM,    PPCVLE,         {RT, SI}},
+{"lil",                OP(14),         DRA_MASK,    PWRCOM,    PPCVLE,         {RT, SI}},
+{"addi",       OP(14),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA0, SI}},
+{"cal",                OP(14),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, D, RA0}},
+{"subi",       OP(14),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA0, NSI}},
+{"la",         OP(14),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, D, RA0}},
+
+{"lis",                OP(15),         DRA_MASK,    PPCCOM,    PPCVLE,         {RT, SISIGNOPT}},
+{"liu",                OP(15),         DRA_MASK,    PWRCOM,    PPCVLE,         {RT, SISIGNOPT}},
+{"addis",      OP(15),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA0, SISIGNOPT}},
+{"cau",                OP(15),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, RA0, SISIGNOPT}},
+{"subis",      OP(15),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, RA0, NSISIGNOPT}},
+
+{"bdnz-",    BBO(16,BODNZ,0,0),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDM}},
+{"bdnz+",    BBO(16,BODNZ,0,0),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDP}},
+{"bdnz",     BBO(16,BODNZ,0,0),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BD}},
+{"bdn",             BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCVLE,        {BD}},
+{"bdnzl-",   BBO(16,BODNZ,0,1),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDM}},
+{"bdnzl+",   BBO(16,BODNZ,0,1),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDP}},
+{"bdnzl",    BBO(16,BODNZ,0,1),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BD}},
+{"bdnl",     BBO(16,BODNZ,0,1),                BBOATBI_MASK,  PWRCOM,   PPCVLE,        {BD}},
+{"bdnza-",   BBO(16,BODNZ,1,0),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDMA}},
+{"bdnza+",   BBO(16,BODNZ,1,0),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDPA}},
+{"bdnza",    BBO(16,BODNZ,1,0),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDA}},
+{"bdna",     BBO(16,BODNZ,1,0),                BBOATBI_MASK,  PWRCOM,   PPCVLE,        {BDA}},
+{"bdnzla-",  BBO(16,BODNZ,1,1),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDMA}},
+{"bdnzla+",  BBO(16,BODNZ,1,1),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDPA}},
+{"bdnzla",   BBO(16,BODNZ,1,1),                BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDA}},
+{"bdnla",    BBO(16,BODNZ,1,1),                BBOATBI_MASK,  PWRCOM,   PPCVLE,        {BDA}},
+{"bdz-",     BBO(16,BODZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDM}},
+{"bdz+",     BBO(16,BODZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDP}},
+{"bdz",             BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCVLE,        {BD}},
+{"bdzl-",    BBO(16,BODZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDM}},
+{"bdzl+",    BBO(16,BODZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDP}},
+{"bdzl",     BBO(16,BODZ,0,1),         BBOATBI_MASK,  COM,      PPCVLE,        {BD}},
+{"bdza-",    BBO(16,BODZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDMA}},
+{"bdza+",    BBO(16,BODZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDPA}},
+{"bdza",     BBO(16,BODZ,1,0),         BBOATBI_MASK,  COM,      PPCVLE,        {BDA}},
+{"bdzla-",   BBO(16,BODZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDMA}},
+{"bdzla+",   BBO(16,BODZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCVLE,        {BDPA}},
+{"bdzla",    BBO(16,BODZ,1,1),         BBOATBI_MASK,  COM,      PPCVLE,        {BDA}},
+
+{"bge-",     BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bge+",     BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bge",             BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bnl-",     BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bnl+",     BBOCB(16,BOF,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bnl",             BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bgel-",    BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bgel+",    BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bgel",     BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bnll-",    BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bnll+",    BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bnll",     BBOCB(16,BOF,CBLT,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bgea-",    BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bgea+",    BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bgea",     BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bnla-",    BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnla+",    BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnla",     BBOCB(16,BOF,CBLT,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bgela-",   BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bgela+",   BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bgela",    BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bnlla-",   BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnlla+",   BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnlla",    BBOCB(16,BOF,CBLT,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"ble-",     BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"ble+",     BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"ble",             BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bng-",     BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bng+",     BBOCB(16,BOF,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bng",             BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"blel-",    BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"blel+",    BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"blel",     BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bngl-",    BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bngl+",    BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bngl",     BBOCB(16,BOF,CBGT,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"blea-",    BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"blea+",    BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"blea",     BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bnga-",    BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnga+",    BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnga",     BBOCB(16,BOF,CBGT,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"blela-",   BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"blela+",   BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"blela",    BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bngla-",   BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bngla+",   BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bngla",    BBOCB(16,BOF,CBGT,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bne-",     BBOCB(16,BOF,CBEQ,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bne+",     BBOCB(16,BOF,CBEQ,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bne",             BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bnel-",    BBOCB(16,BOF,CBEQ,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bnel+",    BBOCB(16,BOF,CBEQ,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bnel",     BBOCB(16,BOF,CBEQ,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bnea-",    BBOCB(16,BOF,CBEQ,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnea+",    BBOCB(16,BOF,CBEQ,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnea",     BBOCB(16,BOF,CBEQ,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bnela-",   BBOCB(16,BOF,CBEQ,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnela+",   BBOCB(16,BOF,CBEQ,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnela",    BBOCB(16,BOF,CBEQ,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bns-",     BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bns+",     BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bns",             BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bnu-",     BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bnu+",     BBOCB(16,BOF,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bnu",             BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BD}},
+{"bnsl-",    BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bnsl+",    BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bnsl",     BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bnul-",    BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bnul+",    BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bnul",     BBOCB(16,BOF,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BD}},
+{"bnsa-",    BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnsa+",    BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnsa",     BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bnua-",    BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnua+",    BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnua",     BBOCB(16,BOF,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDA}},
+{"bnsla-",   BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnsla+",   BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnsla",    BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bnula-",   BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bnula+",   BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bnula",    BBOCB(16,BOF,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDA}},
+
+{"blt-",     BBOCB(16,BOT,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"blt+",     BBOCB(16,BOT,CBLT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"blt",             BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bltl-",    BBOCB(16,BOT,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bltl+",    BBOCB(16,BOT,CBLT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bltl",     BBOCB(16,BOT,CBLT,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"blta-",    BBOCB(16,BOT,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"blta+",    BBOCB(16,BOT,CBLT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"blta",     BBOCB(16,BOT,CBLT,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bltla-",   BBOCB(16,BOT,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bltla+",   BBOCB(16,BOT,CBLT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bltla",    BBOCB(16,BOT,CBLT,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bgt-",     BBOCB(16,BOT,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bgt+",     BBOCB(16,BOT,CBGT,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bgt",             BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bgtl-",    BBOCB(16,BOT,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bgtl+",    BBOCB(16,BOT,CBGT,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bgtl",     BBOCB(16,BOT,CBGT,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bgta-",    BBOCB(16,BOT,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bgta+",    BBOCB(16,BOT,CBGT,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bgta",     BBOCB(16,BOT,CBGT,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bgtla-",   BBOCB(16,BOT,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bgtla+",   BBOCB(16,BOT,CBGT,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bgtla",    BBOCB(16,BOT,CBGT,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"beq-",     BBOCB(16,BOT,CBEQ,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"beq+",     BBOCB(16,BOT,CBEQ,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"beq",             BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"beql-",    BBOCB(16,BOT,CBEQ,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"beql+",    BBOCB(16,BOT,CBEQ,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"beql",     BBOCB(16,BOT,CBEQ,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"beqa-",    BBOCB(16,BOT,CBEQ,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"beqa+",    BBOCB(16,BOT,CBEQ,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"beqa",     BBOCB(16,BOT,CBEQ,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"beqla-",   BBOCB(16,BOT,CBEQ,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"beqla+",   BBOCB(16,BOT,CBEQ,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"beqla",    BBOCB(16,BOT,CBEQ,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bso-",     BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bso+",     BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bso",             BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bun-",     BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bun+",     BBOCB(16,BOT,CBSO,0,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bun",             BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BD}},
+{"bsol-",    BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bsol+",    BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bsol",     BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BD}},
+{"bunl-",    BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDM}},
+{"bunl+",    BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDP}},
+{"bunl",     BBOCB(16,BOT,CBSO,0,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BD}},
+{"bsoa-",    BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bsoa+",    BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bsoa",     BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"buna-",    BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"buna+",    BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"buna",     BBOCB(16,BOT,CBSO,1,0),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDA}},
+{"bsola-",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bsola+",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bsola",    BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  COM,      PPCVLE,        {CR, BDA}},
+{"bunla-",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDMA}},
+{"bunla+",   BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDPA}},
+{"bunla",    BBOCB(16,BOT,CBSO,1,1),   BBOATCB_MASK,  PPCCOM,   PPCVLE,        {CR, BDA}},
+
+{"bdnzf-",   BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDM}},
+{"bdnzf+",   BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDP}},
+{"bdnzf",    BBO(16,BODNZF,0,0),       BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BD}},
+{"bdnzfl-",  BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDM}},
+{"bdnzfl+",  BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDP}},
+{"bdnzfl",   BBO(16,BODNZF,0,1),       BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BD}},
+{"bdnzfa-",  BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDMA}},
+{"bdnzfa+",  BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDPA}},
+{"bdnzfa",   BBO(16,BODNZF,1,0),       BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bdnzfla-", BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDMA}},
+{"bdnzfla+", BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDPA}},
+{"bdnzfla",  BBO(16,BODNZF,1,1),       BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bdzf-",    BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDM}},
+{"bdzf+",    BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDP}},
+{"bdzf",     BBO(16,BODZF,0,0),                BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BD}},
+{"bdzfl-",   BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDM}},
+{"bdzfl+",   BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDP}},
+{"bdzfl",    BBO(16,BODZF,0,1),                BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BD}},
+{"bdzfa-",   BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDMA}},
+{"bdzfa+",   BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDPA}},
+{"bdzfa",    BBO(16,BODZF,1,0),                BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bdzfla-",  BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDMA}},
+{"bdzfla+",  BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDPA}},
+{"bdzfla",   BBO(16,BODZF,1,1),                BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BDA}},
+
+{"bf-",             BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDM}},
+{"bf+",             BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDP}},
+{"bf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BD}},
+{"bbf",             BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   PPCVLE,        {BI, BD}},
+{"bfl-",     BBO(16,BOF,0,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDM}},
+{"bfl+",     BBO(16,BOF,0,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDP}},
+{"bfl",             BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BD}},
+{"bbfl",     BBO(16,BOF,0,1),          BBOAT_MASK,    PWRCOM,   PPCVLE,        {BI, BD}},
+{"bfa-",     BBO(16,BOF,1,0),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDMA}},
+{"bfa+",     BBO(16,BOF,1,0),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDPA}},
+{"bfa",             BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bbfa",     BBO(16,BOF,1,0),          BBOAT_MASK,    PWRCOM,   PPCVLE,        {BI, BDA}},
+{"bfla-",    BBO(16,BOF,1,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDMA}},
+{"bfla+",    BBO(16,BOF,1,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDPA}},
+{"bfla",     BBO(16,BOF,1,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bbfla",    BBO(16,BOF,1,1),          BBOAT_MASK,    PWRCOM,   PPCVLE,        {BI, BDA}},
+
+{"bdnzt-",   BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDM}},
+{"bdnzt+",   BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDP}},
+{"bdnzt",    BBO(16,BODNZT,0,0),       BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BD}},
+{"bdnztl-",  BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDM}},
+{"bdnztl+",  BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDP}},
+{"bdnztl",   BBO(16,BODNZT,0,1),       BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BD}},
+{"bdnzta-",  BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDMA}},
+{"bdnzta+",  BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDPA}},
+{"bdnzta",   BBO(16,BODNZT,1,0),       BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bdnztla-", BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDMA}},
+{"bdnztla+", BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDPA}},
+{"bdnztla",  BBO(16,BODNZT,1,1),       BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bdzt-",    BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDM}},
+{"bdzt+",    BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDP}},
+{"bdzt",     BBO(16,BODZT,0,0),                BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BD}},
+{"bdztl-",   BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDM}},
+{"bdztl+",   BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDP}},
+{"bdztl",    BBO(16,BODZT,0,1),                BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BD}},
+{"bdzta-",   BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDMA}},
+{"bdzta+",   BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDPA}},
+{"bdzta",    BBO(16,BODZT,1,0),                BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bdztla-",  BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDMA}},
+{"bdztla+",  BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   ISA_V2|PPCVLE, {BI, BDPA}},
+{"bdztla",   BBO(16,BODZT,1,1),                BBOY_MASK,     PPCCOM,   PPCVLE,        {BI, BDA}},
+
+{"bt-",             BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDM}},
+{"bt+",             BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDP}},
+{"bt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BD}},
+{"bbt",             BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   PPCVLE,        {BI, BD}},
+{"btl-",     BBO(16,BOT,0,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDM}},
+{"btl+",     BBO(16,BOT,0,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDP}},
+{"btl",             BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BD}},
+{"bbtl",     BBO(16,BOT,0,1),          BBOAT_MASK,    PWRCOM,   PPCVLE,        {BI, BD}},
+{"bta-",     BBO(16,BOT,1,0),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDMA}},
+{"bta+",     BBO(16,BOT,1,0),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDPA}},
+{"bta",             BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bbta",     BBO(16,BOT,1,0),          BBOAT_MASK,    PWRCOM,   PPCVLE,        {BI, BDA}},
+{"btla-",    BBO(16,BOT,1,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDMA}},
+{"btla+",    BBO(16,BOT,1,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDPA}},
+{"btla",     BBO(16,BOT,1,1),          BBOAT_MASK,    PPCCOM,   PPCVLE,        {BI, BDA}},
+{"bbtla",    BBO(16,BOT,1,1),          BBOAT_MASK,    PWRCOM,   PPCVLE,        {BI, BDA}},
+
+{"bc-",                B(16,0,0),      B_MASK,      PPCCOM,    PPCVLE,         {BOE, BI, BDM}},
+{"bc+",                B(16,0,0),      B_MASK,      PPCCOM,    PPCVLE,         {BOE, BI, BDP}},
+{"bc",         B(16,0,0),      B_MASK,      COM,       PPCVLE,         {BO, BI, BD}},
+{"bcl-",       B(16,0,1),      B_MASK,      PPCCOM,    PPCVLE,         {BOE, BI, BDM}},
+{"bcl+",       B(16,0,1),      B_MASK,      PPCCOM,    PPCVLE,         {BOE, BI, BDP}},
+{"bcl",                B(16,0,1),      B_MASK,      COM,       PPCVLE,         {BO, BI, BD}},
+{"bca-",       B(16,1,0),      B_MASK,      PPCCOM,    PPCVLE,         {BOE, BI, BDMA}},
+{"bca+",       B(16,1,0),      B_MASK,      PPCCOM,    PPCVLE,         {BOE, BI, BDPA}},
+{"bca",                B(16,1,0),      B_MASK,      COM,       PPCVLE,         {BO, BI, BDA}},
+{"bcla-",      B(16,1,1),      B_MASK,      PPCCOM,    PPCVLE,         {BOE, BI, BDMA}},
+{"bcla+",      B(16,1,1),      B_MASK,      PPCCOM,    PPCVLE,         {BOE, BI, BDPA}},
+{"bcla",       B(16,1,1),      B_MASK,      COM,       PPCVLE,         {BO, BI, BDA}},
+
+{"svc",                SC(17,0,0),     SC_MASK,     POWER,     PPCVLE,         {SVC_LEV, FL1, FL2}},
+{"svcl",       SC(17,0,1),     SC_MASK,     POWER,     PPCVLE,         {SVC_LEV, FL1, FL2}},
+{"sc",         SC(17,1,0),     SC_MASK,     PPC,       PPCVLE,         {LEV}},
+{"svca",       SC(17,1,0),     SC_MASK,     PWRCOM,    PPCVLE,         {SV}},
+{"svcla",      SC(17,1,1),     SC_MASK,     POWER,     PPCVLE,         {SV}},
+
+{"b",          B(18,0,0),      B_MASK,      COM,       PPCVLE,         {LI}},
+{"bl",         B(18,0,1),      B_MASK,      COM,       PPCVLE,         {LI}},
+{"ba",         B(18,1,0),      B_MASK,      COM,       PPCVLE,         {LIA}},
+{"bla",                B(18,1,1),      B_MASK,      COM,       PPCVLE,         {LIA}},
+
+{"mcrf",     XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE,         {BF, BFA}},
+
+{"addpcis",  DX(19,2),         DX_MASK,     POWER9,    PPCVLE,         {RT, DXD}},
+{"subpcis",  DX(19,2),         DX_MASK,     POWER9,    PPCVLE,         {RT, NDXD}},
+
+{"bdnzlr",   XLO(19,BODNZ,16,0),       XLBOBIBB_MASK, PPCCOM,   PPCVLE,        {0}},
+{"bdnzlr-",  XLO(19,BODNZ,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {0}},
+{"bdnzlrl",  XLO(19,BODNZ,16,1),       XLBOBIBB_MASK, PPCCOM,   PPCVLE,        {0}},
+{"bdnzlrl-", XLO(19,BODNZ,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {0}},
+{"bdnzlr+",  XLO(19,BODNZP,16,0),      XLBOBIBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {0}},
+{"bdnzlrl+", XLO(19,BODNZP,16,1),      XLBOBIBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {0}},
+{"bdzlr",    XLO(19,BODZ,16,0),                XLBOBIBB_MASK, PPCCOM,   PPCVLE,        {0}},
+{"bdzlr-",   XLO(19,BODZ,16,0),                XLBOBIBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {0}},
+{"bdzlrl",   XLO(19,BODZ,16,1),                XLBOBIBB_MASK, PPCCOM,   PPCVLE,        {0}},
+{"bdzlrl-",  XLO(19,BODZ,16,1),                XLBOBIBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {0}},
+{"bdzlr+",   XLO(19,BODZP,16,0),       XLBOBIBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {0}},
+{"bdzlrl+",  XLO(19,BODZP,16,1),       XLBOBIBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {0}},
+{"blr",             XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCVLE,        {0}},
+{"br",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCVLE,        {0}},
+{"blrl",     XLO(19,BOU,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCVLE,        {0}},
+{"brl",             XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCVLE,        {0}},
+{"bdnzlr-",  XLO(19,BODNZM4,16,0),     XLBOBIBB_MASK, ISA_V2,   PPCVLE,        {0}},
+{"bdnzlrl-", XLO(19,BODNZM4,16,1),     XLBOBIBB_MASK, ISA_V2,   PPCVLE,        {0}},
+{"bdnzlr+",  XLO(19,BODNZP4,16,0),     XLBOBIBB_MASK, ISA_V2,   PPCVLE,        {0}},
+{"bdnzlrl+", XLO(19,BODNZP4,16,1),     XLBOBIBB_MASK, ISA_V2,   PPCVLE,        {0}},
+{"bdzlr-",   XLO(19,BODZM4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCVLE,        {0}},
+{"bdzlrl-",  XLO(19,BODZM4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCVLE,        {0}},
+{"bdzlr+",   XLO(19,BODZP4,16,0),      XLBOBIBB_MASK, ISA_V2,   PPCVLE,        {0}},
+{"bdzlrl+",  XLO(19,BODZP4,16,1),      XLBOBIBB_MASK, ISA_V2,   PPCVLE,        {0}},
+
+{"bgelr",    XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bgelr-",   XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bger",     XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnllr",    XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnllr-",   XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnlr",     XLOCB(19,BOF,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bgelrl",   XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgerl",    XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnllrl",   XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnlrl",    XLOCB(19,BOF,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"blelr",    XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"blelr-",   XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bler",     XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnglr",    XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnglr-",   XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bngr",     XLOCB(19,BOF,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"blelrl",   XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"blelrl-",  XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"blerl",    XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnglrl",   XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bngrl",    XLOCB(19,BOF,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnelr",    XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bner",     XLOCB(19,BOF,CBEQ,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnerl",    XLOCB(19,BOF,CBEQ,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnslr",    XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnslr-",   XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnsr",     XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnulr",    XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnulr-",   XLOCB(19,BOF,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnslrl",   XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnsrl",    XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bnulrl",   XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgelr+",   XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnllr+",   XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"blelr+",   XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnglr+",   XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"blelrl+",  XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnslr+",   XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnulr+",   XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"blelr-",   XLOCB(19,BOFM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"blelr+",   XLOCB(19,BOFP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bltlr",    XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bltlr-",   XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltr",     XLOCB(19,BOT,CBLT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bltlrl",   XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltrl",    XLOCB(19,BOT,CBLT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bgtlr",    XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgtr",     XLOCB(19,BOT,CBGT,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgtrl",    XLOCB(19,BOT,CBGT,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"beqlr",    XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"beqr",     XLOCB(19,BOT,CBEQ,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"beqrl",    XLOCB(19,BOT,CBEQ,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bsolr",    XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bsolr-",   XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsor",     XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bunlr",    XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bunlr-",   XLOCB(19,BOT,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsolrl",   XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsorl",    XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PWRCOM,   PPCVLE,        {CR}},
+{"bunlrl",   XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltlr+",   XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsolr+",   XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bunlr+",   XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+
+{"bdnzflr",  XLO(19,BODNZF,16,0),      XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bdnzflr-", XLO(19,BODNZF,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdnzflrl", XLO(19,BODNZF,16,1),      XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bdnzflrl-",XLO(19,BODNZF,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdnzflr+", XLO(19,BODNZFP,16,0),     XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdnzflrl+",XLO(19,BODNZFP,16,1),     XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdzflr",   XLO(19,BODZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bdzflr-",  XLO(19,BODZF,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdzflrl",  XLO(19,BODZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bdzflrl-", XLO(19,BODZF,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdzflr+",  XLO(19,BODZFP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdzflrl+", XLO(19,BODZFP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bflr",     XLO(19,BOF,16,0),         XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bflr-",    XLO(19,BOF,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bbfr",     XLO(19,BOF,16,0),         XLBOBB_MASK,   PWRCOM,   PPCVLE,        {BI}},
+{"bflrl",    XLO(19,BOF,16,1),         XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bflrl-",   XLO(19,BOF,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bbfrl",    XLO(19,BOF,16,1),         XLBOBB_MASK,   PWRCOM,   PPCVLE,        {BI}},
+{"bflr+",    XLO(19,BOFP,16,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bflrl+",   XLO(19,BOFP,16,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bflr-",    XLO(19,BOFM4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"bflrl-",   XLO(19,BOFM4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"bflr+",    XLO(19,BOFP4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"bflrl+",   XLO(19,BOFP4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"bdnztlr",  XLO(19,BODNZT,16,0),      XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bdnztlr-", XLO(19,BODNZT,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdnztlrl", XLO(19,BODNZT,16,1),      XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bdnztlrl-", XLO(19,BODNZT,16,1),     XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdnztlr+", XLO(19,BODNZTP,16,0),     XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdnztlrl+", XLO(19,BODNZTP,16,1),    XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdztlr",   XLO(19,BODZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bdztlr-",  XLO(19,BODZT,16,0),       XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdztlrl",  XLO(19,BODZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bdztlrl-", XLO(19,BODZT,16,1),       XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdztlr+",  XLO(19,BODZTP,16,0),      XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bdztlrl+", XLO(19,BODZTP,16,1),      XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"btlr",     XLO(19,BOT,16,0),         XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"btlr-",    XLO(19,BOT,16,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bbtr",     XLO(19,BOT,16,0),         XLBOBB_MASK,   PWRCOM,   PPCVLE,        {BI}},
+{"btlrl",    XLO(19,BOT,16,1),         XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"btlrl-",   XLO(19,BOT,16,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bbtrl",    XLO(19,BOT,16,1),         XLBOBB_MASK,   PWRCOM,   PPCVLE,        {BI}},
+{"btlr+",    XLO(19,BOTP,16,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"btlrl+",   XLO(19,BOTP,16,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"btlr-",    XLO(19,BOTM4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"btlrl-",   XLO(19,BOTM4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"btlr+",    XLO(19,BOTP4,16,0),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"btlrl+",   XLO(19,BOTP4,16,1),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+
+{"bclr-",    XLYLK(19,16,0,0),         XLYBB_MASK,    PPCCOM,   PPCVLE,        {BOE, BI}},
+{"bclrl-",   XLYLK(19,16,0,1),         XLYBB_MASK,    PPCCOM,   PPCVLE,        {BOE, BI}},
+{"bclr+",    XLYLK(19,16,1,0),         XLYBB_MASK,    PPCCOM,   PPCVLE,        {BOE, BI}},
+{"bclrl+",   XLYLK(19,16,1,1),         XLYBB_MASK,    PPCCOM,   PPCVLE,        {BOE, BI}},
+{"bclr",     XLLK(19,16,0),            XLBH_MASK,     PPCCOM,   PPCVLE,        {BO, BI, BH}},
+{"bcr",             XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   PPCVLE,        {BO, BI}},
+{"bclrl",    XLLK(19,16,1),            XLBH_MASK,     PPCCOM,   PPCVLE,        {BO, BI, BH}},
+{"bcrl",     XLLK(19,16,1),            XLBB_MASK,     PWRCOM,   PPCVLE,        {BO, BI}},
+
+{"rfid",       XL(19,18),      0xffffffff,  PPC64,     PPCVLE, {0}},
+
+{"crnot",      XL(19,33),      XL_MASK,     PPCCOM,    PPCVLE,         {BT, BA, BBA}},
+{"crnor",      XL(19,33),      XL_MASK,     COM,       PPCVLE,         {BT, BA, BB}},
+{"rfmci",      X(19,38),    0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
+
+{"rfdi",       XL(19,39),      0xffffffff,  E500MC,    PPCVLE,         {0}},
+{"rfi",                XL(19,50),      0xffffffff,  COM,       PPCVLE,         {0}},
+{"rfci",       XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
+
+{"rfsvc",      XL(19,82),      0xffffffff,  POWER,     PPCVLE,         {0}},
+
+{"rfgi",       XL(19,102),   0xffffffff, E500MC|PPCA2, PPCVLE,         {0}},
+
+{"crandc",     XL(19,129),     XL_MASK,     COM,       PPCVLE,         {BT, BA, BB}},
+
+{"rfebb",      XL(19,146),     XLS_MASK,    POWER8,    PPCVLE,         {SXL}},
+
+{"isync",      XL(19,150),     0xffffffff,  PPCCOM,    PPCVLE,         {0}},
+{"ics",                XL(19,150),     0xffffffff,  PWRCOM,    PPCVLE,         {0}},
+
+{"crclr",      XL(19,193),     XL_MASK,     PPCCOM,    PPCVLE,         {BT, BAT, BBA}},
+{"crxor",      XL(19,193),     XL_MASK,     COM,       PPCVLE,         {BT, BA, BB}},
+
+{"dnh",                X(19,198),      X_MASK,      E500MC,    PPCVLE,         {DUI, DUIS}},
+
+{"crnand",     XL(19,225),     XL_MASK,     COM,       PPCVLE,         {BT, BA, BB}},
+
+{"crand",      XL(19,257),     XL_MASK,     COM,       PPCVLE,         {BT, BA, BB}},
+
+{"hrfid",      XL(19,274),    0xffffffff, POWER5|CELL, PPC476|PPCVLE,  {0}},
+
+{"crset",      XL(19,289),     XL_MASK,     PPCCOM,    PPCVLE,         {BT, BAT, BBA}},
+{"creqv",      XL(19,289),     XL_MASK,     COM,       PPCVLE,         {BT, BA, BB}},
+
+{"urfid",      XL(19,306),     0xffffffff,  POWER9,    PPCVLE,         {0}},
+{"stop",       XL(19,370),     0xffffffff,  POWER9,    PPCVLE,         {0}},
+
+{"doze",       XL(19,402),     0xffffffff,  POWER6,    POWER9|PPCVLE,  {0}},
+
+{"crorc",      XL(19,417),     XL_MASK,     COM,       PPCVLE,         {BT, BA, BB}},
+
+{"nap",                XL(19,434),     0xffffffff,  POWER6,    POWER9|PPCVLE,  {0}},
+
+{"crmove",     XL(19,449),     XL_MASK,     PPCCOM,    PPCVLE,         {BT, BA, BBA}},
+{"cror",       XL(19,449),     XL_MASK,     COM,       PPCVLE,         {BT, BA, BB}},
+
+{"sleep",      XL(19,466),     0xffffffff,  POWER6,    POWER9|PPCVLE,  {0}},
+{"rvwinkle",   XL(19,498),     0xffffffff,  POWER6,    POWER9|PPCVLE,  {0}},
+
+{"bctr",    XLO(19,BOU,528,0),         XLBOBIBB_MASK, COM,      PPCVLE,        {0}},
+{"bctrl",   XLO(19,BOU,528,1),         XLBOBIBB_MASK, COM,      PPCVLE,        {0}},
+
+{"bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"blectr-", XLOCB(19,BOFM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"blectr+", XLOCB(19,BOFP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   PPCVLE,        {CR}},
+{"bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM,   ISA_V2|PPCVLE, {CR}},
+{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1),        XLBOCBBB_MASK, ISA_V2,   PPCVLE,        {CR}},
+
+{"bfctr",   XLO(19,BOF,528,0),         XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bfctr-",  XLO(19,BOF,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bfctrl",  XLO(19,BOF,528,1),         XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"bfctrl-", XLO(19,BOF,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bfctr+",  XLO(19,BOFP,528,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bfctrl+", XLO(19,BOFP,528,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"bfctr-",  XLO(19,BOFM4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"bfctrl-", XLO(19,BOFM4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"bfctr+",  XLO(19,BOFP4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"bfctrl+", XLO(19,BOFP4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"btctr",   XLO(19,BOT,528,0),         XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"btctr-",  XLO(19,BOT,528,0),         XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"btctrl",  XLO(19,BOT,528,1),         XLBOBB_MASK,   PPCCOM,   PPCVLE,        {BI}},
+{"btctrl-", XLO(19,BOT,528,1),         XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"btctr+",  XLO(19,BOTP,528,0),                XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"btctrl+", XLO(19,BOTP,528,1),                XLBOBB_MASK,   PPCCOM,   ISA_V2|PPCVLE, {BI}},
+{"btctr-",  XLO(19,BOTM4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"btctrl-", XLO(19,BOTM4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"btctr+",  XLO(19,BOTP4,528,0),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+{"btctrl+", XLO(19,BOTP4,528,1),       XLBOBB_MASK,   ISA_V2,   PPCVLE,        {BI}},
+
+{"bcctr-",  XLYLK(19,528,0,0),         XLYBB_MASK,    PPCCOM,   PPCVLE,        {BOE, BI}},
+{"bcctrl-", XLYLK(19,528,0,1),         XLYBB_MASK,    PPCCOM,   PPCVLE,        {BOE, BI}},
+{"bcctr+",  XLYLK(19,528,1,0),         XLYBB_MASK,    PPCCOM,   PPCVLE,        {BOE, BI}},
+{"bcctrl+", XLYLK(19,528,1,1),         XLYBB_MASK,    PPCCOM,   PPCVLE,        {BOE, BI}},
+{"bcctr",   XLLK(19,528,0),            XLBH_MASK,     PPCCOM,   PPCVLE,        {BO, BI, BH}},
+{"bcc",            XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   PPCVLE,        {BO, BI}},
+{"bcctrl",  XLLK(19,528,1),            XLBH_MASK,     PPCCOM,   PPCVLE,        {BO, BI, BH}},
+{"bccl",    XLLK(19,528,1),            XLBB_MASK,     PWRCOM,   PPCVLE,        {BO, BI}},
+
+{"bctar-",  XLYLK(19,560,0,0),         XLYBB_MASK,    POWER8,   PPCVLE,        {BOE, BI}},
+{"bctarl-", XLYLK(19,560,0,1),         XLYBB_MASK,    POWER8,   PPCVLE,        {BOE, BI}},
+{"bctar+",  XLYLK(19,560,1,0),         XLYBB_MASK,    POWER8,   PPCVLE,        {BOE, BI}},
+{"bctarl+", XLYLK(19,560,1,1),         XLYBB_MASK,    POWER8,   PPCVLE,        {BOE, BI}},
+{"bctar",   XLLK(19,560,0),            XLBH_MASK,     POWER8,   PPCVLE,        {BO, BI, BH}},
+{"bctarl",  XLLK(19,560,1),            XLBH_MASK,     POWER8,   PPCVLE,        {BO, BI, BH}},
+
+{"rlwimi",     M(20,0),        M_MASK,      PPCCOM,    PPCVLE,         {RA, RS, SH, MBE, ME}},
+{"rlimi",      M(20,0),        M_MASK,      PWRCOM,    PPCVLE,         {RA, RS, SH, MBE, ME}},
+
+{"rlwimi.",    M(20,1),        M_MASK,      PPCCOM,    PPCVLE,         {RA, RS, SH, MBE, ME}},
+{"rlimi.",     M(20,1),        M_MASK,      PWRCOM,    PPCVLE,         {RA, RS, SH, MBE, ME}},
+
+{"rotlwi",     MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCVLE,         {RA, RS, SH}},
+{"clrlwi",     MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCVLE,         {RA, RS, MB}},
+{"rlwinm",     M(21,0),        M_MASK,      PPCCOM,    PPCVLE,         {RA, RS, SH, MBE, ME}},
+{"rlinm",      M(21,0),        M_MASK,      PWRCOM,    PPCVLE,         {RA, RS, SH, MBE, ME}},
+{"rotlwi.",    MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCVLE,         {RA, RS, SH}},
+{"clrlwi.",    MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCVLE,         {RA, RS, MB}},
+{"rlwinm.",    M(21,1),        M_MASK,      PPCCOM,    PPCVLE,         {RA, RS, SH, MBE, ME}},
+{"rlinm.",     M(21,1),        M_MASK,      PWRCOM,    PPCVLE,         {RA, RS, SH, MBE, ME}},
+
+{"rlmi",       M(22,0),        M_MASK,      M601,      PPCVLE,         {RA, RS, RB, MBE, ME}},
+{"rlmi.",      M(22,1),        M_MASK,      M601,      PPCVLE,         {RA, RS, RB, MBE, ME}},
+
+{"rotlw",      MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCVLE,         {RA, RS, RB}},
+{"rlwnm",      M(23,0),        M_MASK,      PPCCOM,    PPCVLE,         {RA, RS, RB, MBE, ME}},
+{"rlnm",       M(23,0),        M_MASK,      PWRCOM,    PPCVLE,         {RA, RS, RB, MBE, ME}},
+{"rotlw.",     MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCVLE,         {RA, RS, RB}},
+{"rlwnm.",     M(23,1),        M_MASK,      PPCCOM,    PPCVLE,         {RA, RS, RB, MBE, ME}},
+{"rlnm.",      M(23,1),        M_MASK,      PWRCOM,    PPCVLE,         {RA, RS, RB, MBE, ME}},
+
+{"nop",                OP(24),         0xffffffff,  PPCCOM,    PPCVLE,         {0}},
+{"ori",                OP(24),         OP_MASK,     PPCCOM,    PPCVLE,         {RA, RS, UI}},
+{"oril",       OP(24),         OP_MASK,     PWRCOM,    PPCVLE,         {RA, RS, UI}},
+
+{"oris",       OP(25),         OP_MASK,     PPCCOM,    PPCVLE,         {RA, RS, UI}},
+{"oriu",       OP(25),         OP_MASK,     PWRCOM,    PPCVLE,         {RA, RS, UI}},
+
+{"xnop",       OP(26),         0xffffffff,  PPCCOM,    PPCVLE,         {0}},
+{"xori",       OP(26),         OP_MASK,     PPCCOM,    PPCVLE,         {RA, RS, UI}},
+{"xoril",      OP(26),         OP_MASK,     PWRCOM,    PPCVLE,         {RA, RS, UI}},
+
+{"xoris",      OP(27),         OP_MASK,     PPCCOM,    PPCVLE,         {RA, RS, UI}},
+{"xoriu",      OP(27),         OP_MASK,     PWRCOM,    PPCVLE,         {RA, RS, UI}},
+
+{"andi.",      OP(28),         OP_MASK,     PPCCOM,    PPCVLE,         {RA, RS, UI}},
+{"andil.",     OP(28),         OP_MASK,     PWRCOM,    PPCVLE,         {RA, RS, UI}},
+
+{"andis.",     OP(29),         OP_MASK,     PPCCOM,    PPCVLE,         {RA, RS, UI}},
+{"andiu.",     OP(29),         OP_MASK,     PWRCOM,    PPCVLE,         {RA, RS, UI}},
+
+{"rotldi",     MD(30,0,0),     MDMB_MASK,   PPC64,     PPCVLE,         {RA, RS, SH6}},
+{"clrldi",     MD(30,0,0),     MDSH_MASK,   PPC64,     PPCVLE,         {RA, RS, MB6}},
+{"rldicl",     MD(30,0,0),     MD_MASK,     PPC64,     PPCVLE,         {RA, RS, SH6, MB6}},
+{"rotldi.",    MD(30,0,1),     MDMB_MASK,   PPC64,     PPCVLE,         {RA, RS, SH6}},
+{"clrldi.",    MD(30,0,1),     MDSH_MASK,   PPC64,     PPCVLE,         {RA, RS, MB6}},
+{"rldicl.",    MD(30,0,1),     MD_MASK,     PPC64,     PPCVLE,         {RA, RS, SH6, MB6}},
+
+{"rldicr",     MD(30,1,0),     MD_MASK,     PPC64,     PPCVLE,         {RA, RS, SH6, ME6}},
+{"rldicr.",    MD(30,1,1),     MD_MASK,     PPC64,     PPCVLE,         {RA, RS, SH6, ME6}},
+
+{"rldic",      MD(30,2,0),     MD_MASK,     PPC64,     PPCVLE,         {RA, RS, SH6, MB6}},
+{"rldic.",     MD(30,2,1),     MD_MASK,     PPC64,     PPCVLE,         {RA, RS, SH6, MB6}},
+
+{"rldimi",     MD(30,3,0),     MD_MASK,     PPC64,     PPCVLE,         {RA, RS, SH6, MB6}},
+{"rldimi.",    MD(30,3,1),     MD_MASK,     PPC64,     PPCVLE,         {RA, RS, SH6, MB6}},
+
+{"rotld",      MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCVLE,         {RA, RS, RB}},
+{"rldcl",      MDS(30,8,0),    MDS_MASK,    PPC64,     PPCVLE,         {RA, RS, RB, MB6}},
+{"rotld.",     MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCVLE,         {RA, RS, RB}},
+{"rldcl.",     MDS(30,8,1),    MDS_MASK,    PPC64,     PPCVLE,         {RA, RS, RB, MB6}},
+
+{"rldcr",      MDS(30,9,0),    MDS_MASK,    PPC64,     PPCVLE,         {RA, RS, RB, ME6}},
+{"rldcr.",     MDS(30,9,1),    MDS_MASK,    PPC64,     PPCVLE,         {RA, RS, RB, ME6}},
+
+{"cmpw",       XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    0,              {OBF, RA, RB}},
+{"cmpd",       XOPL(31,0,1),   XCMPL_MASK,  PPC64,     0,              {OBF, RA, RB}},
+{"cmp",                X(31,0),        XCMP_MASK,   PPC,       0,              {BF, L, RA, RB}},
 {"cmp",                X(31,0),        XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
 
-{"twlgt",      XTO(31,4,TOLGT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tlgt",       XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twllt",      XTO(31,4,TOLLT), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tllt",       XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"tweq",       XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"teq",                XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twlge",      XTO(31,4,TOLGE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tlge",       XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twlnl",      XTO(31,4,TOLNL), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tlnl",       XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twlle",      XTO(31,4,TOLLE), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tlle",       XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twlng",      XTO(31,4,TOLNG), XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tlng",       XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twgt",       XTO(31,4,TOGT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tgt",                XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twge",       XTO(31,4,TOGE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tge",                XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twnl",       XTO(31,4,TONL),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tnl",                XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twlt",       XTO(31,4,TOLT),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tlt",                XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twle",       XTO(31,4,TOLE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tle",                XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twng",       XTO(31,4,TONG),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tng",                XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"twne",       XTO(31,4,TONE),  XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tne",                XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"trap",       XTO(31,4,TOU),   0xffffffff, PPCCOM|PPCVLE, PPCNONE,    {0}},
-{"twu",                XTO(31,4,TOU),   XTO_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RA, RB}},
-{"tu",         XTO(31,4,TOU),   XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
-{"tw",         X(31,4),         X_MASK, PPCCOM|PPCVLE, PPCNONE,        {TO, RA, RB}},
-{"t",          X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
-
-{"lvsl",       X(31,6),        X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
-{"lvebx",      X(31,7),        X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
-{"lbfcmx",     APU(31,7,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
-
-{"subfc",      XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"sf",         XO(31,8,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"subc",       XO(31,8,0,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
-{"subfc.",     XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"sf.",                XO(31,8,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"subc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
-
-{"mulhdu",     XO(31,9,0,0),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"mulhdu.",    XO(31,9,0,1),   XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
-
-{"addc",       XO(31,10,0,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"a",          XO(31,10,0,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"addc.",      XO(31,10,0,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"a.",         XO(31,10,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-
-{"mulhwu",     XO(31,11,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
-{"mulhwu.",    XO(31,11,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
-
-{"lxsiwzx",    X(31,12),       XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
-
-{"isellt",     X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
-
-{"tlbilxlpid", XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
-{"tlbilxpid",  XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
-{"tlbilxva",   XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
-{"tlbilx",     X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
-
-{"mfcr",       XFXM(31,19,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE,      {RT, FXM4}},
-{"mfocrf",     XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,      {RT, FXM}},
-
-{"lwarx",      X(31,20),       XEH_MASK,    PPC|PPCVLE, PPCNONE,       {RT, RA0, RB, EH}},
-
-{"ldx",                X(31,21),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
-
-{"icbt",       X(31,22),       X_MASK,      BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA0, RB}},
-
-{"lwzx",       X(31,23),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RA0, RB}},
-{"lx",         X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
-
-{"slw",                XRC(31,24,0),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
-{"sl",         XRC(31,24,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
-{"slw.",       XRC(31,24,1),   X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RA, RS, RB}},
-{"sl.",                XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
-
-{"cntlzw",     XRC(31,26,0),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
-{"cntlz",      XRC(31,26,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
-{"cntlzw.",    XRC(31,26,1),   XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
-{"cntlz.",     XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
-
-{"sld",                XRC(31,27,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
-{"sld.",       XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
-
-{"and",                XRC(31,28,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-{"and.",       XRC(31,28,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-
-{"maskg",      XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
-{"maskg.",     XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
-
-{"ldepx",      X(31,29),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
-
-{"waitasec",   X(31,30),       XRTRARB_MASK,POWER8,    POWER9,         {0}},
-{"wait",       X(31,30),       XWC_MASK,    POWER9,    PPCNONE,        {WC}},
-
-{"lwepx",      X(31,31),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
-
-{"cmplw",      XOPL(31,32,0),  XCMPL_MASK,  PPCCOM|PPCVLE, PPCNONE,    {OBF, RA, RB}},
-{"cmpld",      XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
-{"cmpl",       X(31,32),       XCMP_MASK,   PPC|PPCVLE, PPCNONE,       {BF, L, RA, RB}},
+{"twlgt",      XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tlgt",       XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twllt",      XTO(31,4,TOLLT), XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tllt",       XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"tweq",       XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"teq",                XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twlge",      XTO(31,4,TOLGE), XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tlge",       XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twlnl",      XTO(31,4,TOLNL), XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tlnl",       XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twlle",      XTO(31,4,TOLLE), XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tlle",       XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twlng",      XTO(31,4,TOLNG), XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tlng",       XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twgt",       XTO(31,4,TOGT),  XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tgt",                XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twge",       XTO(31,4,TOGE),  XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tge",                XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twnl",       XTO(31,4,TONL),  XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tnl",                XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twlt",       XTO(31,4,TOLT),  XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tlt",                XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twle",       XTO(31,4,TOLE),  XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tle",                XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twng",       XTO(31,4,TONG),  XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tng",                XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"twne",       XTO(31,4,TONE),  XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tne",                XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"trap",       XTO(31,4,TOU),   0xffffffff, PPCCOM,    0,              {0}},
+{"twu",                XTO(31,4,TOU),   XTO_MASK,   PPCCOM,    0,              {RA, RB}},
+{"tu",         XTO(31,4,TOU),   XTO_MASK,   PWRCOM,    0,              {RA, RB}},
+{"tw",         X(31,4),         X_MASK,     PPCCOM,    0,              {TO, RA, RB}},
+{"t",          X(31,4),         X_MASK,     PWRCOM,    0,              {TO, RA, RB}},
+
+{"lvsl",       X(31,6),        X_MASK,      PPCVEC,    0,              {VD, RA0, RB}},
+{"lvebx",      X(31,7),        X_MASK,      PPCVEC,    0,              {VD, RA0, RB}},
+{"lbfcmx",     APU(31,7,0),    APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
+
+{"subfc",      XO(31,8,0,0),   XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"sf",         XO(31,8,0,0),   XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"subc",       XO(31,8,0,0),   XO_MASK,     PPCCOM,    0,              {RT, RB, RA}},
+{"subfc.",     XO(31,8,0,1),   XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"sf.",                XO(31,8,0,1),   XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"subc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM,    0,              {RT, RB, RA}},
+
+{"mulhdu",     XO(31,9,0,0),   XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+{"mulhdu.",    XO(31,9,0,1),   XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+
+{"addc",       XO(31,10,0,0),  XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"a",          XO(31,10,0,0),  XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"addc.",      XO(31,10,0,1),  XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"a.",         XO(31,10,0,1),  XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+
+{"mulhwu",     XO(31,11,0,0),  XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"mulhwu.",    XO(31,11,0,1),  XO_MASK,     PPC,       0,              {RT, RA, RB}},
+
+{"lxsiwzx",    X(31,12),       XX1_MASK,    PPCVSX2,   0,              {XT6, RA0, RB}},
+
+{"isellt",     X(31,15),       X_MASK,      PPCISEL,   0,              {RT, RA0, RB}},
+
+{"tlbilxlpid", XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, 0,              {0}},
+{"tlbilxpid",  XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, 0,              {0}},
+{"tlbilxva",   XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, 0,              {RA0, RB}},
+{"tlbilx",     X(31,18),       X_MASK,   E500MC|PPCA2, 0,              {T, RA0, RB}},
+
+{"mfcr",       XFXM(31,19,0,0), XFXFXM_MASK, COM,      0,              {RT, FXM4}},
+{"mfocrf",     XFXM(31,19,0,1), XFXFXM_MASK, COM,      0,              {RT, FXM}},
+
+{"lwarx",      X(31,20),       XEH_MASK,    PPC,       0,              {RT, RA0, RB, EH}},
+
+{"ldx",                X(31,21),       X_MASK,      PPC64,     0,              {RT, RA0, RB}},
+
+{"icbt",       X(31,22),  X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0,       {CT, RA0, RB}},
+
+{"lwzx",       X(31,23),       X_MASK,      PPCCOM,    0,              {RT, RA0, RB}},
+{"lx",         X(31,23),       X_MASK,      PWRCOM,    0,              {RT, RA, RB}},
+
+{"slw",                XRC(31,24,0),   X_MASK,      PPCCOM,    0,              {RA, RS, RB}},
+{"sl",         XRC(31,24,0),   X_MASK,      PWRCOM,    0,              {RA, RS, RB}},
+{"slw.",       XRC(31,24,1),   X_MASK,      PPCCOM,    0,              {RA, RS, RB}},
+{"sl.",                XRC(31,24,1),   X_MASK,      PWRCOM,    0,              {RA, RS, RB}},
+
+{"cntlzw",     XRC(31,26,0),   XRB_MASK,    PPCCOM,    0,              {RA, RS}},
+{"cntlz",      XRC(31,26,0),   XRB_MASK,    PWRCOM,    0,              {RA, RS}},
+{"cntlzw.",    XRC(31,26,1),   XRB_MASK,    PPCCOM,    0,              {RA, RS}},
+{"cntlz.",     XRC(31,26,1),   XRB_MASK,    PWRCOM,    0,              {RA, RS}},
+
+{"sld",                XRC(31,27,0),   X_MASK,      PPC64,     0,              {RA, RS, RB}},
+{"sld.",       XRC(31,27,1),   X_MASK,      PPC64,     0,              {RA, RS, RB}},
+
+{"and",                XRC(31,28,0),   X_MASK,      COM,       0,              {RA, RS, RB}},
+{"and.",       XRC(31,28,1),   X_MASK,      COM,       0,              {RA, RS, RB}},
+
+{"maskg",      XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
+{"maskg.",     XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
+
+{"ldepx",      X(31,29),       X_MASK,   E500MC|PPCA2, 0,              {RT, RA0, RB}},
+
+{"waitasec",   X(31,30),      XRTRARB_MASK, POWER8,    POWER9,         {0}},
+{"wait",       X(31,30),       XWC_MASK,    POWER9,    0,              {WC}},
+
+{"lwepx",      X(31,31),       X_MASK,   E500MC|PPCA2, 0,              {RT, RA0, RB}},
+
+{"cmplw",      XOPL(31,32,0),  XCMPL_MASK,  PPCCOM,    0,              {OBF, RA, RB}},
+{"cmpld",      XOPL(31,32,1),  XCMPL_MASK,  PPC64,     0,              {OBF, RA, RB}},
+{"cmpl",       X(31,32),       XCMP_MASK,   PPC,       0,              {BF, L, RA, RB}},
 {"cmpl",       X(31,32),       XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
 
-{"lvsr",       X(31,38),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
-{"lvehx",      X(31,39),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
-{"lhfcmx",     APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"lvsr",       X(31,38),       X_MASK,      PPCVEC,    0,              {VD, RA0, RB}},
+{"lvehx",      X(31,39),       X_MASK,      PPCVEC,    0,              {VD, RA0, RB}},
+{"lhfcmx",     APU(31,39,0),   APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"mviwsplt",   X(31,46),       X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
+{"mviwsplt",   X(31,46),       X_MASK,      PPCVEC2,   0,              {VD, RA, RB}},
 
-{"iselgt",     X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
+{"iselgt",     X(31,47),       X_MASK,      PPCISEL,   0,              {RT, RA0, RB}},
 
-{"lvewx",      X(31,71),       X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
+{"lvewx",      X(31,71),       X_MASK,      PPCVEC,    0,              {VD, RA0, RB}},
 
-{"addg6s",     XO(31,74,0,0),  XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
+{"addg6s",     XO(31,74,0,0),  XO_MASK,     POWER6,    0,              {RT, RA, RB}},
 
-{"lxsiwax",    X(31,76),       XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
+{"lxsiwax",    X(31,76),       XX1_MASK,    PPCVSX2,   0,              {XT6, RA0, RB}},
 
-{"iseleq",     X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA0, RB}},
+{"iseleq",     X(31,79),       X_MASK,      PPCISEL,   0,              {RT, RA0, RB}},
 
-{"isel",       XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}},
+{"isel",       XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0,             {RT, RA0, RB, CRB}},
 
-{"subf",       XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
-{"sub",                XO(31,40,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
-{"subf.",      XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
-{"sub.",       XO(31,40,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RB, RA}},
+{"subf",       XO(31,40,0,0),  XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"sub",                XO(31,40,0,0),  XO_MASK,     PPC,       0,              {RT, RB, RA}},
+{"subf.",      XO(31,40,0,1),  XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"sub.",       XO(31,40,0,1),  XO_MASK,     PPC,       0,              {RT, RB, RA}},
 
-{"mfvsrd",     X(31,51),       XX1RB_MASK,   PPCVSX2,  PPCNONE,        {RA, XS6}},
-{"mffprd",     X(31,51),       XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, FRS}},
-{"mfvrd",      X(31,51)|1,     XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, VS}},
-{"eratilx",    X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
+{"mfvsrd",     X(31,51),       XX1RB_MASK,   PPCVSX2,  0,              {RA, XS6}},
+{"mffprd",     X(31,51),       XX1RB_MASK|1, PPCVSX2,  0,              {RA, FRS}},
+{"mfvrd",      X(31,51)|1,     XX1RB_MASK|1, PPCVSX2,  0,              {RA, VS}},
+{"eratilx",    X(31,51),       X_MASK,      PPCA2,     0,              {ERAT_T, RA, RB}},
 
-{"lbarx",      X(31,52),       XEH_MASK,    POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+{"lbarx",      X(31,52),       XEH_MASK, POWER8|E6500, 0,              {RT, RA0, RB, EH}},
 
-{"ldux",       X(31,53),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
+{"ldux",       X(31,53),       X_MASK,      PPC64,     0,              {RT, RAL, RB}},
 
-{"dcbst",      X(31,54),       XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
+{"dcbst",      X(31,54),       XRT_MASK,    PPC,       0,              {RA0, RB}},
 
-{"lwzux",      X(31,55),       X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RT, RAL, RB}},
-{"lux",                X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"lwzux",      X(31,55),       X_MASK,      PPCCOM,    0,              {RT, RAL, RB}},
+{"lux",                X(31,55),       X_MASK,      PWRCOM,    0,              {RT, RA, RB}},
 
-{"cntlzd",     XRC(31,58,0),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
-{"cntlzd.",    XRC(31,58,1),   XRB_MASK,    PPC64|PPCVLE, PPCNONE,     {RA, RS}},
+{"cntlzd",     XRC(31,58,0),   XRB_MASK,    PPC64,     0,              {RA, RS}},
+{"cntlzd.",    XRC(31,58,1),   XRB_MASK,    PPC64,     0,              {RA, RS}},
 
-{"andc",       XRC(31,60,0),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-{"andc.",      XRC(31,60,1),   X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
+{"andc",       XRC(31,60,0),   X_MASK,      COM,       0,              {RA, RS, RB}},
+{"andc.",      XRC(31,60,1),   X_MASK,      COM,       0,              {RA, RS, RB}},
 
-{"waitrsv",    X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, PPCNONE,    {0}},
-{"waitimpl",   X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, PPCNONE,    {0}},
-{"wait",       X(31,62),       XWC_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
+{"waitrsv",    X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0,          {0}},
+{"waitimpl",   X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0,          {0}},
+{"wait",       X(31,62),       XWC_MASK,    E500MC|PPCA2, 0,           {WC}},
 
-{"dcbstep",    XRT(31,63,0),   XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+{"dcbstep",    XRT(31,63,0),   XRT_MASK,    E500MC|PPCA2, 0,           {RA0, RB}},
 
-{"tdlgt",      XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdllt",      XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdeq",       XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdlge",      XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdlnl",      XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdlle",      XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdlng",      XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdgt",       XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdge",       XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdnl",       XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdlt",       XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdle",       XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdng",       XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdne",       XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"tdu",                XTO(31,68,TOU),   XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
-{"td",         X(31,68),       X_MASK,      PPC64|PPCVLE, PPCNONE,     {TO, RA, RB}},
+{"tdlgt",      XTO(31,68,TOLGT), XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdllt",      XTO(31,68,TOLLT), XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdeq",       XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdlge",      XTO(31,68,TOLGE), XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdlnl",      XTO(31,68,TOLNL), XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdlle",      XTO(31,68,TOLLE), XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdlng",      XTO(31,68,TOLNG), XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdgt",       XTO(31,68,TOGT),  XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdge",       XTO(31,68,TOGE),  XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdnl",       XTO(31,68,TONL),  XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdlt",       XTO(31,68,TOLT),  XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdle",       XTO(31,68,TOLE),  XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdng",       XTO(31,68,TONG),  XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdne",       XTO(31,68,TONE),  XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"tdu",                XTO(31,68,TOU),   XTO_MASK,  PPC64,     0,              {RA, RB}},
+{"td",         X(31,68),       X_MASK,      PPC64,     0,              {TO, RA, RB}},
 
-{"lwfcmx",     APU(31,71,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
-{"mulhd",      XO(31,73,0,0),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"mulhd.",     XO(31,73,0,1),  XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
+{"lwfcmx",     APU(31,71,0),   APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
+{"mulhd",      XO(31,73,0,0),  XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+{"mulhd.",     XO(31,73,0,1),  XO_MASK,     PPC64,     0,              {RT, RA, RB}},
 
-{"mulhw",      XO(31,75,0,0),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
-{"mulhw.",     XO(31,75,0,1),  XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
+{"mulhw",      XO(31,75,0,0),  XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"mulhw.",     XO(31,75,0,1),  XO_MASK,     PPC,       0,              {RT, RA, RB}},
 
-{"dlmzb",      XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
-{"dlmzb.",     XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN|PPCVLE, PPCNONE, {RA, RS, RB}},
+{"dlmzb",      XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0,           {RA, RS, RB}},
+{"dlmzb.",     XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0,           {RA, RS, RB}},
 
-{"mtsrd",      X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
+{"mtsrd",      X(31,82),  XRB_MASK|(1<<20), PPC64,     0,              {SR, RS}},
 
-{"mfmsr",      X(31,83),       XRARB_MASK,  COM|PPCVLE, PPCNONE,       {RT}},
+{"mfmsr",      X(31,83),       XRARB_MASK,  COM,       0,              {RT}},
 
-{"ldarx",      X(31,84),       XEH_MASK,    PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB, EH}},
+{"ldarx",      X(31,84),       XEH_MASK,    PPC64,     0,              {RT, RA0, RB, EH}},
 
 {"dcbfl",      XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA0, RB}},
-{"dcbf",       X(31,86),       XLRT_MASK,   PPC|PPCVLE, PPCNONE,       {RA0, RB, L}},
+{"dcbf",       X(31,86),       XLRT_MASK,   PPC,       0,              {RA0, RB, L}},
 
-{"lbzx",       X(31,87),       X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
+{"lbzx",       X(31,87),       X_MASK,      COM,       0,              {RT, RA0, RB}},
 
-{"lbepx",      X(31,95),       X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+{"lbepx",      X(31,95),       X_MASK,   E500MC|PPCA2, 0,              {RT, RA0, RB}},
 
-{"dni",                XRC(31,97,1),   XRB_MASK,    E6500,     PPCNONE,        {DUI, DCTL}},
+{"dni",                XRC(31,97,1),   XRB_MASK,    E6500,     0,              {DUI, DCTL}},
 
-{"lvx",                X(31,103),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
-{"lqfcmx",     APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"lvx",                X(31,103),      X_MASK,      PPCVEC,    0,              {VD, RA0, RB}},
+{"lqfcmx",     APU(31,103,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"neg",                XO(31,104,0,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
-{"neg.",       XO(31,104,0,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
+{"neg",                XO(31,104,0,0), XORB_MASK,   COM,       0,              {RT, RA}},
+{"neg.",       XO(31,104,0,1), XORB_MASK,   COM,       0,              {RT, RA}},
 
-{"mul",                XO(31,107,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-{"mul.",       XO(31,107,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
+{"mul",                XO(31,107,0,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
+{"mul.",       XO(31,107,0,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
 
-{"mvidsplt",   X(31,110),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA, RB}},
+{"mvidsplt",   X(31,110),      X_MASK,      PPCVEC2,   0,              {VD, RA, RB}},
 
-{"mtsrdin",    X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
+{"mtsrdin",    X(31,114),      XRA_MASK,    PPC64,     0,              {RS, RB}},
 
-{"mffprwz",    X(31,115),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, FRS}},
-{"mfvrwz",     X(31,115)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {RA, VS}},
-{"mfvsrwz",    X(31,115),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {RA, XS6}},
+{"mffprwz",    X(31,115),      XX1RB_MASK|1, PPCVSX2,  0,              {RA, FRS}},
+{"mfvrwz",     X(31,115)|1,    XX1RB_MASK|1, PPCVSX2,  0,              {RA, VS}},
+{"mfvsrwz",    X(31,115),      XX1RB_MASK,   PPCVSX2,  0,              {RA, XS6}},
 
-{"lharx",      X(31,116),      XEH_MASK,    POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
+{"lharx",      X(31,116),      XEH_MASK, POWER8|E6500, 0,              {RT, RA0, RB, EH}},
 
-{"clf",                X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
+{"clf",                X(31,118),      XTO_MASK,    POWER,     0,              {RA, RB}},
 
-{"lbzux",      X(31,119),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
+{"lbzux",      X(31,119),      X_MASK,      COM,       0,              {RT, RAL, RB}},
 
-{"popcntb",    X(31,122),      XRB_MASK,    POWER5|PPCVLE, PPCNONE,    {RA, RS}},
+{"popcntb",    X(31,122),      XRB_MASK,    POWER5,    0,              {RA, RS}},
 
-{"not",                XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
-{"nor",                XRC(31,124,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-{"not.",       XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
-{"nor.",       XRC(31,124,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
+{"not",                XRC(31,124,0),  X_MASK,      COM,       0,              {RA, RS, RBS}},
+{"nor",                XRC(31,124,0),  X_MASK,      COM,       0,              {RA, RS, RB}},
+{"not.",       XRC(31,124,1),  X_MASK,      COM,       0,              {RA, RS, RBS}},
+{"nor.",       XRC(31,124,1),  X_MASK,      COM,       0,              {RA, RS, RB}},
 
-{"dcbfep",     XRT(31,127,0),  XRT_MASK,    E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+{"dcbfep",     XRT(31,127,0),  XRT_MASK, E500MC|PPCA2, 0,              {RA0, RB}},
 
-{"setb",       X(31,128),      XRB_MASK|(3<<16), POWER9, PPCNONE,      {RT, BFA}},
+{"setb",       X(31,128),    XRB_MASK|(3<<16), POWER9, 0,              {RT, BFA}},
 
-{"wrtee",      X(31,131),      XRARB_MASK,  PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
+{"wrtee",      X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0,    {RS}},
 
-{"dcbtstls",   X(31,134),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+{"dcbtstls",   X(31,134),      X_MASK, PPCCHLK|PPC476|TITAN, 0,        {CT, RA0, RB}},
 
-{"stvebx",     X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
-{"stbfcmx",    APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stvebx",     X(31,135),      X_MASK,      PPCVEC,    0,              {VS, RA0, RB}},
+{"stbfcmx",    APU(31,135,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"subfe",      XO(31,136,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"sfe",                XO(31,136,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"subfe.",     XO(31,136,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"sfe.",       XO(31,136,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"subfe",      XO(31,136,0,0), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"sfe",                XO(31,136,0,0), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"subfe.",     XO(31,136,0,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"sfe.",       XO(31,136,0,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"adde",       XO(31,138,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"ae",         XO(31,138,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"adde.",      XO(31,138,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"ae.",                XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"adde",       XO(31,138,0,0), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"ae",         XO(31,138,0,0), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"adde.",      XO(31,138,0,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"ae.",                XO(31,138,0,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"stxsiwx",    X(31,140),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XS6, RA0, RB}},
+{"stxsiwx",    X(31,140),      XX1_MASK,    PPCVSX2,   0,              {XS6, RA0, RB}},
 
-{"msgsndp",    XRTRA(31,142,0,0), XRTRA_MASK, POWER8,  PPCNONE,        {RB}},
-{"dcbtstlse",  X(31,142),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
+{"msgsndp",    XRTRA(31,142,0,0), XRTRA_MASK, POWER8,  0,              {RB}},
+{"dcbtstlse",  X(31,142),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
 
-{"mtcr",       XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},
-{"mtcrf",      XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE,     {FXM, RS}},
-{"mtocrf",     XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,     {FXM, RS}},
+{"mtcr",       XFXM(31,144,0xff,0), XRARB_MASK, COM,   0,              {RS}},
+{"mtcrf",      XFXM(31,144,0,0), XFXFXM_MASK, COM,     0,              {FXM, RS}},
+{"mtocrf",     XFXM(31,144,0,1), XFXFXM_MASK, COM,     0,              {FXM, RS}},
 
-{"mtmsr",      X(31,146),      XRLARB_MASK, COM|PPCVLE, PPCNONE,       {RS, A_L}},
+{"mtmsr",      X(31,146),      XRLARB_MASK, COM,       0,              {RS, A_L}},
 
-{"mtsle",      X(31,147),    XRTLRARB_MASK, POWER8,    PPCNONE,        {L}},
+{"mtsle",      X(31,147),    XRTLRARB_MASK, POWER8,    0,              {L}},
 
-{"eratsx",     XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
-{"eratsx.",    XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
+{"eratsx",     XRC(31,147,0),  X_MASK,      PPCA2,     0,              {RT, RA0, RB}},
+{"eratsx.",    XRC(31,147,1),  X_MASK,      PPCA2,     0,              {RT, RA0, RB}},
 
-{"stdx",       X(31,149),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
+{"stdx",       X(31,149),      X_MASK,      PPC64,     0,              {RS, RA0, RB}},
 
-{"stwcx.",     XRC(31,150,1),  X_MASK,      PPC|PPCVLE, PPCNONE,       {RS, RA0, RB}},
+{"stwcx.",     XRC(31,150,1),  X_MASK,      PPC,       0,              {RS, RA0, RB}},
 
-{"stwx",       X(31,151),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RA0, RB}},
-{"stx",                X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
+{"stwx",       X(31,151),      X_MASK,      PPCCOM,    0,              {RS, RA0, RB}},
+{"stx",                X(31,151),      X_MASK,      PWRCOM,    0,              {RS, RA, RB}},
 
-{"slq",                XRC(31,152,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"slq.",       XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"slq",                XRC(31,152,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"slq.",       XRC(31,152,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"sle",                XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"sle.",       XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"sle",                XRC(31,153,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"sle.",       XRC(31,153,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"prtyw",      X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
+{"prtyw",      X(31,154),    XRB_MASK, POWER6|PPCA2|PPC476, 0,         {RA, RS}},
 
-{"stdepx",     X(31,157),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
+{"stdepx",     X(31,157),      X_MASK,   E500MC|PPCA2, 0,              {RS, RA0, RB}},
 
-{"stwepx",     X(31,159),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
+{"stwepx",     X(31,159),      X_MASK,   E500MC|PPCA2, 0,              {RS, RA0, RB}},
 
-{"wrteei",     X(31,163),      XE_MASK,     PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}},
+{"wrteei",     X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0,       {E}},
 
-{"dcbtls",     X(31,166),      X_MASK,      PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+{"dcbtls",     X(31,166),      X_MASK,  PPCCHLK|PPC476|TITAN, 0,       {CT, RA0, RB}},
 
-{"stvehx",     X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
-{"sthfcmx",    APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stvehx",     X(31,167),      X_MASK,      PPCVEC,    0,              {VS, RA0, RB}},
+{"sthfcmx",    APU(31,167,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"addex",      ZRC(31,170,0),  Z2_MASK,     POWER9,    PPCNONE,        {RT, RA, RB, CY}},
-{"addex.",     ZRC(31,170,1),  Z2_MASK,     POWER9,    PPCNONE,        {RT, RA, RB, CY}},
+{"addex",      ZRC(31,170,0),  Z2_MASK,     POWER9,    0,              {RT, RA, RB, CY}},
+{"addex.",     ZRC(31,170,1),  Z2_MASK,     POWER9,    0,              {RT, RA, RB, CY}},
 
-{"msgclrp",    XRTRA(31,174,0,0), XRTRA_MASK, POWER8,  PPCNONE,        {RB}},
-{"dcbtlse",    X(31,174),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
+{"msgclrp",    XRTRA(31,174,0,0), XRTRA_MASK, POWER8,  0,              {RB}},
+{"dcbtlse",    X(31,174),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA0, RB}},
 
-{"mtmsrd",     X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
+{"mtmsrd",     X(31,178),      XRLARB_MASK, PPC64,     0,              {RS, A_L}},
 
-{"mtvsrd",     X(31,179),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
-{"mtfprd",     X(31,179),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
-{"mtvrd",      X(31,179)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
-{"eratre",     X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
+{"mtvsrd",     X(31,179),      XX1RB_MASK,   PPCVSX2,  0,              {XT6, RA}},
+{"mtfprd",     X(31,179),      XX1RB_MASK|1, PPCVSX2,  0,              {FRT, RA}},
+{"mtvrd",      X(31,179)|1,    XX1RB_MASK|1, PPCVSX2,  0,              {VD, RA}},
+{"eratre",     X(31,179),      X_MASK,      PPCA2,     0,              {RT, RA, WS}},
 
-{"stdux",      X(31,181),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RAS, RB}},
+{"stdux",      X(31,181),      X_MASK,      PPC64,     0,              {RS, RAS, RB}},
 
-{"stqcx.",     XRC(31,182,1),  X_MASK,      POWER8,    PPCNONE,        {RSQ, RA0, RB}},
-{"wchkall",    X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
+{"stqcx.",     XRC(31,182,1),  X_MASK,      POWER8,    0,              {RSQ, RA0, RB}},
+{"wchkall",    X(31,182),      X_MASK,      PPCA2,     0,              {OBF}},
 
-{"stwux",      X(31,183),      X_MASK,      PPCCOM|PPCVLE, PPCNONE,    {RS, RAS, RB}},
-{"stux",       X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
+{"stwux",      X(31,183),      X_MASK,      PPCCOM,    0,              {RS, RAS, RB}},
+{"stux",       X(31,183),      X_MASK,      PWRCOM,    0,              {RS, RA0, RB}},
 
-{"sliq",       XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
-{"sliq.",      XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
+{"sliq",       XRC(31,184,0),  X_MASK,      M601,      0,              {RA, RS, SH}},
+{"sliq.",      XRC(31,184,1),  X_MASK,      M601,      0,              {RA, RS, SH}},
 
-{"prtyd",      X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
+{"prtyd",      X(31,186),      XRB_MASK, POWER6|PPCA2, 0,              {RA, RS}},
 
-{"cmprb",      X(31,192),      XCMP_MASK,   POWER9,    PPCNONE,        {BF, L, RA, RB}},
+{"cmprb",      X(31,192),      XCMP_MASK,   POWER9,    0,              {BF, L, RA, RB}},
 
-{"icblq.",     XRC(31,198,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
+{"icblq.",     XRC(31,198,1),  X_MASK,      E6500,     0,              {CT, RA0, RB}},
 
-{"stvewx",     X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA0, RB}},
-{"stwfcmx",    APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stvewx",     X(31,199),      X_MASK,      PPCVEC,    0,              {VS, RA0, RB}},
+{"stwfcmx",    APU(31,199,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"subfze",     XO(31,200,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"sfze",       XO(31,200,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
-{"subfze.",    XO(31,200,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"sfze.",      XO(31,200,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
+{"subfze",     XO(31,200,0,0), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"sfze",       XO(31,200,0,0), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
+{"subfze.",    XO(31,200,0,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"sfze.",      XO(31,200,0,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
-{"addze",      XO(31,202,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"aze",                XO(31,202,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
-{"addze.",     XO(31,202,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"aze.",       XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
+{"addze",      XO(31,202,0,0), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"aze",                XO(31,202,0,0), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
+{"addze.",     XO(31,202,0,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"aze.",       XO(31,202,0,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
-{"msgsnd",     XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
+{"msgsnd",     XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0,  {RB}},
 
-{"mtsr",       X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
+{"mtsr",       X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
 
-{"mtfprwa",    X(31,211),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
-{"mtvrwa",     X(31,211)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
-{"mtvsrwa",    X(31,211),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
-{"eratwe",     X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
+{"mtfprwa",    X(31,211),      XX1RB_MASK|1, PPCVSX2,  0,              {FRT, RA}},
+{"mtvrwa",     X(31,211)|1,    XX1RB_MASK|1, PPCVSX2,  0,              {VD, RA}},
+{"mtvsrwa",    X(31,211),      XX1RB_MASK,   PPCVSX2,  0,              {XT6, RA}},
+{"eratwe",     X(31,211),      X_MASK,      PPCA2,     0,              {RS, RA, WS}},
 
-{"ldawx.",     XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
+{"ldawx.",     XRC(31,212,1),  X_MASK,      PPCA2,     0,              {RT, RA0, RB}},
 
-{"stdcx.",     XRC(31,214,1),  X_MASK,      PPC64|PPCVLE, PPCNONE,     {RS, RA0, RB}},
+{"stdcx.",     XRC(31,214,1),  X_MASK,      PPC64,     0,              {RS, RA0, RB}},
 
-{"stbx",       X(31,215),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
+{"stbx",       X(31,215),      X_MASK,      COM,       0,              {RS, RA0, RB}},
 
-{"sllq",       XRC(31,216,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"sllq.",      XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"sllq",       XRC(31,216,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"sllq.",      XRC(31,216,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"sleq",       XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"sleq.",      XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"sleq",       XRC(31,217,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"sleq.",      XRC(31,217,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"stbepx",     X(31,223),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
+{"stbepx",     X(31,223),      X_MASK,   E500MC|PPCA2, 0,              {RS, RA0, RB}},
 
-{"cmpeqb",     X(31,224),      XCMPL_MASK,   POWER9,   PPCNONE,        {BF, RA, RB}},
+{"cmpeqb",     X(31,224),      XCMPL_MASK,  POWER9,    0,              {BF, RA, RB}},
 
-{"icblc",      X(31,230),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
+{"icblc",      X(31,230),      X_MASK, PPCCHLK|PPC476|TITAN, 0,        {CT, RA0, RB}},
 
-{"stvx",       X(31,231),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VS, RA0, RB}},
-{"stqfcmx",    APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stvx",       X(31,231),      X_MASK,      PPCVEC,    0,              {VS, RA0, RB}},
+{"stqfcmx",    APU(31,231,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"subfme",     XO(31,232,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"sfme",       XO(31,232,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
-{"subfme.",    XO(31,232,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"sfme.",      XO(31,232,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
+{"subfme",     XO(31,232,0,0), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"sfme",       XO(31,232,0,0), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
+{"subfme.",    XO(31,232,0,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"sfme.",      XO(31,232,0,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
-{"mulld",      XO(31,233,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"mulld.",     XO(31,233,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
+{"mulld",      XO(31,233,0,0), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+{"mulld.",     XO(31,233,0,1), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
 
-{"addme",      XO(31,234,0,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"ame",                XO(31,234,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
-{"addme.",     XO(31,234,0,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"ame.",       XO(31,234,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
+{"addme",      XO(31,234,0,0), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"ame",                XO(31,234,0,0), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
+{"addme.",     XO(31,234,0,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"ame.",       XO(31,234,0,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
-{"mullw",      XO(31,235,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"muls",       XO(31,235,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"mullw.",     XO(31,235,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"muls.",      XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"mullw",      XO(31,235,0,0), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"muls",       XO(31,235,0,0), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"mullw.",     XO(31,235,0,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"muls.",      XO(31,235,0,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"icblce",     X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
-{"msgclr",     XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8|PPCVLE, PPCNONE, {RB}},
-{"mtsrin",     X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
+{"icblce",     X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
+{"msgclr",     XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0,  {RB}},
+{"mtsrin",     X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
 {"mtsri",      X(31,242),      XRA_MASK,    POWER,     NON32,          {RS, RB}},
 
-{"mtfprwz",    X(31,243),      XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {FRT, RA}},
-{"mtvrwz",     X(31,243)|1,    XX1RB_MASK|1, PPCVSX2,  PPCNONE,        {VD, RA}},
-{"mtvsrwz",    X(31,243),      XX1RB_MASK,   PPCVSX2,  PPCNONE,        {XT6, RA}},
+{"mtfprwz",    X(31,243),      XX1RB_MASK|1, PPCVSX2,  0,              {FRT, RA}},
+{"mtvrwz",     X(31,243)|1,    XX1RB_MASK|1, PPCVSX2,  0,              {VD, RA}},
+{"mtvsrwz",    X(31,243),      XX1RB_MASK,   PPCVSX2,  0,              {XT6, RA}},
 
-{"dcbtstt",    XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
-{"dcbtst",     X(31,246),      X_MASK,      POWER4,    DCBT_EO,        {RA0, RB, CT}},
-{"dcbtst",     X(31,246),      X_MASK,      DCBT_EO,   PPCNONE,        {CT, RA0, RB}},
-{"dcbtst",     X(31,246),      X_MASK,      PPC,       POWER4|DCBT_EO, {RA0, RB}},
+{"dcbtstt",    XRT(31,246,0x10), XRT_MASK,  POWER7,    0,              {RA0, RB}},
+{"dcbtst",     X(31,246),      X_MASK,      POWER4,    DCBT_EO,        {RA0, RB, CT}},
+{"dcbtst",     X(31,246),      X_MASK,      DCBT_EO,   0,              {CT, RA0, RB}},
+{"dcbtst",     X(31,246),      X_MASK,      PPC,       POWER4|DCBT_EO, {RA0, RB}},
 
-{"stbux",      X(31,247),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
+{"stbux",      X(31,247),      X_MASK,      COM,       0,              {RS, RAS, RB}},
 
-{"slliq",      XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
-{"slliq.",     XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
+{"slliq",      XRC(31,248,0),  X_MASK,      M601,      0,              {RA, RS, SH}},
+{"slliq.",     XRC(31,248,1),  X_MASK,      M601,      0,              {RA, RS, SH}},
 
-{"bpermd",     X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
+{"bpermd",     X(31,252),      X_MASK,   POWER7|PPCA2, 0,              {RA, RS, RB}},
 
-{"dcbtstep",   XRT(31,255,0),  X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+{"dcbtstep",   XRT(31,255,0),  X_MASK,   E500MC|PPCA2, 0,              {RT, RA0, RB}},
 
-{"mfdcrx",     X(31,259),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}},
-{"mfdcrx.",    XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
+{"mfdcrx",     X(31,259),      X_MASK, BOOKE|PPCA2|PPC476, TITAN,      {RS, RA}},
+{"mfdcrx.",    XRC(31,259,1),  X_MASK,      PPCA2,     0,              {RS, RA}},
 
-{"lvexbx",     X(31,261),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
+{"lvexbx",     X(31,261),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"icbt",       X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
+{"icbt",       X(31,262),      XRT_MASK,    PPC403,    0,              {RA, RB}},
 
-{"lvepxl",     X(31,263),      X_MASK,      PPCVEC2|PPCVLE, PPCNONE,   {VD, RA0, RB}},
+{"lvepxl",     X(31,263),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"ldfcmx",     APU(31,263,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
-{"doz",                XO(31,264,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-{"doz.",       XO(31,264,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
+{"ldfcmx",     APU(31,263,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
+{"doz",                XO(31,264,0,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
+{"doz.",       XO(31,264,0,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
 
-{"modud",      X(31,265),      X_MASK,      POWER9,    PPCNONE,        {RT, RA, RB}},
+{"modud",      X(31,265),      X_MASK,      POWER9,    0,              {RT, RA, RB}},
 
-{"add",                XO(31,266,0,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"cax",                XO(31,266,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"add.",       XO(31,266,0,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"cax.",       XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"add",                XO(31,266,0,0), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"cax",                XO(31,266,0,0), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"add.",       XO(31,266,0,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"cax.",       XO(31,266,0,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"moduw",      X(31,267),      X_MASK,      POWER9,    PPCNONE,        {RT, RA, RB}},
+{"moduw",      X(31,267),      X_MASK,      POWER9,    0,              {RT, RA, RB}},
 
-{"lxvx",       X(31,268),      XX1_MASK|1<<6, PPCVSX3, PPCNONE,        {XT6, RA0, RB}},
-{"lxvl",       X(31,269),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
+{"lxvx",       X(31,268),      XX1_MASK|1<<6, PPCVSX3, 0,              {XT6, RA0, RB}},
+{"lxvl",       X(31,269),      XX1_MASK,    PPCVSX3,   0,              {XT6, RA0, RB}},
 
-{"ehpriv",     X(31,270),      0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}},
+{"ehpriv",     X(31,270),      0xffffffff,  E500MC|PPCA2, 0,           {0}},
 
-{"tlbiel",     X(31,274),      X_MASK|1<<20,POWER9,    PPC476,         {RB, RSO, RIC, PRS, X_R}},
+{"tlbiel",     X(31,274),      X_MASK|1<<20,POWER9,    PPC476,         {RB, RSO, RIC, PRS, X_R}},
 {"tlbiel",     X(31,274),      XRTLRA_MASK, POWER4,    POWER9|PPC476,  {RB, L}},
 
-{"mfapidi",    X(31,275),      X_MASK,      BOOKE,     E500|TITAN,     {RT, RA}},
+{"mfapidi",    X(31,275),      X_MASK,      BOOKE,     E500|TITAN,     {RT, RA}},
 
-{"lqarx",      X(31,276),      XEH_MASK,    POWER8,    PPCNONE,        {RTQ, RAX, RBX, EH}},
+{"lqarx",      X(31,276),      XEH_MASK,    POWER8,    0,              {RTQ, RAX, RBX, EH}},
 
-{"lscbx",      XRC(31,277,0),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
-{"lscbx.",     XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
+{"lscbx",      XRC(31,277,0),  X_MASK,      M601,      0,              {RT, RA, RB}},
+{"lscbx.",     XRC(31,277,1),  X_MASK,      M601,      0,              {RT, RA, RB}},
 
-{"dcbtt",      XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA0, RB}},
-{"dcbt",       X(31,278),      X_MASK,      POWER4,    DCBT_EO,        {RA0, RB, CT}},
-{"dcbt",       X(31,278),      X_MASK,      DCBT_EO,   PPCNONE,        {CT, RA0, RB}},
-{"dcbt",       X(31,278),      X_MASK,      PPC,       POWER4|DCBT_EO, {RA0, RB}},
+{"dcbtt",      XRT(31,278,0x10), XRT_MASK,  POWER7,    0,              {RA0, RB}},
+{"dcbt",       X(31,278),      X_MASK,      POWER4,    DCBT_EO,        {RA0, RB, CT}},
+{"dcbt",       X(31,278),      X_MASK,      DCBT_EO,   0,              {CT, RA0, RB}},
+{"dcbt",       X(31,278),      X_MASK,      PPC,       POWER4|DCBT_EO, {RA0, RB}},
 
-{"lhzx",       X(31,279),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
+{"lhzx",       X(31,279),      X_MASK,      COM,       0,              {RT, RA0, RB}},
 
-{"cdtbcd",     X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
+{"cdtbcd",     X(31,282),      XRB_MASK,    POWER6,    0,              {RA, RS}},
 
-{"eqv",                XRC(31,284,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-{"eqv.",       XRC(31,284,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
+{"eqv",                XRC(31,284,0),  X_MASK,      COM,       0,              {RA, RS, RB}},
+{"eqv.",       XRC(31,284,1),  X_MASK,      COM,       0,              {RA, RS, RB}},
 
-{"lhepx",      X(31,287),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+{"lhepx",      X(31,287),      X_MASK,   E500MC|PPCA2, 0,              {RT, RA0, RB}},
 
-{"mfdcrux",    X(31,291),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RS, RA}},
+{"mfdcrux",    X(31,291),      X_MASK,      PPC464,    0,              {RS, RA}},
 
-{"lvexhx",     X(31,293),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
-{"lvepx",      X(31,295),      X_MASK,      PPCVEC2|PPCVLE, PPCNONE,   {VD, RA0, RB}},
+{"lvexhx",     X(31,293),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
+{"lvepx",      X(31,295),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"lxvll",      X(31,301),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
+{"lxvll",      X(31,301),      XX1_MASK,    PPCVSX3,   0,              {XT6, RA0, RB}},
 
-{"mfbhrbe",    X(31,302),      X_MASK,      POWER8,    PPCNONE,        {RT, BHRBE}},
+{"mfbhrbe",    X(31,302),      X_MASK,      POWER8,    0,              {RT, BHRBE}},
 
-{"tlbie",      X(31,306),      X_MASK|1<<20,POWER9,    TITAN,          {RB, RS, RIC, PRS, X_R}},
-{"tlbie",      X(31,306),      XRA_MASK,    POWER7,    POWER9|TITAN,   {RB, RS}},
-{"tlbie",      X(31,306),      XRTLRA_MASK, PPC,       E500|POWER7|TITAN,      {RB, L}},
-{"tlbi",       X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
+{"tlbie",      X(31,306),      X_MASK|1<<20,POWER9,    TITAN,          {RB, RS, RIC, PRS, X_R}},
+{"tlbie",      X(31,306),      XRA_MASK,    POWER7,    POWER9|TITAN,   {RB, RS}},
+{"tlbie",      X(31,306),      XRTLRA_MASK, PPC,    E500|POWER7|TITAN, {RB, L}},
+{"tlbi",       X(31,306),      XRT_MASK,    POWER,     0,              {RA0, RB}},
 
-{"mfvsrld",    X(31,307),      XX1RB_MASK,  PPCVSX3,   PPCNONE,        {RA, XS6}},
+{"mfvsrld",    X(31,307),      XX1RB_MASK,  PPCVSX3,   0,              {RA, XS6}},
 
-{"ldmx",       X(31,309),      X_MASK,      POWER9,    PPCNONE,        {RT, RA0, RB}},
+{"ldmx",       X(31,309),      X_MASK,      POWER9,    0,              {RT, RA0, RB}},
 
-{"eciwx",      X(31,310),      X_MASK,      PPC,       E500|TITAN,     {RT, RA0, RB}},
+{"eciwx",      X(31,310),      X_MASK,      PPC,       E500|TITAN,     {RT, RA0, RB}},
 
-{"lhzux",      X(31,311),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
+{"lhzux",      X(31,311),      X_MASK,      COM,       0,              {RT, RAL, RB}},
 
-{"cbcdtd",     X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
+{"cbcdtd",     X(31,314),      XRB_MASK,    POWER6,    0,              {RA, RS}},
 
-{"xor",                XRC(31,316,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-{"xor.",       XRC(31,316,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
+{"xor",                XRC(31,316,0),  X_MASK,      COM,       0,              {RA, RS, RB}},
+{"xor.",       XRC(31,316,1),  X_MASK,      COM,       0,              {RA, RS, RB}},
 
-{"dcbtep",     XRT(31,319,0),  X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+{"dcbtep",     XRT(31,319,0),  X_MASK,   E500MC|PPCA2, 0,              {RT, RA0, RB}},
 
-{"mfexisr",    XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfexier",    XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbr0",      XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbr1",      XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbr2",      XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbr3",      XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbr4",      XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbr5",      XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbr6",      XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbr7",      XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbear",     XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfbesr",     XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfiocr",     XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmacr0",   XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmact0",   XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmada0",   XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmasa0",   XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmacc0",   XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmacr1",   XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmact1",   XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmada1",   XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmasa1",   XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmacc1",   XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmacr2",   XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmact2",   XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmada2",   XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmasa2",   XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmacc2",   XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmacr3",   XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmact3",   XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmada3",   XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmasa3",   XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmacc3",   XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdmasr",    XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdcr",      X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {RT, SPR}},
-{"mfdcr.",     XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
+{"mfexisr",    XSPR(31,323, 64), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfexier",    XSPR(31,323, 66), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbr0",      XSPR(31,323,128), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbr1",      XSPR(31,323,129), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbr2",      XSPR(31,323,130), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbr3",      XSPR(31,323,131), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbr4",      XSPR(31,323,132), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbr5",      XSPR(31,323,133), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbr6",      XSPR(31,323,134), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbr7",      XSPR(31,323,135), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbear",     XSPR(31,323,144), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfbesr",     XSPR(31,323,145), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfiocr",     XSPR(31,323,160), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmacr0",   XSPR(31,323,192), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmact0",   XSPR(31,323,193), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmada0",   XSPR(31,323,194), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmasa0",   XSPR(31,323,195), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmacc0",   XSPR(31,323,196), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmacr1",   XSPR(31,323,200), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmact1",   XSPR(31,323,201), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmada1",   XSPR(31,323,202), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmasa1",   XSPR(31,323,203), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmacc1",   XSPR(31,323,204), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmacr2",   XSPR(31,323,208), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmact2",   XSPR(31,323,209), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmada2",   XSPR(31,323,210), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmasa2",   XSPR(31,323,211), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmacc2",   XSPR(31,323,212), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmacr3",   XSPR(31,323,216), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmact3",   XSPR(31,323,217), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmada3",   XSPR(31,323,218), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmasa3",   XSPR(31,323,219), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmacc3",   XSPR(31,323,220), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdmasr",    XSPR(31,323,224), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdcr",      X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
+{"mfdcr.",     XRC(31,323,1),  X_MASK,      PPCA2,     0,              {RT, SPR}},
 
-{"lvexwx",     X(31,325),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
+{"lvexwx",     X(31,325),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"dcread",     X(31,326),      X_MASK,  PPC476|TITAN,  PPCNONE,        {RT, RA0, RB}},
+{"dcread",     X(31,326),      X_MASK,   PPC476|TITAN, 0,              {RT, RA0, RB}},
 
-{"div",                XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-{"div.",       XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
+{"div",                XO(31,331,0,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
+{"div.",       XO(31,331,0,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
 
-{"lxvdsx",     X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
+{"lxvdsx",     X(31,332),      XX1_MASK,    PPCVSX,    0,              {XT6, RA0, RB}},
 
-{"mfpmr",      X(31,334),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}},
-{"mftmr",      X(31,366),      X_MASK, PPCTMR|E6500,   PPCNONE,        {RT, TMR}},
+{"mfpmr",      X(31,334),      X_MASK, PPCPMR|PPCE300, 0,              {RT, PMR}},
+{"mftmr",      X(31,366),      X_MASK, PPCTMR|E6500,   0,              {RT, TMR}},
 
-{"slbsync",    X(31,338),      0xffffffff,  POWER9,    PPCNONE,        {0}},
-
-{"mfmq",       XSPR(31,339,  0), XSPR_MASK, M601,      PPCNONE,        {RT}},
-{"mfxer",      XSPR(31,339,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
-{"mfrtcu",     XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
-{"mfrtcl",     XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
-{"mfdec",      XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
-{"mflr",       XSPR(31,339,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
-{"mfctr",      XSPR(31,339,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RT}},
-{"mfdscr",     XSPR(31,339, 17), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
-{"mftid",      XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
-{"mfdsisr",    XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
-{"mfdar",      XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
+{"slbsync",    X(31,338),      0xffffffff,  POWER9,    0,              {0}},
+
+{"mfmq",       XSPR(31,339,  0), XSPR_MASK, M601,      0,              {RT}},
+{"mfxer",      XSPR(31,339,  1), XSPR_MASK, COM,       0,              {RT}},
+{"mfrtcu",     XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
+{"mfrtcl",     XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
+{"mfdec",      XSPR(31,339,  6), XSPR_MASK, MFDEC1,    0,              {RT}},
+{"mflr",       XSPR(31,339,  8), XSPR_MASK, COM,       0,              {RT}},
+{"mfctr",      XSPR(31,339,  9), XSPR_MASK, COM,       0,              {RT}},
+{"mfdscr",     XSPR(31,339, 17), XSPR_MASK, POWER6,    0,              {RT}},
+{"mftid",      XSPR(31,339, 17), XSPR_MASK, POWER,     0,              {RT}},
+{"mfdsisr",    XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
+{"mfdar",      XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
 {"mfdec",      XSPR(31,339, 22), XSPR_MASK, MFDEC2,    MFDEC1,         {RT}},
-{"mfsdr0",     XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
-{"mfsdr1",     XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
-{"mfsrr0",     XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
-{"mfsrr1",     XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
-{"mfcfar",     XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
-{"mfpid",      XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfcsrr0",    XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfcsrr1",    XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfdear",     XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfesr",      XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivpr",     XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfctrl",     XSPR(31,339,136), XSPR_MASK, POWER4,    PPCNONE,        {RT}},
-{"mfcmpa",     XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcmpb",     XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcmpc",     XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcmpd",     XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mficr",      XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfder",      XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcounta",   XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcountb",   XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcmpe",     XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcmpf",     XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcmpg",     XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfcmph",     XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mflctrl1",   XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mflctrl2",   XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfictrl",    XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfbar",      XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfvrsave",   XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
-{"mfusprg0",   XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfsprg",     XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {RT, SPRG}},
-{"mfsprg4",    XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
-{"mfsprg5",    XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
-{"mfsprg6",    XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
-{"mfsprg7",    XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}},
-{"mftbu",      XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
-{"mftb",       X(31,339),        X_MASK,    POWER4|BOOKE|PPCVLE, PPCNONE, {RT, TBR}},
-{"mftbl",      XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE|PPCVLE, PPCNONE, {RT}},
-{"mfsprg0",    XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
-{"mfsprg1",    XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
-{"mfsprg2",    XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
-{"mfsprg3",    XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
-{"mfasr",      XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
-{"mfear",      XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
-{"mfpir",      XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfpvr",      XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RT}},
-{"mfdbsr",     XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfdbcr0",    XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfdbcr1",    XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfdbcr2",    XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfiac1",     XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfiac2",     XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfiac3",     XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfiac4",     XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfdac1",     XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfdac2",     XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfdvc1",     XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfdvc2",     XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mftsr",      XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mftcr",      XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor0",    XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor1",    XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor2",    XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor3",    XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor4",    XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor5",    XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor6",    XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor7",    XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor8",    XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor9",    XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor10",   XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor11",   XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor12",   XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor13",   XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor14",   XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfivor15",   XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RT}},
-{"mfspefscr",  XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
-{"mfbbear",    XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
-{"mfbbtar",    XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
-{"mfivor32",   XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
-{"mfibatu",    XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
-{"mfivor33",   XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
-{"mfibatl",    XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
-{"mfivor34",   XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
-{"mfivor35",   XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
-{"mfdbatu",    XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
-{"mfdbatl",    XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
-{"mfic_cst",   XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfic_adr",   XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfic_dat",   XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfdc_cst",   XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfdc_adr",   XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfdc_dat",   XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmcsrr0",   XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
-{"mfmcsrr1",   XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
-{"mfmcsr",     XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
-{"mfmcar",     XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
-{"mfdpdr",     XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfdpir",     XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfimmr",     XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmi_ctr",   XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmi_ap",    XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmi_epn",   XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmi_twc",   XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmi_rpn",   XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_ctr",   XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfm_casid",  XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_ap",    XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_epn",   XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_twb",   XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_twc",   XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_rpn",   XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfm_tw",     XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmi_dbram0",        XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmi_dbram1",        XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_dbram0",        XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfmd_dbram1",        XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
-{"mfivndx",    XSPR(31,339,880), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfdvndx",    XSPR(31,339,881), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfivlim",    XSPR(31,339,882), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfdvlim",    XSPR(31,339,883), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfclcsr",    XSPR(31,339,884), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfccr1",     XSPR(31,339,888), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfppr",      XSPR(31,339,896), XSPR_MASK, POWER7,    PPCNONE,        {RT}},
-{"mfppr32",    XSPR(31,339,898), XSPR_MASK, POWER7,    PPCNONE,        {RT}},
-{"mfrstcfg",   XSPR(31,339,923), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfdcdbtrl",  XSPR(31,339,924), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfdcdbtrh",  XSPR(31,339,925), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mficdbtr",   XSPR(31,339,927), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfummcr0",   XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfupmc1",    XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfupmc2",    XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfusia",     XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfummcr1",   XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfupmc3",    XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfupmc4",    XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfzpr",      XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfpid",      XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfmmucr",    XSPR(31,339,946), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
-{"mfccr0",     XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RT}},
-{"mfiac3",     XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
-{"mfiac4",     XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
-{"mfdvc1",     XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
-{"mfdvc2",     XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
-{"mfmmcr0",    XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfpmc1",     XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfsgr",      XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdcwr",     XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfpmc2",     XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfsia",      XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfsler",     XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
-{"mfmmcr1",    XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfsu0r",     XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
-{"mfdbcr1",    XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
-{"mfpmc3",     XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mfpmc4",     XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
-{"mficdbdr",   XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,     {RT}},
-{"mfesr",      XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdear",     XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfevpr",     XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfcdbcr",    XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mftsr",      XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mftcr",      XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfpit",      XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mftbhi",     XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mftblo",     XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfsrr2",     XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfsrr3",     XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
-{"mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
-{"mfdbdr",     XSPR(31,339,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
-{"mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
-{"mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
-{"mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
-{"mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
-{"mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
-{"mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
-{"mfspr",      X(31,339),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, SPR}},
-
-{"lwax",       X(31,341),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RA0, RB}},
-
-{"dst",                XDSS(31,342,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
-
-{"lhax",       X(31,343),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
-
-{"lvxl",       X(31,359),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VD, RA0, RB}},
-
-{"abs",                XO(31,360,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
-{"abs.",       XO(31,360,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
-
-{"divs",       XO(31,363,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-{"divs.",      XO(31,363,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-
-{"lxvwsx",     X(31,364),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
-
-{"tlbia",      X(31,370),      0xffffffff,  PPC,       E500|TITAN,     {0}},
+{"mfsdr0",     XSPR(31,339, 24), XSPR_MASK, POWER,     0,              {RT}},
+{"mfsdr1",     XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
+{"mfsrr0",     XSPR(31,339, 26), XSPR_MASK, COM,       0,              {RT}},
+{"mfsrr1",     XSPR(31,339, 27), XSPR_MASK, COM,       0,              {RT}},
+{"mfcfar",     XSPR(31,339, 28), XSPR_MASK, POWER6,    0,              {RT}},
+{"mfpid",      XSPR(31,339, 48), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfcsrr0",    XSPR(31,339, 58), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfcsrr1",    XSPR(31,339, 59), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfdear",     XSPR(31,339, 61), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfesr",      XSPR(31,339, 62), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivpr",     XSPR(31,339, 63), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfctrl",     XSPR(31,339,136), XSPR_MASK, POWER4,    0,              {RT}},
+{"mfcmpa",     XSPR(31,339,144), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcmpb",     XSPR(31,339,145), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcmpc",     XSPR(31,339,146), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcmpd",     XSPR(31,339,147), XSPR_MASK, PPC860,    0,              {RT}},
+{"mficr",      XSPR(31,339,148), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfder",      XSPR(31,339,149), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcounta",   XSPR(31,339,150), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcountb",   XSPR(31,339,151), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcmpe",     XSPR(31,339,152), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcmpf",     XSPR(31,339,153), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcmpg",     XSPR(31,339,154), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfcmph",     XSPR(31,339,155), XSPR_MASK, PPC860,    0,              {RT}},
+{"mflctrl1",   XSPR(31,339,156), XSPR_MASK, PPC860,    0,              {RT}},
+{"mflctrl2",   XSPR(31,339,157), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfictrl",    XSPR(31,339,158), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfbar",      XSPR(31,339,159), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfvrsave",   XSPR(31,339,256), XSPR_MASK, PPCVEC,    0,              {RT}},
+{"mfusprg0",   XSPR(31,339,256), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfsprg",     XSPR(31,339,256), XSPRG_MASK, PPC,      0,              {RT, SPRG}},
+{"mfsprg4",    XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0,           {RT}},
+{"mfsprg5",    XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0,           {RT}},
+{"mfsprg6",    XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0,           {RT}},
+{"mfsprg7",    XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0,           {RT}},
+{"mftbu",      XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0,           {RT}},
+{"mftb",       X(31,339),        X_MASK,    POWER4|BOOKE, 0,           {RT, TBR}},
+{"mftbl",      XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0,           {RT}},
+{"mfsprg0",    XSPR(31,339,272), XSPR_MASK, PPC,       0,              {RT}},
+{"mfsprg1",    XSPR(31,339,273), XSPR_MASK, PPC,       0,              {RT}},
+{"mfsprg2",    XSPR(31,339,274), XSPR_MASK, PPC,       0,              {RT}},
+{"mfsprg3",    XSPR(31,339,275), XSPR_MASK, PPC,       0,              {RT}},
+{"mfasr",      XSPR(31,339,280), XSPR_MASK, PPC64,     0,              {RT}},
+{"mfear",      XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
+{"mfpir",      XSPR(31,339,286), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfpvr",      XSPR(31,339,287), XSPR_MASK, PPC,       0,              {RT}},
+{"mfdbsr",     XSPR(31,339,304), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfdbcr0",    XSPR(31,339,308), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfdbcr1",    XSPR(31,339,309), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfdbcr2",    XSPR(31,339,310), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfiac1",     XSPR(31,339,312), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfiac2",     XSPR(31,339,313), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfiac3",     XSPR(31,339,314), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfiac4",     XSPR(31,339,315), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfdac1",     XSPR(31,339,316), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfdac2",     XSPR(31,339,317), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfdvc1",     XSPR(31,339,318), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfdvc2",     XSPR(31,339,319), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mftsr",      XSPR(31,339,336), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mftcr",      XSPR(31,339,340), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor0",    XSPR(31,339,400), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor1",    XSPR(31,339,401), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor2",    XSPR(31,339,402), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor3",    XSPR(31,339,403), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor4",    XSPR(31,339,404), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor5",    XSPR(31,339,405), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor6",    XSPR(31,339,406), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor7",    XSPR(31,339,407), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor8",    XSPR(31,339,408), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor9",    XSPR(31,339,409), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor10",   XSPR(31,339,410), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor11",   XSPR(31,339,411), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor12",   XSPR(31,339,412), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor13",   XSPR(31,339,413), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor14",   XSPR(31,339,414), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfivor15",   XSPR(31,339,415), XSPR_MASK, BOOKE,     0,              {RT}},
+{"mfspefscr",  XSPR(31,339,512), XSPR_MASK, PPCSPE,    0,              {RT}},
+{"mfbbear",    XSPR(31,339,513), XSPR_MASK, PPCBRLK,   0,              {RT}},
+{"mfbbtar",    XSPR(31,339,514), XSPR_MASK, PPCBRLK,   0,              {RT}},
+{"mfivor32",   XSPR(31,339,528), XSPR_MASK, PPCSPE,    0,              {RT}},
+{"mfibatu",    XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
+{"mfivor33",   XSPR(31,339,529), XSPR_MASK, PPCSPE,    0,              {RT}},
+{"mfibatl",    XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
+{"mfivor34",   XSPR(31,339,530), XSPR_MASK, PPCSPE,    0,              {RT}},
+{"mfivor35",   XSPR(31,339,531), XSPR_MASK, PPCPMR,    0,              {RT}},
+{"mfdbatu",    XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
+{"mfdbatl",    XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
+{"mfic_cst",   XSPR(31,339,560), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfic_adr",   XSPR(31,339,561), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfic_dat",   XSPR(31,339,562), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfdc_cst",   XSPR(31,339,568), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfdc_adr",   XSPR(31,339,569), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfdc_dat",   XSPR(31,339,570), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmcsrr0",   XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  0,              {RT}},
+{"mfmcsrr1",   XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  0,              {RT}},
+{"mfmcsr",     XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  0,              {RT}},
+{"mfmcar",     XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
+{"mfdpdr",     XSPR(31,339,630), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfdpir",     XSPR(31,339,631), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfimmr",     XSPR(31,339,638), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmi_ctr",   XSPR(31,339,784), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmi_ap",    XSPR(31,339,786), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmi_epn",   XSPR(31,339,787), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmi_twc",   XSPR(31,339,789), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmi_rpn",   XSPR(31,339,790), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_ctr",   XSPR(31,339,792), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfm_casid",  XSPR(31,339,793), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_ap",    XSPR(31,339,794), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_epn",   XSPR(31,339,795), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_twb",   XSPR(31,339,796), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_twc",   XSPR(31,339,797), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_rpn",   XSPR(31,339,798), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfm_tw",     XSPR(31,339,799), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmi_dbram0",        XSPR(31,339,817), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmi_dbram1",        XSPR(31,339,818), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_dbram0",        XSPR(31,339,825), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfmd_dbram1",        XSPR(31,339,826), XSPR_MASK, PPC860,    0,              {RT}},
+{"mfivndx",    XSPR(31,339,880), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfdvndx",    XSPR(31,339,881), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfivlim",    XSPR(31,339,882), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfdvlim",    XSPR(31,339,883), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfclcsr",    XSPR(31,339,884), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfccr1",     XSPR(31,339,888), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfppr",      XSPR(31,339,896), XSPR_MASK, POWER7,    0,              {RT}},
+{"mfppr32",    XSPR(31,339,898), XSPR_MASK, POWER7,    0,              {RT}},
+{"mfrstcfg",   XSPR(31,339,923), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfdcdbtrl",  XSPR(31,339,924), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfdcdbtrh",  XSPR(31,339,925), XSPR_MASK, TITAN,     0,              {RT}},
+{"mficdbtr",   XSPR(31,339,927), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfummcr0",   XSPR(31,339,936), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfupmc1",    XSPR(31,339,937), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfupmc2",    XSPR(31,339,938), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfusia",     XSPR(31,339,939), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfummcr1",   XSPR(31,339,940), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfupmc3",    XSPR(31,339,941), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfupmc4",    XSPR(31,339,942), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfzpr",      XSPR(31,339,944), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfpid",      XSPR(31,339,945), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfmmucr",    XSPR(31,339,946), XSPR_MASK, TITAN,     0,              {RT}},
+{"mfccr0",     XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0,           {RT}},
+{"mfiac3",     XSPR(31,339,948), XSPR_MASK, PPC405,    0,              {RT}},
+{"mfiac4",     XSPR(31,339,949), XSPR_MASK, PPC405,    0,              {RT}},
+{"mfdvc1",     XSPR(31,339,950), XSPR_MASK, PPC405,    0,              {RT}},
+{"mfdvc2",     XSPR(31,339,951), XSPR_MASK, PPC405,    0,              {RT}},
+{"mfmmcr0",    XSPR(31,339,952), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfpmc1",     XSPR(31,339,953), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfsgr",      XSPR(31,339,953), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdcwr",     XSPR(31,339,954), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfpmc2",     XSPR(31,339,954), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfsia",      XSPR(31,339,955), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfsler",     XSPR(31,339,955), XSPR_MASK, PPC405,    0,              {RT}},
+{"mfmmcr1",    XSPR(31,339,956), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfsu0r",     XSPR(31,339,956), XSPR_MASK, PPC405,    0,              {RT}},
+{"mfdbcr1",    XSPR(31,339,957), XSPR_MASK, PPC405,    0,              {RT}},
+{"mfpmc3",     XSPR(31,339,957), XSPR_MASK, PPC750,    0,              {RT}},
+{"mfpmc4",     XSPR(31,339,958), XSPR_MASK, PPC750,    0,              {RT}},
+{"mficdbdr",   XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0,           {RT}},
+{"mfesr",      XSPR(31,339,980), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdear",     XSPR(31,339,981), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfevpr",     XSPR(31,339,982), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfcdbcr",    XSPR(31,339,983), XSPR_MASK, PPC403,    0,              {RT}},
+{"mftsr",      XSPR(31,339,984), XSPR_MASK, PPC403,    0,              {RT}},
+{"mftcr",      XSPR(31,339,986), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfpit",      XSPR(31,339,987), XSPR_MASK, PPC403,    0,              {RT}},
+{"mftbhi",     XSPR(31,339,988), XSPR_MASK, PPC403,    0,              {RT}},
+{"mftblo",     XSPR(31,339,989), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfsrr2",     XSPR(31,339,990), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfsrr3",     XSPR(31,339,991), XSPR_MASK, PPC403,    0,              {RT}},
+{"mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   0,              {RT}},
+{"mfdbdr",     XSPR(31,339,1011), XSPR_MASK, TITAN,    0,              {RS}},
+{"mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   0,              {RT}},
+{"mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   0,              {RT}},
+{"mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   0,              {RT}},
+{"mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   0,              {RT}},
+{"mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   0,              {RT}},
+{"mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   0,              {RT}},
+{"mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   0,              {RT}},
+{"mfspr",      X(31,339),      X_MASK,      COM,       0,              {RT, SPR}},
+
+{"lwax",       X(31,341),      X_MASK,      PPC64,     0,              {RT, RA0, RB}},
+
+{"dst",                XDSS(31,342,0), XDSS_MASK,   PPCVEC,    0,              {RA, RB, STRM}},
+
+{"lhax",       X(31,343),      X_MASK,      COM,       0,              {RT, RA0, RB}},
+
+{"lvxl",       X(31,359),      X_MASK,      PPCVEC,    0,              {VD, RA0, RB}},
+
+{"abs",                XO(31,360,0,0), XORB_MASK,   M601,      0,              {RT, RA}},
+{"abs.",       XO(31,360,0,1), XORB_MASK,   M601,      0,              {RT, RA}},
+
+{"divs",       XO(31,363,0,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
+{"divs.",      XO(31,363,0,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
+
+{"lxvwsx",     X(31,364),      XX1_MASK,    PPCVSX3,   0,              {XT6, RA0, RB}},
+
+{"tlbia",      X(31,370),      0xffffffff,  PPC,       E500|TITAN,     {0}},
 
 {"mftbu",      XSPR(31,371,269), XSPR_MASK, PPC,       NO371|POWER4,   {RT}},
-{"mftb",       X(31,371),      X_MASK,      PPC,       NO371|POWER4,   {RT, TBR}},
+{"mftb",       X(31,371),      X_MASK,      PPC,       NO371|POWER4,   {RT, TBR}},
 {"mftbl",      XSPR(31,371,268), XSPR_MASK, PPC,       NO371|POWER4,   {RT}},
 
-{"lwaux",      X(31,373),      X_MASK,      PPC64|PPCVLE, PPCNONE,     {RT, RAL, RB}},
+{"lwaux",      X(31,373),      X_MASK,      PPC64,     0,              {RT, RAL, RB}},
 
-{"dstst",      XDSS(31,374,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
+{"dstst",      XDSS(31,374,0), XDSS_MASK,   PPCVEC,    0,              {RA, RB, STRM}},
 
-{"lhaux",      X(31,375),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RAL, RB}},
+{"lhaux",      X(31,375),      X_MASK,      COM,       0,              {RT, RAL, RB}},
 
-{"popcntw",    X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
+{"popcntw",    X(31,378),      XRB_MASK,    POWER7|PPCA2, 0,           {RA, RS}},
 
-{"mtdcrx",     X(31,387),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RA, RS}},
-{"mtdcrx.",    XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
+{"mtdcrx",     X(31,387),      X_MASK,      BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
+{"mtdcrx.",    XRC(31,387,1),  X_MASK,      PPCA2,     0,              {RA, RS}},
 
-{"stvexbx",    X(31,389),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
+{"stvexbx",    X(31,389),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
 
-{"dcblc",      X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
-{"stdfcmx",    APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"dcblc",      X(31,390),      X_MASK,  PPCCHLK|PPC476|TITAN, 0,       {CT, RA0, RB}},
+{"stdfcmx",    APU(31,391,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"divdeu",     XO(31,393,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divdeu.",    XO(31,393,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divweu",     XO(31,395,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divweu.",    XO(31,395,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divdeu",     XO(31,393,0,0), XO_MASK,     POWER7|PPCA2, 0,           {RT, RA, RB}},
+{"divdeu.",    XO(31,393,0,1), XO_MASK,     POWER7|PPCA2, 0,           {RT, RA, RB}},
+{"divweu",     XO(31,395,0,0), XO_MASK,     POWER7|PPCA2, 0,           {RT, RA, RB}},
+{"divweu.",    XO(31,395,0,1), XO_MASK,     POWER7|PPCA2, 0,           {RT, RA, RB}},
 
-{"stxvx",      X(31,396),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
-{"stxvl",      X(31,397),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
+{"stxvx",      X(31,396),      XX1_MASK,    PPCVSX3,   0,              {XS6, RA0, RB}},
+{"stxvl",      X(31,397),      XX1_MASK,    PPCVSX3,   0,              {XS6, RA0, RB}},
 
-{"dcblce",     X(31,398),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
+{"dcblce",     X(31,398),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
 
-{"slbmte",     X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
+{"slbmte",     X(31,402),      XRA_MASK,    PPC64,     0,              {RS, RB}},
 
-{"mtvsrws",    X(31,403),      XX1RB_MASK,  PPCVSX3,   PPCNONE,        {XT6, RA}},
+{"mtvsrws",    X(31,403),      XX1RB_MASK,  PPCVSX3,   0,              {XT6, RA}},
 
-{"pbt.",       XRC(31,404,1),  X_MASK,      POWER8,    PPCNONE,        {RS, RA0, RB}},
+{"pbt.",       XRC(31,404,1),  X_MASK,      POWER8,    0,              {RS, RA0, RB}},
 
-{"icswx",      XRC(31,406,0),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
-{"icswx.",     XRC(31,406,1),  X_MASK,   POWER7|PPCA2, PPCNONE,        {RS, RA, RB}},
+{"icswx",      XRC(31,406,0),  X_MASK,   POWER7|PPCA2, 0,              {RS, RA, RB}},
+{"icswx.",     XRC(31,406,1),  X_MASK,   POWER7|PPCA2, 0,              {RS, RA, RB}},
 
-{"sthx",       X(31,407),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RA0, RB}},
+{"sthx",       X(31,407),      X_MASK,      COM,       0,              {RS, RA0, RB}},
 
-{"orc",                XRC(31,412,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-{"orc.",       XRC(31,412,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
+{"orc",                XRC(31,412,0),  X_MASK,      COM,       0,              {RA, RS, RB}},
+{"orc.",       XRC(31,412,1),  X_MASK,      COM,       0,              {RA, RS, RB}},
 
-{"sthepx",     X(31,415),      X_MASK,      E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}},
+{"sthepx",     X(31,415),      X_MASK,   E500MC|PPCA2, 0,              {RS, RA0, RB}},
 
-{"mtdcrux",    X(31,419),      X_MASK,      PPC464|PPCVLE, PPCNONE,    {RA, RS}},
+{"mtdcrux",    X(31,419),      X_MASK,      PPC464,    0,              {RA, RS}},
 
-{"stvexhx",    X(31,421),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
+{"stvexhx",    X(31,421),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
 
-{"dcblq.",     XRC(31,422,1),  X_MASK,      E6500,     PPCNONE,        {CT, RA0, RB}},
+{"dcblq.",     XRC(31,422,1),  X_MASK,      E6500,     0,              {CT, RA0, RB}},
 
-{"divde",      XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divde.",     XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divwe",      XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divwe.",     XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divde",      XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divde.",     XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divwe",      XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divwe.",     XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
 
-{"stxvll",     X(31,429),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
+{"stxvll",     X(31,429),      XX1_MASK,    PPCVSX3,   0,              {XS6, RA0, RB}},
 
-{"clrbhrb",    X(31,430),      0xffffffff,  POWER8,    PPCNONE,        {0}},
+{"clrbhrb",    X(31,430),      0xffffffff,  POWER8,    0,              {0}},
 
-{"slbie",      X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
+{"slbie",      X(31,434),      XRTRA_MASK,  PPC64,     0,              {RB}},
 
-{"mtvsrdd",    X(31,435),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
+{"mtvsrdd",    X(31,435),      XX1_MASK,    PPCVSX3,   0,              {XT6, RA0, RB}},
 
-{"lwzmx",      X(31,437),      X_MASK,      POWER9,    PPCNONE,        {RT, RA0, RB}},
+{"lwzmx",      X(31,437),      X_MASK,      POWER9,    0,              {RT, RA0, RB}},
 
-{"ecowx",      X(31,438),      X_MASK,      PPC,       E500|TITAN,     {RT, RA0, RB}},
+{"ecowx",      X(31,438),      X_MASK,      PPC,       E500|TITAN,     {RT, RA0, RB}},
 
-{"sthux",      X(31,439),      X_MASK,      COM|PPCVLE, PPCNONE,       {RS, RAS, RB}},
+{"sthux",      X(31,439),      X_MASK,      COM,       0,              {RS, RAS, RB}},
 
-{"mdors",      0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
+{"mdors",      0x7f9ce378,     0xffffffff,  E500MC,    0,              {0}},
 
-{"miso",       0x7f5ad378,     0xffffffff,  E6500,     PPCNONE,        {0}},
+{"miso",       0x7f5ad378,     0xffffffff,  E6500,     0,              {0}},
 
 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
-   "or rX,rX,rX", with rX being r27, r29 and r30 respectively.  */
-{"yield",      0x7f7bdb78,     0xffffffff,  POWER7,     PPCNONE,       {0}},
-{"mdoio",      0x7fbdeb78,     0xffffffff,  POWER7,     PPCNONE,       {0}},
-{"mdoom",      0x7fdef378,     0xffffffff,  POWER7,     PPCNONE,       {0}},
-{"mr",         XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
-{"or",         XRC(31,444,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-{"mr.",                XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RBS}},
-{"or.",                XRC(31,444,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-
-{"mtexisr",    XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtexier",    XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbr0",      XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbr1",      XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbr2",      XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbr3",      XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbr4",      XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbr5",      XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbr6",      XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbr7",      XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbear",     XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtbesr",     XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtiocr",     XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmacr0",   XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmact0",   XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmada0",   XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmasa0",   XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmacc0",   XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmacr1",   XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmact1",   XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmada1",   XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmasa1",   XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmacc1",   XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmacr2",   XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmact2",   XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmada2",   XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmasa2",   XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmacc2",   XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmacr3",   XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmact3",   XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmada3",   XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmasa3",   XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmacc3",   XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdmasr",    XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdcr",      X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, E500|TITAN, {SPR, RS}},
-{"mtdcr.",     XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
-
-{"stvexwx",    X(31,453),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
-
-{"dccci",      X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
-{"dci",                X(31,454),      XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
-
-{"divdu",      XO(31,457,0,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"divdu.",     XO(31,457,0,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
-
-{"divwu",      XO(31,459,0,0), XO_MASK,  PPC|PPCVLE,   PPCNONE,        {RT, RA, RB}},
-{"divwu.",     XO(31,459,0,1), XO_MASK,  PPC|PPCVLE,   PPCNONE,        {RT, RA, RB}},
-
-{"mtpmr",      X(31,462),      X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}},
-{"mttmr",      X(31,494),      X_MASK, PPCTMR|E6500,   PPCNONE,        {TMR, RS}},
-
-{"slbieg",     X(31,466),      XRA_MASK,    POWER9,    PPCNONE,        {RS, RB}},
-
-{"mtmq",       XSPR(31,467,  0), XSPR_MASK, M601,      PPCNONE,        {RS}},
-{"mtxer",      XSPR(31,467,  1), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
-{"mtlr",       XSPR(31,467,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
-{"mtctr",      XSPR(31,467,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
-{"mtdscr",     XSPR(31,467, 17), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
-{"mttid",      XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
-{"mtdsisr",    XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
-{"mtdar",      XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
-{"mtrtcu",     XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
-{"mtrtcl",     XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
-{"mtdec",      XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
-{"mtsdr0",     XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
-{"mtsdr1",     XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
-{"mtsrr0",     XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
-{"mtsrr1",     XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE,       {RS}},
-{"mtcfar",     XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
-{"mtpid",      XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdecar",    XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtcsrr0",    XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtcsrr1",    XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdear",     XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtesr",      XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivpr",     XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtcmpa",     XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtcmpb",     XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtcmpc",     XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtcmpd",     XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mticr",      XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtder",      XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtcounta",   XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtcountb",   XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtctrl",     XSPR(31,467,152), XSPR_MASK, POWER4,    PPCNONE,        {RS}},
-{"mtcmpe",     XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtcmpf",     XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtcmpg",     XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtcmph",     XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtlctrl1",   XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtlctrl2",   XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtictrl",    XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtbar",      XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
-{"mtvrsave",   XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
-{"mtusprg0",   XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtsprg",     XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE,      {SPRG, RS}},
-{"mtsprg0",    XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
-{"mtsprg1",    XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
-{"mtsprg2",    XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
-{"mtsprg3",    XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE,       {RS}},
-{"mtsprg4",    XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
-{"mtsprg5",    XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
-{"mtsprg6",    XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
-{"mtsprg7",    XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}},
-{"mtasr",      XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
-{"mtear",      XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
-{"mttbl",      XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
-{"mttbu",      XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
-{"mtdbsr",     XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdbcr0",    XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdbcr1",    XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdbcr2",    XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtiac1",     XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtiac2",     XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtiac3",     XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtiac4",     XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdac1",     XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdac2",     XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdvc1",     XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtdvc2",     XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mttsr",      XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mttcr",      XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor0",    XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor1",    XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor2",    XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor3",    XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor4",    XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor5",    XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor6",    XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor7",    XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor8",    XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor9",    XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor10",   XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor11",   XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor12",   XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor13",   XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor14",   XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtivor15",   XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,     {RS}},
-{"mtspefscr",  XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
-{"mtbbear",    XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
-{"mtbbtar",    XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
-{"mtivor32",   XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
-{"mtibatu",    XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
-{"mtivor33",   XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
-{"mtibatl",    XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
-{"mtivor34",   XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
-{"mtivor35",   XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
-{"mtdbatu",    XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
-{"mtdbatl",    XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
-{"mtmcsrr0",   XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
-{"mtmcsrr1",   XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE,  {RS}},
-{"mtmcsr",     XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
-{"mtivndx",    XSPR(31,467,880), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
-{"mtdvndx",    XSPR(31,467,881), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
-{"mtivlim",    XSPR(31,467,882), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
-{"mtdvlim",    XSPR(31,467,883), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
-{"mtclcsr",    XSPR(31,467,884), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
-{"mtccr1",     XSPR(31,467,888), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
-{"mtppr",      XSPR(31,467,896), XSPR_MASK, POWER7,    PPCNONE,        {RS}},
-{"mtppr32",    XSPR(31,467,898), XSPR_MASK, POWER7,    PPCNONE,        {RS}},
-{"mtummcr0",   XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtupmc1",    XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtupmc2",    XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtusia",     XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtummcr1",   XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtupmc3",    XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtupmc4",    XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtzpr",      XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtpid",      XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtrmmucr",   XSPR(31,467,946), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
-{"mtccr0",     XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RS}},
-{"mtiac3",     XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
-{"mtiac4",     XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
-{"mtdvc1",     XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
-{"mtdvc2",     XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
-{"mtmmcr0",    XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtpmc1",     XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtsgr",      XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdcwr",     XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtpmc2",     XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtsia",      XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtsler",     XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
-{"mtmmcr1",    XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtsu0r",     XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
-{"mtdbcr1",    XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
-{"mtpmc3",     XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mtpmc4",     XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
-{"mticdbdr",   XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtesr",      XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdear",     XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtevpr",     XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtcdbcr",    XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mttsr",      XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mttcr",      XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtpit",      XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mttbhi",     XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mttblo",     XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtsrr2",     XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtsrr3",     XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
-{"mtdbsr",     XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtdbdr",     XSPR(31,467,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
-{"mtdbcr0",    XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
-{"mtiac1",     XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtiac2",     XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtdac1",     XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtdac2",     XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtl2cr",     XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
-{"mtdccr",     XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mticcr",     XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtictc",     XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
-{"mtpbl1",     XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtthrm1",    XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
-{"mtpbu1",     XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtthrm2",    XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
-{"mtpbl2",     XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtthrm3",    XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
-{"mtpbu2",     XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
-{"mtspr",      X(31,467),      X_MASK,      COM|PPCVLE, PPCNONE,       {SPR, RS}},
-
-{"dcbi",       X(31,470),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
-
-{"nand",       XRC(31,476,0),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-{"nand.",      XRC(31,476,1),  X_MASK,      COM|PPCVLE, PPCNONE,       {RA, RS, RB}},
-
-{"dsn",        X(31,483),      XRT_MASK,    E500MC|PPCVLE, PPCNONE,    {RA, RB}},
-
-{"dcread",     X(31,486),      X_MASK,  PPC403|PPC440|PPCVLE, PPCA2|PPC476, {RT, RA0, RB}},
-
-{"icbtls",     X(31,486),      X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}},
-
-{"stvxl",      X(31,487),      X_MASK,      PPCVEC|PPCVLE, PPCNONE,    {VS, RA0, RB}},
-
-{"nabs",       XO(31,488,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
-{"nabs.",      XO(31,488,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
-
-{"divd",       XO(31,489,0,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"divd.",      XO(31,489,0,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
-
-{"divw",       XO(31,491,0,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
-{"divw.",      XO(31,491,0,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
-
-{"icbtlse",    X(31,494),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
-
-{"slbia",      X(31,498),      0xff1fffff,  POWER6,    PPCNONE,        {IH}},
+   "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
+{"yield",      0x7f7bdb78,     0xffffffff,  POWER7,    0,              {0}},
+{"mdoio",      0x7fbdeb78,     0xffffffff,  POWER7,    0,              {0}},
+{"mdoom",      0x7fdef378,     0xffffffff,  POWER7,    0,              {0}},
+{"mr",         XRC(31,444,0),  X_MASK,      COM,       0,              {RA, RS, RBS}},
+{"or",         XRC(31,444,0),  X_MASK,      COM,       0,              {RA, RS, RB}},
+{"mr.",                XRC(31,444,1),  X_MASK,      COM,       0,              {RA, RS, RBS}},
+{"or.",                XRC(31,444,1),  X_MASK,      COM,       0,              {RA, RS, RB}},
+
+{"mtexisr",    XSPR(31,451, 64), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtexier",    XSPR(31,451, 66), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbr0",      XSPR(31,451,128), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbr1",      XSPR(31,451,129), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbr2",      XSPR(31,451,130), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbr3",      XSPR(31,451,131), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbr4",      XSPR(31,451,132), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbr5",      XSPR(31,451,133), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbr6",      XSPR(31,451,134), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbr7",      XSPR(31,451,135), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbear",     XSPR(31,451,144), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtbesr",     XSPR(31,451,145), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtiocr",     XSPR(31,451,160), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmacr0",   XSPR(31,451,192), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmact0",   XSPR(31,451,193), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmada0",   XSPR(31,451,194), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmasa0",   XSPR(31,451,195), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmacc0",   XSPR(31,451,196), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmacr1",   XSPR(31,451,200), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmact1",   XSPR(31,451,201), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmada1",   XSPR(31,451,202), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmasa1",   XSPR(31,451,203), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmacc1",   XSPR(31,451,204), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmacr2",   XSPR(31,451,208), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmact2",   XSPR(31,451,209), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmada2",   XSPR(31,451,210), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmasa2",   XSPR(31,451,211), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmacc2",   XSPR(31,451,212), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmacr3",   XSPR(31,451,216), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmact3",   XSPR(31,451,217), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmada3",   XSPR(31,451,218), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmasa3",   XSPR(31,451,219), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmacc3",   XSPR(31,451,220), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdmasr",    XSPR(31,451,224), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdcr",      X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
+{"mtdcr.",     XRC(31,451,1), X_MASK,       PPCA2,     0,              {SPR, RS}},
+
+{"stvexwx",    X(31,453),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
+
+{"dccci",      X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0,      {RAOPT, RBOPT}},
+{"dci",                X(31,454),      XRARB_MASK, PPCA2|PPC476, 0,            {CT}},
+
+{"divdu",      XO(31,457,0,0), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+{"divdu.",     XO(31,457,0,1), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+
+{"divwu",      XO(31,459,0,0), XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"divwu.",     XO(31,459,0,1), XO_MASK,     PPC,       0,              {RT, RA, RB}},
+
+{"mtpmr",      X(31,462),      X_MASK, PPCPMR|PPCE300, 0,              {PMR, RS}},
+{"mttmr",      X(31,494),      X_MASK, PPCTMR|E6500,   0,              {TMR, RS}},
+
+{"slbieg",     X(31,466),      XRA_MASK,    POWER9,    0,              {RS, RB}},
+
+{"mtmq",       XSPR(31,467,  0), XSPR_MASK, M601,      0,              {RS}},
+{"mtxer",      XSPR(31,467,  1), XSPR_MASK, COM,       0,              {RS}},
+{"mtlr",       XSPR(31,467,  8), XSPR_MASK, COM,       0,              {RS}},
+{"mtctr",      XSPR(31,467,  9), XSPR_MASK, COM,       0,              {RS}},
+{"mtdscr",     XSPR(31,467, 17), XSPR_MASK, POWER6,    0,              {RS}},
+{"mttid",      XSPR(31,467, 17), XSPR_MASK, POWER,     0,              {RS}},
+{"mtdsisr",    XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
+{"mtdar",      XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
+{"mtrtcu",     XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
+{"mtrtcl",     XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
+{"mtdec",      XSPR(31,467, 22), XSPR_MASK, COM,       0,              {RS}},
+{"mtsdr0",     XSPR(31,467, 24), XSPR_MASK, POWER,     0,              {RS}},
+{"mtsdr1",     XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
+{"mtsrr0",     XSPR(31,467, 26), XSPR_MASK, COM,       0,              {RS}},
+{"mtsrr1",     XSPR(31,467, 27), XSPR_MASK, COM,       0,              {RS}},
+{"mtcfar",     XSPR(31,467, 28), XSPR_MASK, POWER6,    0,              {RS}},
+{"mtpid",      XSPR(31,467, 48), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdecar",    XSPR(31,467, 54), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtcsrr0",    XSPR(31,467, 58), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtcsrr1",    XSPR(31,467, 59), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdear",     XSPR(31,467, 61), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtesr",      XSPR(31,467, 62), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivpr",     XSPR(31,467, 63), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtcmpa",     XSPR(31,467,144), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtcmpb",     XSPR(31,467,145), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtcmpc",     XSPR(31,467,146), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtcmpd",     XSPR(31,467,147), XSPR_MASK, PPC860,    0,              {RS}},
+{"mticr",      XSPR(31,467,148), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtder",      XSPR(31,467,149), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtcounta",   XSPR(31,467,150), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtcountb",   XSPR(31,467,151), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtctrl",     XSPR(31,467,152), XSPR_MASK, POWER4,    0,              {RS}},
+{"mtcmpe",     XSPR(31,467,152), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtcmpf",     XSPR(31,467,153), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtcmpg",     XSPR(31,467,154), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtcmph",     XSPR(31,467,155), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtlctrl1",   XSPR(31,467,156), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtlctrl2",   XSPR(31,467,157), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtictrl",    XSPR(31,467,158), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtbar",      XSPR(31,467,159), XSPR_MASK, PPC860,    0,              {RS}},
+{"mtvrsave",   XSPR(31,467,256), XSPR_MASK, PPCVEC,    0,              {RS}},
+{"mtusprg0",   XSPR(31,467,256), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtsprg",     XSPR(31,467,256), XSPRG_MASK, PPC,      0,              {SPRG, RS}},
+{"mtsprg0",    XSPR(31,467,272), XSPR_MASK, PPC,       0,              {RS}},
+{"mtsprg1",    XSPR(31,467,273), XSPR_MASK, PPC,       0,              {RS}},
+{"mtsprg2",    XSPR(31,467,274), XSPR_MASK, PPC,       0,              {RS}},
+{"mtsprg3",    XSPR(31,467,275), XSPR_MASK, PPC,       0,              {RS}},
+{"mtsprg4",    XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0,           {RS}},
+{"mtsprg5",    XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0,           {RS}},
+{"mtsprg6",    XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0,           {RS}},
+{"mtsprg7",    XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0,           {RS}},
+{"mtasr",      XSPR(31,467,280), XSPR_MASK, PPC64,     0,              {RS}},
+{"mtear",      XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
+{"mttbl",      XSPR(31,467,284), XSPR_MASK, PPC,       0,              {RS}},
+{"mttbu",      XSPR(31,467,285), XSPR_MASK, PPC,       0,              {RS}},
+{"mtdbsr",     XSPR(31,467,304), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdbcr0",    XSPR(31,467,308), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdbcr1",    XSPR(31,467,309), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdbcr2",    XSPR(31,467,310), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtiac1",     XSPR(31,467,312), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtiac2",     XSPR(31,467,313), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtiac3",     XSPR(31,467,314), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtiac4",     XSPR(31,467,315), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdac1",     XSPR(31,467,316), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdac2",     XSPR(31,467,317), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdvc1",     XSPR(31,467,318), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtdvc2",     XSPR(31,467,319), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mttsr",      XSPR(31,467,336), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mttcr",      XSPR(31,467,340), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor0",    XSPR(31,467,400), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor1",    XSPR(31,467,401), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor2",    XSPR(31,467,402), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor3",    XSPR(31,467,403), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor4",    XSPR(31,467,404), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor5",    XSPR(31,467,405), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor6",    XSPR(31,467,406), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor7",    XSPR(31,467,407), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor8",    XSPR(31,467,408), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor9",    XSPR(31,467,409), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor10",   XSPR(31,467,410), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor11",   XSPR(31,467,411), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor12",   XSPR(31,467,412), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor13",   XSPR(31,467,413), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor14",   XSPR(31,467,414), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtivor15",   XSPR(31,467,415), XSPR_MASK, BOOKE,     0,              {RS}},
+{"mtspefscr",  XSPR(31,467,512), XSPR_MASK, PPCSPE,    0,              {RS}},
+{"mtbbear",    XSPR(31,467,513), XSPR_MASK, PPCBRLK,   0,              {RS}},
+{"mtbbtar",    XSPR(31,467,514), XSPR_MASK, PPCBRLK,   0,              {RS}},
+{"mtivor32",   XSPR(31,467,528), XSPR_MASK, PPCSPE,    0,              {RS}},
+{"mtibatu",    XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
+{"mtivor33",   XSPR(31,467,529), XSPR_MASK, PPCSPE,    0,              {RS}},
+{"mtibatl",    XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
+{"mtivor34",   XSPR(31,467,530), XSPR_MASK, PPCSPE,    0,              {RS}},
+{"mtivor35",   XSPR(31,467,531), XSPR_MASK, PPCPMR,    0,              {RS}},
+{"mtdbatu",    XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
+{"mtdbatl",    XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
+{"mtmcsrr0",   XSPR(31,467,570), XSPR_MASK, PPCRFMCI,  0,              {RS}},
+{"mtmcsrr1",   XSPR(31,467,571), XSPR_MASK, PPCRFMCI,  0,              {RS}},
+{"mtmcsr",     XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  0,              {RS}},
+{"mtivndx",    XSPR(31,467,880), XSPR_MASK, TITAN,     0,              {RS}},
+{"mtdvndx",    XSPR(31,467,881), XSPR_MASK, TITAN,     0,              {RS}},
+{"mtivlim",    XSPR(31,467,882), XSPR_MASK, TITAN,     0,              {RS}},
+{"mtdvlim",    XSPR(31,467,883), XSPR_MASK, TITAN,     0,              {RS}},
+{"mtclcsr",    XSPR(31,467,884), XSPR_MASK, TITAN,     0,              {RS}},
+{"mtccr1",     XSPR(31,467,888), XSPR_MASK, TITAN,     0,              {RS}},
+{"mtppr",      XSPR(31,467,896), XSPR_MASK, POWER7,    0,              {RS}},
+{"mtppr32",    XSPR(31,467,898), XSPR_MASK, POWER7,    0,              {RS}},
+{"mtummcr0",   XSPR(31,467,936), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtupmc1",    XSPR(31,467,937), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtupmc2",    XSPR(31,467,938), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtusia",     XSPR(31,467,939), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtummcr1",   XSPR(31,467,940), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtupmc3",    XSPR(31,467,941), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtupmc4",    XSPR(31,467,942), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtzpr",      XSPR(31,467,944), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtpid",      XSPR(31,467,945), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtrmmucr",   XSPR(31,467,946), XSPR_MASK, TITAN,     0,              {RS}},
+{"mtccr0",     XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0,           {RS}},
+{"mtiac3",     XSPR(31,467,948), XSPR_MASK, PPC405,    0,              {RS}},
+{"mtiac4",     XSPR(31,467,949), XSPR_MASK, PPC405,    0,              {RS}},
+{"mtdvc1",     XSPR(31,467,950), XSPR_MASK, PPC405,    0,              {RS}},
+{"mtdvc2",     XSPR(31,467,951), XSPR_MASK, PPC405,    0,              {RS}},
+{"mtmmcr0",    XSPR(31,467,952), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtpmc1",     XSPR(31,467,953), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtsgr",      XSPR(31,467,953), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdcwr",     XSPR(31,467,954), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtpmc2",     XSPR(31,467,954), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtsia",      XSPR(31,467,955), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtsler",     XSPR(31,467,955), XSPR_MASK, PPC405,    0,              {RS}},
+{"mtmmcr1",    XSPR(31,467,956), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtsu0r",     XSPR(31,467,956), XSPR_MASK, PPC405,    0,              {RS}},
+{"mtdbcr1",    XSPR(31,467,957), XSPR_MASK, PPC405,    0,              {RS}},
+{"mtpmc3",     XSPR(31,467,957), XSPR_MASK, PPC750,    0,              {RS}},
+{"mtpmc4",     XSPR(31,467,958), XSPR_MASK, PPC750,    0,              {RS}},
+{"mticdbdr",   XSPR(31,467,979), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtesr",      XSPR(31,467,980), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdear",     XSPR(31,467,981), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtevpr",     XSPR(31,467,982), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtcdbcr",    XSPR(31,467,983), XSPR_MASK, PPC403,    0,              {RS}},
+{"mttsr",      XSPR(31,467,984), XSPR_MASK, PPC403,    0,              {RS}},
+{"mttcr",      XSPR(31,467,986), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtpit",      XSPR(31,467,987), XSPR_MASK, PPC403,    0,              {RS}},
+{"mttbhi",     XSPR(31,467,988), XSPR_MASK, PPC403,    0,              {RS}},
+{"mttblo",     XSPR(31,467,989), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtsrr2",     XSPR(31,467,990), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtsrr3",     XSPR(31,467,991), XSPR_MASK, PPC403,    0,              {RS}},
+{"mtdbsr",     XSPR(31,467,1008), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtdbdr",     XSPR(31,467,1011), XSPR_MASK, TITAN,    0,              {RS}},
+{"mtdbcr0",    XSPR(31,467,1010), XSPR_MASK, PPC405,   0,              {RS}},
+{"mtiac1",     XSPR(31,467,1012), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtiac2",     XSPR(31,467,1013), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtdac1",     XSPR(31,467,1014), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtdac2",     XSPR(31,467,1015), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtl2cr",     XSPR(31,467,1017), XSPR_MASK, PPC750,   0,              {RS}},
+{"mtdccr",     XSPR(31,467,1018), XSPR_MASK, PPC403,   0,              {RS}},
+{"mticcr",     XSPR(31,467,1019), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtictc",     XSPR(31,467,1019), XSPR_MASK, PPC750,   0,              {RS}},
+{"mtpbl1",     XSPR(31,467,1020), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtthrm1",    XSPR(31,467,1020), XSPR_MASK, PPC750,   0,              {RS}},
+{"mtpbu1",     XSPR(31,467,1021), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtthrm2",    XSPR(31,467,1021), XSPR_MASK, PPC750,   0,              {RS}},
+{"mtpbl2",     XSPR(31,467,1022), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtthrm3",    XSPR(31,467,1022), XSPR_MASK, PPC750,   0,              {RS}},
+{"mtpbu2",     XSPR(31,467,1023), XSPR_MASK, PPC403,   0,              {RS}},
+{"mtspr",      X(31,467),      X_MASK,      COM,       0,              {SPR, RS}},
+
+{"dcbi",       X(31,470),      XRT_MASK,    PPC,       0,              {RA0, RB}},
+
+{"nand",       XRC(31,476,0),  X_MASK,      COM,       0,              {RA, RS, RB}},
+{"nand.",      XRC(31,476,1),  X_MASK,      COM,       0,              {RA, RS, RB}},
+
+{"dsn",                X(31,483),      XRT_MASK,    E500MC,    0,              {RA, RB}},
+
+{"dcread",     X(31,486),      X_MASK,  PPC403|PPC440, PPCA2|PPC476,   {RT, RA0, RB}},
+
+{"icbtls",     X(31,486),      X_MASK,  PPCCHLK|PPC476|TITAN, 0,       {CT, RA0, RB}},
+
+{"stvxl",      X(31,487),      X_MASK,      PPCVEC,    0,              {VS, RA0, RB}},
+
+{"nabs",       XO(31,488,0,0), XORB_MASK,   M601,      0,              {RT, RA}},
+{"nabs.",      XO(31,488,0,1), XORB_MASK,   M601,      0,              {RT, RA}},
+
+{"divd",       XO(31,489,0,0), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+{"divd.",      XO(31,489,0,1), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+
+{"divw",       XO(31,491,0,0), XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"divw.",      XO(31,491,0,1), XO_MASK,     PPC,       0,              {RT, RA, RB}},
+
+{"icbtlse",    X(31,494),      X_MASK,      PPCCHLK,   E500MC,         {CT, RA, RB}},
+
+{"slbia",      X(31,498),      0xff1fffff,  POWER6,    0,              {IH}},
 {"slbia",      X(31,498),      0xffffffff,  PPC64,     POWER6,         {0}},
 
-{"cli",                X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
+{"cli",                X(31,502),      XRB_MASK,    POWER,     0,              {RT, RA}},
 
-{"popcntd",    X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
+{"popcntd",    X(31,506),      XRB_MASK, POWER7|PPCA2, 0,              {RA, RS}},
 
-{"cmpb",       X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
+{"cmpb",       X(31,508),      X_MASK, POWER6|PPCA2|PPC476, 0,         {RA, RS, RB}},
 
-{"mcrxr",      X(31,512),      XBFRARB_MASK, COM|PPCVLE, POWER7,       {BF}},
+{"mcrxr",      X(31,512),      XBFRARB_MASK, COM,      POWER7,         {BF}},
 
-{"lbdx",       X(31,515),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
+{"lbdx",       X(31,515),      X_MASK,      E500MC,    0,              {RT, RA, RB}},
 
-{"bblels",     X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
+{"bblels",     X(31,518),      X_MASK,      PPCBRLK,   0,              {0}},
 
-{"lvlx",       X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
-{"lbfcmux",    APU(31,519,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"lvlx",       X(31,519),      X_MASK,      CELL,      0,              {VD, RA0, RB}},
+{"lbfcmux",    APU(31,519,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"subfco",     XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"sfo",                XO(31,8,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"subco",      XO(31,8,1,0),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
-{"subfco.",    XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"sfo.",       XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"subco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RB, RA}},
+{"subfco",     XO(31,8,1,0),   XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"sfo",                XO(31,8,1,0),   XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"subco",      XO(31,8,1,0),   XO_MASK,     PPCCOM,    0,              {RT, RB, RA}},
+{"subfco.",    XO(31,8,1,1),   XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"sfo.",       XO(31,8,1,1),   XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"subco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM,    0,              {RT, RB, RA}},
 
-{"addco",      XO(31,10,1,0),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"ao",         XO(31,10,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"addco.",     XO(31,10,1,1),  XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"ao.",                XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"addco",      XO(31,10,1,0),  XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"ao",         XO(31,10,1,0),  XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"addco.",     XO(31,10,1,1),  XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"ao.",                XO(31,10,1,1),  XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"lxsspx",     X(31,524),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XT6, RA0, RB}},
+{"lxsspx",     X(31,524),      XX1_MASK,    PPCVSX2,   0,              {XT6, RA0, RB}},
 
-{"clcs",       X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
+{"clcs",       X(31,531),      XRB_MASK,    M601,      0,              {RT, RA}},
 
-{"ldbrx",      X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
+{"ldbrx",      X(31,532),      X_MASK, CELL|POWER7|PPCA2, 0,           {RT, RA0, RB}},
 
-{"lswx",       X(31,533),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RAX, RBX}},
-{"lsx",                X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"lswx",       X(31,533),      X_MASK,      PPCCOM,    E500|E500MC,    {RT, RAX, RBX}},
+{"lsx",                X(31,533),      X_MASK,      PWRCOM,    0,              {RT, RA, RB}},
 
-{"lwbrx",      X(31,534),      X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RT, RA0, RB}},
-{"lbrx",       X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"lwbrx",      X(31,534),      X_MASK,      PPCCOM,    0,              {RT, RA0, RB}},
+{"lbrx",       X(31,534),      X_MASK,      PWRCOM,    0,              {RT, RA, RB}},
 
-{"lfsx",       X(31,535),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
+{"lfsx",       X(31,535),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
 
-{"srw",                XRC(31,536,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
-{"sr",         XRC(31,536,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
-{"srw.",       XRC(31,536,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
-{"sr.",                XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
+{"srw",                XRC(31,536,0),  X_MASK,      PPCCOM,    0,              {RA, RS, RB}},
+{"sr",         XRC(31,536,0),  X_MASK,      PWRCOM,    0,              {RA, RS, RB}},
+{"srw.",       XRC(31,536,1),  X_MASK,      PPCCOM,    0,              {RA, RS, RB}},
+{"sr.",                XRC(31,536,1),  X_MASK,      PWRCOM,    0,              {RA, RS, RB}},
 
-{"rrib",       XRC(31,537,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"rrib.",      XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"rrib",       XRC(31,537,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"rrib.",      XRC(31,537,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"cnttzw",     XRC(31,538,0),  XRB_MASK,    POWER9,    PPCNONE,        {RA, RS}},
-{"cnttzw.",    XRC(31,538,1),  XRB_MASK,    POWER9,    PPCNONE,        {RA, RS}},
+{"cnttzw",     XRC(31,538,0),  XRB_MASK,    POWER9,    0,              {RA, RS}},
+{"cnttzw.",    XRC(31,538,1),  XRB_MASK,    POWER9,    0,              {RA, RS}},
 
-{"srd",                XRC(31,539,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
-{"srd.",       XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
+{"srd",                XRC(31,539,0),  X_MASK,      PPC64,     0,              {RA, RS, RB}},
+{"srd.",       XRC(31,539,1),  X_MASK,      PPC64,     0,              {RA, RS, RB}},
 
-{"maskir",     XRC(31,541,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"maskir.",    XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"maskir",     XRC(31,541,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"maskir.",    XRC(31,541,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"lhdx",       X(31,547),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
+{"lhdx",       X(31,547),      X_MASK,      E500MC,    0,              {RT, RA, RB}},
 
-{"lvtrx",      X(31,549),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
+{"lvtrx",      X(31,549),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"bbelr",      X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
+{"bbelr",      X(31,550),      X_MASK,      PPCBRLK,   0,              {0}},
 
-{"lvrx",       X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
-{"lhfcmux",    APU(31,551,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"lvrx",       X(31,551),      X_MASK,      CELL,      0,              {VD, RA0, RB}},
+{"lhfcmux",    APU(31,551,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"subfo",      XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
-{"subo",       XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
-{"subfo.",     XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
-{"subo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
+{"subfo",      XO(31,40,1,0),  XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"subo",       XO(31,40,1,0),  XO_MASK,     PPC,       0,              {RT, RB, RA}},
+{"subfo.",     XO(31,40,1,1),  XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"subo.",      XO(31,40,1,1),  XO_MASK,     PPC,       0,              {RT, RB, RA}},
 
-{"tlbsync",    X(31,566),      0xffffffff, PPC|PPCVLE, PPCNONE,        {0}},
+{"tlbsync",    X(31,566),      0xffffffff,  PPC,       0,              {0}},
 
-{"lfsux",      X(31,567),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
+{"lfsux",      X(31,567),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
 
-{"cnttzd",     XRC(31,570,0),  XRB_MASK,    POWER9,    PPCNONE,        {RA, RS}},
-{"cnttzd.",    XRC(31,570,1),  XRB_MASK,    POWER9,    PPCNONE,        {RA, RS}},
+{"cnttzd",     XRC(31,570,0),  XRB_MASK,    POWER9,    0,              {RA, RS}},
+{"cnttzd.",    XRC(31,570,1),  XRB_MASK,    POWER9,    0,              {RA, RS}},
 
-{"mcrxrx",     X(31,576),      XBFRARB_MASK, POWER9,   PPCNONE,        {BF}},
+{"mcrxrx",     X(31,576),     XBFRARB_MASK, POWER9,    0,              {BF}},
 
-{"lwdx",       X(31,579),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
+{"lwdx",       X(31,579),      X_MASK,      E500MC,    0,              {RT, RA, RB}},
 
-{"lvtlx",      X(31,581),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
+{"lvtlx",      X(31,581),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"lwat",       X(31,582),      X_MASK,      POWER9,    PPCNONE,        {RT, RA0, FC}},
+{"lwat",       X(31,582),      X_MASK,      POWER9,    0,              {RT, RA0, FC}},
 
-{"lwfcmux",    APU(31,583,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"lwfcmux",    APU(31,583,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"lxsdx",      X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
+{"lxsdx",      X(31,588),      XX1_MASK,    PPCVSX,    0,              {XT6, RA0, RB}},
 
-{"mfsr",       X(31,595), XRB_MASK|(1<<20), COM,       NON32,          {RT, SR}},
+{"mfsr",       X(31,595), XRB_MASK|(1<<20), COM,       NON32,          {RT, SR}},
 
-{"lswi",       X(31,597),      X_MASK,  PPCCOM|PPCVLE, E500|E500MC,    {RT, RAX, NBI}},
-{"lsi",                X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
+{"lswi",       X(31,597),      X_MASK,      PPCCOM,    E500|E500MC,    {RT, RAX, NBI}},
+{"lsi",                X(31,597),      X_MASK,      PWRCOM,    0,              {RT, RA0, NB}},
 
 {"hwsync",     XSYNC(31,598,0), 0xffffffff, POWER4,    BOOKE|PPC476,   {0}},
 {"lwsync",     XSYNC(31,598,1), 0xffffffff, PPC,       E500,           {0}},
-{"ptesync",    XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
-{"sync",       X(31,598),      XSYNCLE_MASK,POWER9|E6500, PPCNONE,     {LS, ESYNC}},
-{"sync",       X(31,598),      XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476|POWER9, {LS}},
-{"msync",      X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
-{"sync",       X(31,598),      0xffffffff, BOOKE|PPC476, E6500,        {0}},
-{"lwsync",     X(31,598),      0xffffffff, E500,       PPCNONE,        {0}},
-{"dcs",                X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
+{"ptesync",    XSYNC(31,598,2), 0xffffffff, PPC64,     0,              {0}},
+{"sync",       X(31,598),     XSYNCLE_MASK, POWER9|E6500, 0,           {LS, ESYNC}},
+{"sync",       X(31,598),     XSYNC_MASK, PPCCOM, BOOKE|PPC476|POWER9, {LS}},
+{"msync",      X(31,598),     0xffffffff, BOOKE|PPCA2|PPC476, 0,       {0}},
+{"sync",       X(31,598),     0xffffffff,   BOOKE|PPC476, E6500,       {0}},
+{"lwsync",     X(31,598),     0xffffffff,   E500,      0,              {0}},
+{"dcs",                X(31,598),     0xffffffff,   PWRCOM,    0,              {0}},
 
-{"lfdx",       X(31,599),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
+{"lfdx",       X(31,599),      X_MASK,      COM,       PPCEFS,         {FRT, RA0, RB}},
 
 {"mffgpr",     XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
-{"lfdepx",     X(31,607),      X_MASK,   E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA0, RB}},
+{"lfdepx",     X(31,607),      X_MASK,   E500MC|PPCA2, 0,              {FRT, RA0, RB}},
 
-{"lddx",       X(31,611),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {RT, RA, RB}},
+{"lddx",       X(31,611),      X_MASK,      E500MC,    0,              {RT, RA, RB}},
 
-{"lvswx",      X(31,613),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
+{"lvswx",      X(31,613),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"ldat",       X(31,614),      X_MASK,      POWER9,    PPCNONE,        {RT, RA0, FC}},
+{"ldat",       X(31,614),      X_MASK,      POWER9,    0,              {RT, RA0, FC}},
 
-{"lqfcmux",    APU(31,615,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"lqfcmux",    APU(31,615,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"nego",       XO(31,104,1,0), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
-{"nego.",      XO(31,104,1,1), XORB_MASK,   COM|PPCVLE, PPCNONE,       {RT, RA}},
+{"nego",       XO(31,104,1,0), XORB_MASK,   COM,       0,              {RT, RA}},
+{"nego.",      XO(31,104,1,1), XORB_MASK,   COM,       0,              {RT, RA}},
 
-{"mulo",       XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-{"mulo.",      XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
+{"mulo",       XO(31,107,1,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
+{"mulo.",      XO(31,107,1,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
 
-{"mfsri",      X(31,627),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
+{"mfsri",      X(31,627),      X_MASK,      M601,      0,              {RT, RA, RB}},
 
-{"dclst",      X(31,630),      XRB_MASK,    M601,      PPCNONE,        {RS, RA}},
+{"dclst",      X(31,630),      XRB_MASK,    M601,      0,              {RS, RA}},
 
-{"lfdux",      X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
+{"lfdux",      X(31,631),      X_MASK,      COM,       PPCEFS,         {FRT, RAS, RB}},
 
-{"stbdx",      X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
+{"stbdx",      X(31,643),      X_MASK,      E500MC,    0,              {RS, RA, RB}},
 
-{"stvlx",      X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
-{"stbfcmux",   APU(31,647,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stvlx",      X(31,647),      X_MASK,      CELL,      0,              {VS, RA0, RB}},
+{"stbfcmux",   APU(31,647,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"stxsspx",    X(31,652),      XX1_MASK,    PPCVSX2,   PPCNONE,        {XS6, RA0, RB}},
+{"stxsspx",    X(31,652),      XX1_MASK,    PPCVSX2,   0,              {XS6, RA0, RB}},
 
-{"tbegin.",    XRC(31,654,1), XRTLRARB_MASK,PPCHTM,    PPCNONE,        {HTM_R}},
+{"tbegin.",    XRC(31,654,1), XRTLRARB_MASK, PPCHTM,   0,              {HTM_R}},
 
-{"subfeo",     XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"sfeo",       XO(31,136,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"subfeo.",    XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"sfeo.",      XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"subfeo",     XO(31,136,1,0), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"sfeo",       XO(31,136,1,0), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"subfeo.",    XO(31,136,1,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"sfeo.",      XO(31,136,1,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"addeo",      XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"aeo",                XO(31,138,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"addeo.",     XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"aeo.",       XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"addeo",      XO(31,138,1,0), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"aeo",                XO(31,138,1,0), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"addeo.",     XO(31,138,1,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"aeo.",       XO(31,138,1,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"mfsrin",     X(31,659),      XRA_MASK,    PPC,       NON32,          {RT, RB}},
+{"mfsrin",     X(31,659),      XRA_MASK,    PPC,       NON32,          {RT, RB}},
 
-{"stdbrx",     X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
+{"stdbrx",     X(31,660),      X_MASK, CELL|POWER7|PPCA2, 0,           {RS, RA0, RB}},
 
-{"stswx",      X(31,661),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, RB}},
-{"stsx",       X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
+{"stswx",      X(31,661),      X_MASK,      PPCCOM,    E500|E500MC,    {RS, RA0, RB}},
+{"stsx",       X(31,661),      X_MASK,      PWRCOM,    0,              {RS, RA0, RB}},
 
-{"stwbrx",     X(31,662),      X_MASK, PPCCOM|PPCVLE,  PPCNONE,        {RS, RA0, RB}},
-{"stbrx",      X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
+{"stwbrx",     X(31,662),      X_MASK,      PPCCOM,    0,              {RS, RA0, RB}},
+{"stbrx",      X(31,662),      X_MASK,      PWRCOM,    0,              {RS, RA0, RB}},
 
-{"stfsx",      X(31,663),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
+{"stfsx",      X(31,663),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
 
-{"srq",                XRC(31,664,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"srq.",       XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"srq",                XRC(31,664,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"srq.",       XRC(31,664,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"sre",                XRC(31,665,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"sre.",       XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"sre",                XRC(31,665,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"sre.",       XRC(31,665,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"sthdx",      X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
+{"sthdx",      X(31,675),      X_MASK,      E500MC,    0,              {RS, RA, RB}},
 
-{"stvfrx",     X(31,677),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
+{"stvfrx",     X(31,677),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
 
-{"stvrx",      X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
-{"sthfcmux",   APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stvrx",      X(31,679),      X_MASK,      CELL,      0,              {VS, RA0, RB}},
+{"sthfcmux",   APU(31,679,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"tendall.",   XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE,   {0}},
-{"tend.",      XRC(31,686,1), XRTARARB_MASK, PPCHTM,   PPCNONE,        {HTM_A}},
+{"tendall.",   XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0,         {0}},
+{"tend.",      XRC(31,686,1), XRTARARB_MASK, PPCHTM,   0,              {HTM_A}},
 
-{"stbcx.",     XRC(31,694,1),  X_MASK,      POWER8|E6500, PPCNONE,     {RS, RA0, RB}},
+{"stbcx.",     XRC(31,694,1),  X_MASK,   POWER8|E6500, 0,              {RS, RA0, RB}},
 
-{"stfsux",     X(31,695),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
+{"stfsux",     X(31,695),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
 
-{"sriq",       XRC(31,696,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
-{"sriq.",      XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
+{"sriq",       XRC(31,696,0),  X_MASK,      M601,      0,              {RA, RS, SH}},
+{"sriq.",      XRC(31,696,1),  X_MASK,      M601,      0,              {RA, RS, SH}},
 
-{"stwdx",      X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
+{"stwdx",      X(31,707),      X_MASK,      E500MC,    0,              {RS, RA, RB}},
 
-{"stvflx",     X(31,709),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
+{"stvflx",     X(31,709),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
 
-{"stwat",      X(31,710),      X_MASK,      POWER9,    PPCNONE,        {RS, RA0, FC}},
+{"stwat",      X(31,710),      X_MASK,      POWER9,    0,              {RS, RA0, FC}},
 
-{"stwfcmux",   APU(31,711,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stwfcmux",   APU(31,711,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"stxsdx",     X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
+{"stxsdx",     X(31,716),      XX1_MASK,    PPCVSX,    0,              {XS6, RA0, RB}},
 
-{"tcheck",     X(31,718),   XRTBFRARB_MASK, PPCHTM,    PPCNONE,        {BF}},
+{"tcheck",     X(31,718),   XRTBFRARB_MASK, PPCHTM,    0,              {BF}},
 
-{"subfzeo",    XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
-{"sfzeo",      XO(31,200,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
-{"subfzeo.",   XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
-{"sfzeo.",     XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
+{"subfzeo",    XO(31,200,1,0), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"sfzeo",      XO(31,200,1,0), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
+{"subfzeo.",   XO(31,200,1,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"sfzeo.",     XO(31,200,1,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
-{"addzeo",     XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
-{"azeo",       XO(31,202,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
-{"addzeo.",    XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE,      {RT, RA}},
-{"azeo.",      XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
+{"addzeo",     XO(31,202,1,0), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"azeo",       XO(31,202,1,0), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
+{"addzeo.",    XO(31,202,1,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"azeo.",      XO(31,202,1,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
-{"stswi",      X(31,725),      X_MASK, PPCCOM|PPCVLE,  E500|E500MC,    {RS, RA0, NB}},
-{"stsi",       X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
+{"stswi",      X(31,725),      X_MASK,      PPCCOM,    E500|E500MC,    {RS, RA0, NB}},
+{"stsi",       X(31,725),      X_MASK,      PWRCOM,    0,              {RS, RA0, NB}},
 
-{"sthcx.",     XRC(31,726,1),  X_MASK,      POWER8|E6500, PPCNONE,     {RS, RA0, RB}},
+{"sthcx.",     XRC(31,726,1),  X_MASK,   POWER8|E6500, 0,              {RS, RA0, RB}},
 
-{"stfdx",      X(31,727),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
+{"stfdx",      X(31,727),      X_MASK,      COM,       PPCEFS,         {FRS, RA0, RB}},
 
-{"srlq",       XRC(31,728,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"srlq.",      XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"srlq",       XRC(31,728,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"srlq.",      XRC(31,728,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"sreq",       XRC(31,729,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"sreq.",      XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"sreq",       XRC(31,729,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"sreq.",      XRC(31,729,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
 {"mftgpr",     XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
-{"stfdepx",    X(31,735),      X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,   {FRS, RA0, RB}},
+{"stfdepx",    X(31,735),      X_MASK,   E500MC|PPCA2, 0,              {FRS, RA0, RB}},
 
-{"stddx",      X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
+{"stddx",      X(31,739),      X_MASK,      E500MC,    0,              {RS, RA, RB}},
 
-{"stvswx",     X(31,741),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
+{"stvswx",     X(31,741),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
 
-{"stdat",      X(31,742),      X_MASK,      POWER9,    PPCNONE,        {RS, RA0, FC}},
+{"stdat",      X(31,742),      X_MASK,      POWER9,    0,              {RS, RA0, FC}},
 
-{"stqfcmux",   APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stqfcmux",   APU(31,743,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"subfmeo",    XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
-{"sfmeo",      XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
-{"subfmeo.",   XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
-{"sfmeo.",     XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
+{"subfmeo",    XO(31,232,1,0), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"sfmeo",      XO(31,232,1,0), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
+{"subfmeo.",   XO(31,232,1,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"sfmeo.",     XO(31,232,1,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
-{"mulldo",     XO(31,233,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"mulldo.",    XO(31,233,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
+{"mulldo",     XO(31,233,1,0), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+{"mulldo.",    XO(31,233,1,1), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
 
-{"addmeo",     XO(31,234,1,0), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"ameo",       XO(31,234,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
-{"addmeo.",    XO(31,234,1,1), XORB_MASK,   PPCCOM|PPCVLE, PPCNONE,    {RT, RA}},
-{"ameo.",      XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
+{"addmeo",     XO(31,234,1,0), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"ameo",       XO(31,234,1,0), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
+{"addmeo.",    XO(31,234,1,1), XORB_MASK,   PPCCOM,    0,              {RT, RA}},
+{"ameo.",      XO(31,234,1,1), XORB_MASK,   PWRCOM,    0,              {RT, RA}},
 
-{"mullwo",     XO(31,235,1,0), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"mulso",      XO(31,235,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"mullwo.",    XO(31,235,1,1), XO_MASK,     PPCCOM|PPCVLE, PPCNONE,    {RT, RA, RB}},
-{"mulso.",     XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"mullwo",     XO(31,235,1,0), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"mulso",      XO(31,235,1,0), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"mullwo.",    XO(31,235,1,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"mulso.",     XO(31,235,1,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"tsuspend.",  XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM,  PPCNONE,        {0}},
-{"tresume.",   XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM,  PPCNONE,        {0}},
-{"tsr.",       XRC(31,750,1),    XRTLRARB_MASK,PPCHTM, PPCNONE,        {L}},
+{"tsuspend.",  XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM,  0,              {0}},
+{"tresume.",   XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM,  0,              {0}},
+{"tsr.",       XRC(31,750,1),    XRTLRARB_MASK,PPCHTM, 0,              {L}},
 
-{"darn",       X(31,755),      XLRAND_MASK, POWER9,    PPCNONE,        {RT, LRAND}},
+{"darn",       X(31,755),      XLRAND_MASK, POWER9,    0,              {RT, LRAND}},
 
-{"dcba",       X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
-{"dcbal",      XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA0, RB}},
+{"dcba",       X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
+{"dcbal",      XOPL(31,758,1), XRT_MASK,    E500MC,    0,              {RA0, RB}},
 
-{"stfdux",     X(31,759),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
+{"stfdux",     X(31,759),      X_MASK,      COM,       PPCEFS,         {FRS, RAS, RB}},
 
-{"srliq",      XRC(31,760,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
-{"srliq.",     XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
+{"srliq",      XRC(31,760,0),  X_MASK,      M601,      0,              {RA, RS, SH}},
+{"srliq.",     XRC(31,760,1),  X_MASK,      M601,      0,              {RA, RS, SH}},
 
-{"lvsm",       X(31,773),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
+{"lvsm",       X(31,773),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"copy_first", XOPL(31,774,1), XRT_MASK,    POWER9,    PPCNONE,        {RA0, RB}},
-{"copy",       X(31,774),      XLRT_MASK,   POWER9,    PPCNONE,        {RA0, RB, L}},
+{"copy_first", XOPL(31,774,1), XRT_MASK,    POWER9,    0,              {RA0, RB}},
+{"copy",       X(31,774),      XLRT_MASK,   POWER9,    0,              {RA0, RB, L}},
 
-{"stvepxl",    X(31,775),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
-{"lvlxl",      X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
-{"ldfcmux",    APU(31,775,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stvepxl",    X(31,775),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
+{"lvlxl",      X(31,775),      X_MASK,      CELL,      0,              {VD, RA0, RB}},
+{"ldfcmux",    APU(31,775,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"dozo",       XO(31,264,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-{"dozo.",      XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
+{"dozo",       XO(31,264,1,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
+{"dozo.",      XO(31,264,1,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
 
-{"addo",       XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"caxo",       XO(31,266,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
-{"addo.",      XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"caxo.",      XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
+{"addo",       XO(31,266,1,0), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"caxo",       XO(31,266,1,0), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
+{"addo.",      XO(31,266,1,1), XO_MASK,     PPCCOM,    0,              {RT, RA, RB}},
+{"caxo.",      XO(31,266,1,1), XO_MASK,     PWRCOM,    0,              {RT, RA, RB}},
 
-{"modsd",      X(31,777),      X_MASK,      POWER9,    PPCNONE,        {RT, RA, RB}},
-{"modsw",      X(31,779),      X_MASK,      POWER9,    PPCNONE,        {RT, RA, RB}},
+{"modsd",      X(31,777),      X_MASK,      POWER9,    0,              {RT, RA, RB}},
+{"modsw",      X(31,779),      X_MASK,      POWER9,    0,              {RT, RA, RB}},
 
-{"lxvw4x",     X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
-{"lxsibzx",    X(31,781),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
+{"lxvw4x",     X(31,780),      XX1_MASK,    PPCVSX,    0,              {XT6, RA0, RB}},
+{"lxsibzx",    X(31,781),      XX1_MASK,    PPCVSX3,   0,              {XT6, RA0, RB}},
 
-{"tabortwc.",  XRC(31,782,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, RB}},
+{"tabortwc.",  XRC(31,782,1),  X_MASK,      PPCHTM,    0,              {TO, RA, RB}},
 
-{"tlbivax",    X(31,786),      XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
+{"tlbivax",    X(31,786),      XRT_MASK, BOOKE|PPCA2|PPC476, 0,        {RA0, RB}},
 
-{"lwzcix",     X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
+{"lwzcix",     X(31,789),      X_MASK,      POWER6,    0,              {RT, RA0, RB}},
 
-{"lhbrx",      X(31,790),      X_MASK,      COM|PPCVLE, PPCNONE,       {RT, RA0, RB}},
+{"lhbrx",      X(31,790),      X_MASK,      COM,       0,              {RT, RA0, RB}},
 
-{"lfdpx",      X(31,791),      X_MASK,      POWER6,    POWER7,         {FRTp, RA0, RB}},
-{"lfqx",       X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
+{"lfdpx",      X(31,791),      X_MASK,      POWER6,    POWER7,         {FRTp, RA0, RB}},
+{"lfqx",       X(31,791),      X_MASK,      POWER2,    0,              {FRT, RA, RB}},
 
-{"sraw",       XRC(31,792,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
-{"sra",                XRC(31,792,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
-{"sraw.",      XRC(31,792,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, RB}},
-{"sra.",       XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
+{"sraw",       XRC(31,792,0),  X_MASK,      PPCCOM,    0,              {RA, RS, RB}},
+{"sra",                XRC(31,792,0),  X_MASK,      PWRCOM,    0,              {RA, RS, RB}},
+{"sraw.",      XRC(31,792,1),  X_MASK,      PPCCOM,    0,              {RA, RS, RB}},
+{"sra.",       XRC(31,792,1),  X_MASK,      PWRCOM,    0,              {RA, RS, RB}},
 
-{"srad",       XRC(31,794,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
-{"srad.",      XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
+{"srad",       XRC(31,794,0),  X_MASK,      PPC64,     0,              {RA, RS, RB}},
+{"srad.",      XRC(31,794,1),  X_MASK,      PPC64,     0,              {RA, RS, RB}},
 
-{"lfddx",      X(31,803),      X_MASK,      E500MC|PPCVLE, PPCNONE,    {FRT, RA, RB}},
+{"lfddx",      X(31,803),      X_MASK,      E500MC,    0,              {FRT, RA, RB}},
 
-{"lvtrxl",     X(31,805),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
-{"stvepx",     X(31,807),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
-{"lvrxl",      X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
+{"lvtrxl",     X(31,805),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
+{"stvepx",     X(31,807),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
+{"lvrxl",      X(31,807),      X_MASK,      CELL,      0,              {VD, RA0, RB}},
 
-{"lxvh8x",     X(31,812),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
-{"lxsihzx",    X(31,813),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
+{"lxvh8x",     X(31,812),      XX1_MASK,    PPCVSX3,   0,              {XT6, RA0, RB}},
+{"lxsihzx",    X(31,813),      XX1_MASK,    PPCVSX3,   0,              {XT6, RA0, RB}},
 
-{"tabortdc.",  XRC(31,814,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, RB}},
+{"tabortdc.",  XRC(31,814,1),  X_MASK,      PPCHTM,    0,              {TO, RA, RB}},
 
-{"rac",                X(31,818),      X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
+{"rac",                X(31,818),      X_MASK,      M601,      0,              {RT, RA, RB}},
 
-{"erativax",   X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
+{"erativax",   X(31,819),      X_MASK,      PPCA2,     0,              {RS, RA0, RB}},
 
-{"lhzcix",     X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
+{"lhzcix",     X(31,821),      X_MASK,      POWER6,    0,              {RT, RA0, RB}},
 
-{"dss",                XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
+{"dss",                XDSS(31,822,0), XDSS_MASK,   PPCVEC,    0,              {STRM}},
 
-{"lfqux",      X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
+{"lfqux",      X(31,823),      X_MASK,      POWER2,    0,              {FRT, RA, RB}},
 
-{"srawi",      XRC(31,824,0),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
-{"srai",       XRC(31,824,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
-{"srawi.",     XRC(31,824,1),  X_MASK,  PPCCOM|PPCVLE, PPCNONE,        {RA, RS, SH}},
-{"srai.",      XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
+{"srawi",      XRC(31,824,0),  X_MASK,      PPCCOM,    0,              {RA, RS, SH}},
+{"srai",       XRC(31,824,0),  X_MASK,      PWRCOM,    0,              {RA, RS, SH}},
+{"srawi.",     XRC(31,824,1),  X_MASK,      PPCCOM,    0,              {RA, RS, SH}},
+{"srai.",      XRC(31,824,1),  X_MASK,      PWRCOM,    0,              {RA, RS, SH}},
 
-{"sradi",      XS(31,413,0),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
-{"sradi.",     XS(31,413,1),   XS_MASK,     PPC64|PPCVLE, PPCNONE,     {RA, RS, SH6}},
+{"sradi",      XS(31,413,0),   XS_MASK,     PPC64,     0,              {RA, RS, SH6}},
+{"sradi.",     XS(31,413,1),   XS_MASK,     PPC64,     0,              {RA, RS, SH6}},
 
-{"lvtlxl",     X(31,837),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
+{"lvtlxl",     X(31,837),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"cp_abort",   X(31,838),      XRTRARB_MASK,POWER9,    PPCNONE,        {0}},
+{"cp_abort",   X(31,838),      XRTRARB_MASK,POWER9,    0,              {0}},
 
-{"divo",       XO(31,331,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-{"divo.",      XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
+{"divo",       XO(31,331,1,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
+{"divo.",      XO(31,331,1,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
 
-{"lxvd2x",     X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA0, RB}},
+{"lxvd2x",     X(31,844),      XX1_MASK,    PPCVSX,    0,              {XT6, RA0, RB}},
 {"lxvx",       X(31,844),      XX1_MASK,    POWER8,    POWER9|PPCVSX3, {XT6, RA0, RB}},
 
-{"tabortwci.", XRC(31,846,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, HTM_SI}},
+{"tabortwci.", XRC(31,846,1),  X_MASK,      PPCHTM,    0,              {TO, RA, HTM_SI}},
 
-{"tlbsrx.",    XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
+{"tlbsrx.",    XRC(31,850,1),  XRT_MASK,    PPCA2,     0,              {RA0, RB}},
 
-{"slbmfev",    X(31,851),      XRLA_MASK,   POWER9,    PPCNONE,        {RT, RB, A_L}},
+{"slbmfev",    X(31,851),      XRLA_MASK,   POWER9,    0,              {RT, RB, A_L}},
 {"slbmfev",    X(31,851),      XRA_MASK,    PPC64,     POWER9,         {RT, RB}},
 
-{"lbzcix",     X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
+{"lbzcix",     X(31,853),      X_MASK,      POWER6,    0,              {RT, RA0, RB}},
 
 {"eieio",      X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
-{"mbar",       X(31,854),      X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}},
-{"eieio",      XMBAR(31,854,1),0xffffffff,  E500,      PPCNONE,        {0}},
-{"eieio",      X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
+{"mbar",       X(31,854),      X_MASK,    BOOKE|PPCA2|PPC476, 0,       {MO}},
+{"eieio",      XMBAR(31,854,1),0xffffffff,  E500,      0,              {0}},
+{"eieio",      X(31,854),      0xffffffff, PPCA2|PPC476, 0,            {0}},
 
-{"lfiwax",     X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
+{"lfiwax",     X(31,855),      X_MASK, POWER6|PPCA2|PPC476, 0,         {FRT, RA0, RB}},
 
-{"lvswxl",     X(31,869),      X_MASK,      PPCVEC2,   PPCNONE,        {VD, RA0, RB}},
+{"lvswxl",     X(31,869),      X_MASK,      PPCVEC2,   0,              {VD, RA0, RB}},
 
-{"abso",       XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
-{"abso.",      XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
+{"abso",       XO(31,360,1,0), XORB_MASK,   M601,      0,              {RT, RA}},
+{"abso.",      XO(31,360,1,1), XORB_MASK,   M601,      0,              {RT, RA}},
 
-{"divso",      XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
-{"divso.",     XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
+{"divso",      XO(31,363,1,0), XO_MASK,     M601,      0,              {RT, RA, RB}},
+{"divso.",     XO(31,363,1,1), XO_MASK,     M601,      0,              {RT, RA, RB}},
 
-{"lxvb16x",    X(31,876),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA0, RB}},
+{"lxvb16x",    X(31,876),      XX1_MASK,    PPCVSX3,   0,              {XT6, RA0, RB}},
 
-{"tabortdci.", XRC(31,878,1),  X_MASK,      PPCHTM,    PPCNONE,        {TO, RA, HTM_SI}},
+{"tabortdci.", XRC(31,878,1),  X_MASK,      PPCHTM,    0,              {TO, RA, HTM_SI}},
 
-{"rmieg",      X(31,882),      XRTRA_MASK,  POWER9,    PPCNONE,        {RB}},
+{"rmieg",      X(31,882),      XRTRA_MASK,  POWER9,    0,              {RB}},
 
-{"ldcix",      X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
+{"ldcix",      X(31,885),      X_MASK,      POWER6,    0,              {RT, RA0, RB}},
 
-{"msgsync",    X(31,886),      0xffffffff,  POWER9,    PPCNONE,        {0}},
+{"msgsync",    X(31,886),      0xffffffff,  POWER9,    0,              {0}},
 
-{"lfiwzx",     X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
+{"lfiwzx",     X(31,887),      X_MASK,   POWER7|PPCA2, 0,              {FRT, RA0, RB}},
 
-{"extswsli",   XS(31,445,0),   XS_MASK,     POWER9,    PPCNONE,        {RA, RS, SH6}},
-{"extswsli.",  XS(31,445,1),   XS_MASK,     POWER9,    PPCNONE,        {RA, RS, SH6}},
+{"extswsli",   XS(31,445,0),   XS_MASK,     POWER9,    0,              {RA, RS, SH6}},
+{"extswsli.",  XS(31,445,1),   XS_MASK,     POWER9,    0,              {RA, RS, SH6}},
 
-{"paste",      XRC(31,902,0),  XLRT_MASK,   POWER9,    PPCNONE,        {RA0, RB, L0}},
-{"paste_last", XRCL(31,902,1,1),XRT_MASK,   POWER9,    PPCNONE,        {RA0, RB}},
-{"paste.",     XRC(31,902,1),  XLRT_MASK,   POWER9,    PPCNONE,        {RA0, RB, L1}},
+{"paste",      XRC(31,902,0),  XLRT_MASK,   POWER9,    0,              {RA0, RB, L0}},
+{"paste_last", XRCL(31,902,1,1),XRT_MASK,   POWER9,    0,              {RA0, RB}},
+{"paste.",     XRC(31,902,1),  XLRT_MASK,   POWER9,    0,              {RA0, RB, L1}},
 
-{"stvlxl",     X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
-{"stdfcmux",   APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
+{"stvlxl",     X(31,903),      X_MASK,      CELL,      0,              {VS, RA0, RB}},
+{"stdfcmux",   APU(31,903,0),  APU_MASK,    PPC405,    0,              {FCRT, RA, RB}},
 
-{"divdeuo",    XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divdeuo.",   XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divweuo",    XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divweuo.",   XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divdeuo",    XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divdeuo.",   XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divweuo",    XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divweuo.",   XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
 
-{"stxvw4x",    X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
-{"stxsibx",    X(31,909),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
+{"stxvw4x",    X(31,908),      XX1_MASK,    PPCVSX,    0,              {XS6, RA0, RB}},
+{"stxsibx",    X(31,909),      XX1_MASK,    PPCVSX3,   0,              {XS6, RA0, RB}},
 
-{"tabort.",    XRC(31,910,1),  XRTRB_MASK,  PPCHTM,    PPCNONE,        {RA}},
+{"tabort.",    XRC(31,910,1),  XRTRB_MASK,  PPCHTM,    0,              {RA}},
 
-{"tlbsx",      XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
-{"tlbsx.",     XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
+{"tlbsx",      XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0,   {RTO, RA0, RB}},
+{"tlbsx.",     XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0,   {RTO, RA0, RB}},
 
-{"slbmfee",    X(31,915),      XRLA_MASK,   POWER9,    PPCNONE,        {RT, RB, A_L}},
+{"slbmfee",    X(31,915),      XRLA_MASK,   POWER9,    0,              {RT, RB, A_L}},
 {"slbmfee",    X(31,915),      XRA_MASK,    PPC64,     POWER9,         {RT, RB}},
 
-{"stwcix",     X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
+{"stwcix",     X(31,917),      X_MASK,      POWER6,    0,              {RS, RA0, RB}},
 
-{"sthbrx",     X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
+{"sthbrx",     X(31,918),      X_MASK,      COM,       0,              {RS, RA0, RB}},
 
-{"stfdpx",     X(31,919),      X_MASK,      POWER6,    POWER7,         {FRSp, RA0, RB}},
-{"stfqx",      X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA0, RB}},
+{"stfdpx",     X(31,919),      X_MASK,      POWER6,    POWER7,         {FRSp, RA0, RB}},
+{"stfqx",      X(31,919),      X_MASK,      POWER2,    0,              {FRS, RA0, RB}},
 
-{"sraq",       XRC(31,920,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"sraq.",      XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"sraq",       XRC(31,920,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"sraq.",      XRC(31,920,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"srea",       XRC(31,921,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
-{"srea.",      XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
+{"srea",       XRC(31,921,0),  X_MASK,      M601,      0,              {RA, RS, RB}},
+{"srea.",      XRC(31,921,1),  X_MASK,      M601,      0,              {RA, RS, RB}},
 
-{"extsh",      XRC(31,922,0),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
-{"exts",       XRC(31,922,0),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
-{"extsh.",     XRC(31,922,1),  XRB_MASK,    PPCCOM|PPCVLE, PPCNONE,    {RA, RS}},
-{"exts.",      XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
+{"extsh",      XRC(31,922,0),  XRB_MASK,    PPCCOM,    0,              {RA, RS}},
+{"exts",       XRC(31,922,0),  XRB_MASK,    PWRCOM,    0,              {RA, RS}},
+{"extsh.",     XRC(31,922,1),  XRB_MASK,    PPCCOM,    0,              {RA, RS}},
+{"exts.",      XRC(31,922,1),  XRB_MASK,    PWRCOM,    0,              {RA, RS}},
 
-{"stfddx",     X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
+{"stfddx",     X(31,931),      X_MASK,      E500MC,    0,              {FRS, RA, RB}},
 
-{"stvfrxl",    X(31,933),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
+{"stvfrxl",    X(31,933),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
 
-{"wclrone",    XOPL2(31,934,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
-{"wclrall",    X(31,934),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
-{"wclr",       X(31,934),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
+{"wclrone",    XOPL2(31,934,2),XRT_MASK,    PPCA2,     0,              {RA0, RB}},
+{"wclrall",    X(31,934),      XRARB_MASK,  PPCA2,     0,              {L}},
+{"wclr",       X(31,934),      X_MASK,      PPCA2,     0,              {L, RA0, RB}},
 
-{"stvrxl",     X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
+{"stvrxl",     X(31,935),      X_MASK,      CELL,      0,              {VS, RA0, RB}},
 
-{"divdeo",     XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divdeo.",    XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divweo",     XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
-{"divweo.",    XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divdeo",     XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divdeo.",    XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divweo",     XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
+{"divweo.",    XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, 0,              {RT, RA, RB}},
 
-{"stxvh8x",    X(31,940),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
-{"stxsihx",    X(31,941),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
+{"stxvh8x",    X(31,940),      XX1_MASK,    PPCVSX3,   0,              {XS6, RA0, RB}},
+{"stxsihx",    X(31,941),      XX1_MASK,    PPCVSX3,   0,              {XS6, RA0, RB}},
 
-{"treclaim.",  XRC(31,942,1),  XRTRB_MASK,  PPCHTM,    PPCNONE,        {RA}},
+{"treclaim.",  XRC(31,942,1),  XRTRB_MASK,  PPCHTM,    0,              {RA}},
 
 {"tlbrehi",    XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
 {"tlbrelo",    XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
-{"tlbre",      X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbre",      X(31,946),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0,       {RSO, RAOPT, SHO}},
 
-{"sthcix",     X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
+{"sthcix",     X(31,949),      X_MASK,      POWER6,    0,              {RS, RA0, RB}},
 
-{"icswepx",    XRC(31,950,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
-{"icswepx.",   XRC(31,950,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
+{"icswepx",    XRC(31,950,0),  X_MASK,      PPCA2,     0,              {RS, RA, RB}},
+{"icswepx.",   XRC(31,950,1),  X_MASK,      PPCA2,     0,              {RS, RA, RB}},
 
-{"stfqux",     X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
+{"stfqux",     X(31,951),      X_MASK,      POWER2,    0,              {FRS, RA, RB}},
 
-{"sraiq",      XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
-{"sraiq.",     XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
+{"sraiq",      XRC(31,952,0),  X_MASK,      M601,      0,              {RA, RS, SH}},
+{"sraiq.",     XRC(31,952,1),  X_MASK,      M601,      0,              {RA, RS, SH}},
 
-{"extsb",      XRC(31,954,0),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
-{"extsb.",     XRC(31,954,1),  XRB_MASK, PPC|PPCVLE,   PPCNONE,        {RA, RS}},
+{"extsb",      XRC(31,954,0),  XRB_MASK,    PPC,       0,              {RA, RS}},
+{"extsb.",     XRC(31,954,1),  XRB_MASK,    PPC,       0,              {RA, RS}},
 
-{"stvflxl",    X(31,965),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
+{"stvflxl",    X(31,965),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
 
-{"iccci",      X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
-{"ici",                X(31,966),      XRARB_MASK,  PPCA2|PPC476|PPCVLE, PPCNONE, {CT}},
+{"iccci",      X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0,       {RAOPT, RBOPT}},
+{"ici",                X(31,966),      XRARB_MASK,  PPCA2|PPC476, 0,           {CT}},
 
-{"divduo",     XO(31,457,1,0), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
-{"divduo.",    XO(31,457,1,1), XO_MASK,     PPC64|PPCVLE, PPCNONE,     {RT, RA, RB}},
+{"divduo",     XO(31,457,1,0), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+{"divduo.",    XO(31,457,1,1), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
 
-{"divwuo",     XO(31,459,1,0), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
-{"divwuo.",    XO(31,459,1,1), XO_MASK,     PPC|PPCVLE, PPCNONE,       {RT, RA, RB}},
+{"divwuo",     XO(31,459,1,0), XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"divwuo.",    XO(31,459,1,1), XO_MASK,     PPC,       0,              {RT, RA, RB}},
 
-{"stxvd2x",    X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA0, RB}},
+{"stxvd2x",    X(31,972),      XX1_MASK,    PPCVSX,    0,              {XS6, RA0, RB}},
 {"stxvx",      X(31,972),      XX1_MASK,    POWER8,    POWER9|PPCVSX3, {XS6, RA0, RB}},
 
 {"tlbld",      X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
-{"tlbwehi",    XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
-{"tlbwelo",    XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
-{"tlbwe",      X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbwehi",    XTLB(31,978,0), XTLB_MASK,   PPC403,    0,              {RT, RA}},
+{"tlbwelo",    XTLB(31,978,1), XTLB_MASK,   PPC403,    0,              {RT, RA}},
+{"tlbwe",      X(31,978),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0,       {RSO, RAOPT, SHO}},
 
-{"slbfee.",    XRC(31,979,1),  XRA_MASK,    POWER6,    PPCNONE,        {RT, RB}},
+{"slbfee.",    XRC(31,979,1),  XRA_MASK,    POWER6,    0,              {RT, RB}},
 
-{"stbcix",     X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
+{"stbcix",     X(31,981),      X_MASK,      POWER6,    0,              {RS, RA0, RB}},
 
-{"icbi",       X(31,982),      XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
+{"icbi",       X(31,982),      XRT_MASK,    PPC,       0,              {RA0, RB}},
 
-{"stfiwx",     X(31,983),      X_MASK,      PPC,       PPCEFS,         {FRS, RA0, RB}},
+{"stfiwx",     X(31,983),      X_MASK,      PPC,       PPCEFS,         {FRS, RA0, RB}},
 
-{"extsw",      XRC(31,986,0),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
-{"extsw.",     XRC(31,986,1),  XRB_MASK, PPC64|PPCVLE, PPCNONE,        {RA, RS}},
+{"extsw",      XRC(31,986,0),  XRB_MASK,    PPC64,     0,              {RA, RS}},
+{"extsw.",     XRC(31,986,1),  XRB_MASK,    PPC64,     0,              {RA, RS}},
 
-{"icbiep",     XRT(31,991,0),  XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+{"icbiep",     XRT(31,991,0),  XRT_MASK,    E500MC|PPCA2, 0,           {RA0, RB}},
 
-{"stvswxl",    X(31,997),      X_MASK,      PPCVEC2,   PPCNONE,        {VS, RA0, RB}},
+{"stvswxl",    X(31,997),      X_MASK,      PPCVEC2,   0,              {VS, RA0, RB}},
 
-{"icread",     X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA0, RB}},
+{"icread",     X(31,998),     XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
 
-{"nabso",      XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
-{"nabso.",     XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
+{"nabso",      XO(31,488,1,0), XORB_MASK,   M601,      0,              {RT, RA}},
+{"nabso.",     XO(31,488,1,1), XORB_MASK,   M601,      0,              {RT, RA}},
 
-{"divdo",      XO(31,489,1,0), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
-{"divdo.",     XO(31,489,1,1), XO_MASK,  PPC64|PPCVLE, PPCNONE,        {RT, RA, RB}},
+{"divdo",      XO(31,489,1,0), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
+{"divdo.",     XO(31,489,1,1), XO_MASK,     PPC64,     0,              {RT, RA, RB}},
 
-{"divwo",      XO(31,491,1,0), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
-{"divwo.",     XO(31,491,1,1), XO_MASK,   PPC|PPCVLE,  PPCNONE,        {RT, RA, RB}},
+{"divwo",      XO(31,491,1,0), XO_MASK,     PPC,       0,              {RT, RA, RB}},
+{"divwo.",     XO(31,491,1,1), XO_MASK,     PPC,       0,              {RT, RA, RB}},
 
-{"stxvb16x",   X(31,1004),     XX1_MASK,    PPCVSX3,   PPCNONE,        {XS6, RA0, RB}},
+{"stxvb16x",   X(31,1004),     XX1_MASK,    PPCVSX3,   0,              {XS6, RA0, RB}},
 
-{"trechkpt.",  XRC(31,1006,1), XRTRARB_MASK,PPCHTM,    PPCNONE,        {0}},
+{"trechkpt.",  XRC(31,1006,1), XRTRARB_MASK,PPCHTM,    0,              {0}},
 
-{"tlbli",      X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
+{"tlbli",      X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
 
-{"stdcix",     X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
+{"stdcix",     X(31,1013),     X_MASK,      POWER6,    0,              {RS, RA0, RB}},
 
-{"dcbz",       X(31,1014),     XRT_MASK,    PPC|PPCVLE, PPCNONE,       {RA0, RB}},
-{"dclz",       X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA0, RB}},
+{"dcbz",       X(31,1014),     XRT_MASK,    PPC,       0,              {RA0, RB}},
+{"dclz",       X(31,1014),     XRT_MASK,    PPC,       0,              {RA0, RB}},
 
-{"dcbzep",     XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}},
+{"dcbzep",     XRT(31,1023,0), XRT_MASK,    E500MC|PPCA2, 0,           {RA0, RB}},
 
-{"dcbzl",      XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA0, RB}},
+{"dcbzl",      XOPL(31,1014,1), XRT_MASK,   POWER4|E500MC, PPC476,     {RA0, RB}},
 
-{"cctpl",      0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
-{"cctpm",      0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
-{"cctph",      0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
+{"cctpl",      0x7c210b78,     0xffffffff,  CELL,      0,              {0}},
+{"cctpm",      0x7c421378,     0xffffffff,  CELL,      0,              {0}},
+{"cctph",      0x7c631b78,     0xffffffff,  CELL,      0,              {0}},
 
-{"dstt",       XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
-{"dststt",     XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
-{"dssall",     XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
+{"dstt",       XDSS(31,342,1), XDSS_MASK,   PPCVEC,    0,              {RA, RB, STRM}},
+{"dststt",     XDSS(31,374,1), XDSS_MASK,   PPCVEC,    0,              {RA, RB, STRM}},
+{"dssall",     XDSS(31,822,1), XDSS_MASK,   PPCVEC,    0,              {0}},
 
-{"db8cyc",     0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
-{"db10cyc",    0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
-{"db12cyc",    0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
-{"db16cyc",    0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
+{"db8cyc",     0x7f9ce378,     0xffffffff,  CELL,      0,              {0}},
+{"db10cyc",    0x7fbdeb78,     0xffffffff,  CELL,      0,              {0}},
+{"db12cyc",    0x7fdef378,     0xffffffff,  CELL,      0,              {0}},
+{"db16cyc",    0x7ffffb78,     0xffffffff,  CELL,      0,              {0}},
 
-{"lwz",                OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
-{"l",          OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
+{"lwz",                OP(32),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, D, RA0}},
+{"l",          OP(32),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, D, RA0}},
 
-{"lwzu",       OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
-{"lu",         OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
+{"lwzu",       OP(33),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, D, RAL}},
+{"lu",         OP(33),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, D, RA0}},
 
-{"lbz",                OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
+{"lbz",                OP(34),         OP_MASK,     COM,       PPCVLE,         {RT, D, RA0}},
 
-{"lbzu",       OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
+{"lbzu",       OP(35),         OP_MASK,     COM,       PPCVLE,         {RT, D, RAL}},
 
-{"stw",                OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
-{"st",         OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
+{"stw",                OP(36),         OP_MASK,     PPCCOM,    PPCVLE,         {RS, D, RA0}},
+{"st",         OP(36),         OP_MASK,     PWRCOM,    PPCVLE,         {RS, D, RA0}},
 
-{"stwu",       OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
-{"stu",                OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
+{"stwu",       OP(37),         OP_MASK,     PPCCOM,    PPCVLE,         {RS, D, RAS}},
+{"stu",                OP(37),         OP_MASK,     PWRCOM,    PPCVLE,         {RS, D, RA0}},
 
-{"stb",                OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
+{"stb",                OP(38),         OP_MASK,     COM,       PPCVLE,         {RS, D, RA0}},
 
-{"stbu",       OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
+{"stbu",       OP(39),         OP_MASK,     COM,       PPCVLE,         {RS, D, RAS}},
 
-{"lhz",                OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
+{"lhz",                OP(40),         OP_MASK,     COM,       PPCVLE,         {RT, D, RA0}},
 
-{"lhzu",       OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
+{"lhzu",       OP(41),         OP_MASK,     COM,       PPCVLE,         {RT, D, RAL}},
 
-{"lha",                OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
+{"lha",                OP(42),         OP_MASK,     COM,       PPCVLE,         {RT, D, RA0}},
 
-{"lhau",       OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
+{"lhau",       OP(43),         OP_MASK,     COM,       PPCVLE,         {RT, D, RAL}},
 
-{"sth",                OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
+{"sth",                OP(44),         OP_MASK,     COM,       PPCVLE,         {RS, D, RA0}},
 
-{"sthu",       OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
+{"sthu",       OP(45),         OP_MASK,     COM,       PPCVLE,         {RS, D, RAS}},
 
-{"lmw",                OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
-{"lm",         OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
+{"lmw",                OP(46),         OP_MASK,     PPCCOM,    PPCVLE,         {RT, D, RAM}},
+{"lm",         OP(46),         OP_MASK,     PWRCOM,    PPCVLE,         {RT, D, RA0}},
 
-{"stmw",       OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
-{"stm",                OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
+{"stmw",       OP(47),         OP_MASK,     PPCCOM,    PPCVLE,         {RS, D, RA0}},
+{"stm",                OP(47),         OP_MASK,     PWRCOM,    PPCVLE,         {RS, D, RA0}},
 
-{"lfs",                OP(48),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
+{"lfs",                OP(48),         OP_MASK,     COM,       PPCEFS|PPCVLE,  {FRT, D, RA0}},
 
-{"lfsu",       OP(49),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
+{"lfsu",       OP(49),         OP_MASK,     COM,       PPCEFS|PPCVLE,  {FRT, D, RAS}},
 
-{"lfd",                OP(50),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RA0}},
+{"lfd",                OP(50),         OP_MASK,     COM,       PPCEFS|PPCVLE,  {FRT, D, RA0}},
 
-{"lfdu",       OP(51),         OP_MASK,     COM,       PPCEFS,         {FRT, D, RAS}},
+{"lfdu",       OP(51),         OP_MASK,     COM,       PPCEFS|PPCVLE,  {FRT, D, RAS}},
 
-{"stfs",       OP(52),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
+{"stfs",       OP(52),         OP_MASK,     COM,       PPCEFS|PPCVLE,  {FRS, D, RA0}},
 
-{"stfsu",      OP(53),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
+{"stfsu",      OP(53),         OP_MASK,     COM,       PPCEFS|PPCVLE,  {FRS, D, RAS}},
 
-{"stfd",       OP(54),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RA0}},
+{"stfd",       OP(54),         OP_MASK,     COM,       PPCEFS|PPCVLE,  {FRS, D, RA0}},
 
-{"stfdu",      OP(55),         OP_MASK,     COM,       PPCEFS,         {FRS, D, RAS}},
+{"stfdu",      OP(55),         OP_MASK,     COM,       PPCEFS|PPCVLE,  {FRS, D, RAS}},
 
-{"lq",         OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
-{"psq_l",      OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
-{"lfq",                OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
+{"lq",         OP(56),         OP_MASK,     POWER4,    PPC476|PPCVLE,  {RTQ, DQ, RAQ}},
+{"psq_l",      OP(56),         OP_MASK,     PPCPS,     PPCVLE,         {FRT,PSD,RA,PSW,PSQ}},
+{"lfq",                OP(56),         OP_MASK,     POWER2,    PPCVLE,         {FRT, D, RA0}},
 
-{"lxsd",       DSO(57,2),      DS_MASK,     PPCVSX3,   PPCNONE,        {VD, DS, RA0}},
-{"lxssp",      DSO(57,3),      DS_MASK,     PPCVSX3,   PPCNONE,        {VD, DS, RA0}},
-{"lfdp",       OP(57),         OP_MASK,     POWER6,    POWER7,         {FRTp, DS, RA0}},
-{"psq_lu",     OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
-{"lfqu",       OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
+{"lxsd",       DSO(57,2),      DS_MASK,     PPCVSX3,   PPCVLE,         {VD, DS, RA0}},
+{"lxssp",      DSO(57,3),      DS_MASK,     PPCVSX3,   PPCVLE,         {VD, DS, RA0}},
+{"lfdp",       OP(57),         OP_MASK,     POWER6,    POWER7|PPCVLE,  {FRTp, DS, RA0}},
+{"psq_lu",     OP(57),         OP_MASK,     PPCPS,     PPCVLE,         {FRT,PSD,RA,PSW,PSQ}},
+{"lfqu",       OP(57),         OP_MASK,     POWER2,    PPCVLE,         {FRT, D, RA0}},
 
-{"ld",         DSO(58,0),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
-{"ldu",                DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
-{"lwa",                DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
+{"ld",         DSO(58,0),      DS_MASK,     PPC64,     PPCVLE,         {RT, DS, RA0}},
+{"ldu",                DSO(58,1),      DS_MASK,     PPC64,     PPCVLE,         {RT, DS, RAL}},
+{"lwa",                DSO(58,2),      DS_MASK,     PPC64,     PPCVLE,         {RT, DS, RA0}},
 
-{"dadd",       XRC(59,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-{"dadd.",      XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
+{"dadd",       XRC(59,2,0),    X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
+{"dadd.",      XRC(59,2,1),    X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
 
-{"dqua",       ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
-{"dqua.",      ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
+{"dqua",       ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCVLE,         {FRT,FRA,FRB,RMC}},
+{"dqua.",      ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCVLE,         {FRT,FRA,FRB,RMC}},
 
-{"fdivs",      A(59,18,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
-{"fdivs.",     A(59,18,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
+{"fdivs",      A(59,18,0),     AFRC_MASK,   PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fdivs.",     A(59,18,1),     AFRC_MASK,   PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
 
-{"fsubs",      A(59,20,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
-{"fsubs.",     A(59,20,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
+{"fsubs",      A(59,20,0),     AFRC_MASK,   PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fsubs.",     A(59,20,1),     AFRC_MASK,   PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
 
-{"fadds",      A(59,21,0),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
-{"fadds.",     A(59,21,1),     AFRC_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRB}},
+{"fadds",      A(59,21,0),     AFRC_MASK,   PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fadds.",     A(59,21,1),     AFRC_MASK,   PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
 
-{"fsqrts",     A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
-{"fsqrts.",    A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
+{"fsqrts",     A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN|PPCVLE,   {FRT, FRB}},
+{"fsqrts.",    A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN|PPCVLE,   {FRT, FRB}},
 
-{"fres",       A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
-{"fres",       A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
-{"fres.",      A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
-{"fres.",      A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
+{"fres",       A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCVLE,         {FRT, FRB}},
+{"fres",       A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7|PPCVLE,  {FRT, FRB, A_L}},
+{"fres.",      A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCVLE,         {FRT, FRB}},
+{"fres.",      A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7|PPCVLE,  {FRT, FRB, A_L}},
 
-{"fmuls",      A(59,25,0),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
-{"fmuls.",     A(59,25,1),     AFRB_MASK,   PPC,       PPCEFS,         {FRT, FRA, FRC}},
+{"fmuls",      A(59,25,0),     AFRB_MASK,   PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC}},
+{"fmuls.",     A(59,25,1),     AFRB_MASK,   PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC}},
 
-{"frsqrtes",   A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
-{"frsqrtes",   A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
-{"frsqrtes.",  A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
-{"frsqrtes.",  A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
+{"frsqrtes",   A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCVLE,         {FRT, FRB}},
+{"frsqrtes",   A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7|PPCVLE,  {FRT, FRB, A_L}},
+{"frsqrtes.",  A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCVLE,         {FRT, FRB}},
+{"frsqrtes.",  A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7|PPCVLE,  {FRT, FRB, A_L}},
 
-{"fmsubs",     A(59,28,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fmsubs.",    A(59,28,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
+{"fmsubs",     A(59,28,0),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fmsubs.",    A(59,28,1),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
 
-{"fmadds",     A(59,29,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fmadds.",    A(59,29,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
+{"fmadds",     A(59,29,0),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fmadds.",    A(59,29,1),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
 
-{"fnmsubs",    A(59,30,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fnmsubs.",   A(59,30,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
+{"fnmsubs",    A(59,30,0),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fnmsubs.",   A(59,30,1),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
 
-{"fnmadds",    A(59,31,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fnmadds.",   A(59,31,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
+{"fnmadds",    A(59,31,0),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fnmadds.",   A(59,31,1),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
 
-{"dmul",       XRC(59,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-{"dmul.",      XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
+{"dmul",       XRC(59,34,0),   X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
+{"dmul.",      XRC(59,34,1),   X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
 
-{"drrnd",      ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
-{"drrnd.",     ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
+{"drrnd",      ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCVLE,         {FRT, FRA, FRB, RMC}},
+{"drrnd.",     ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCVLE,         {FRT, FRA, FRB, RMC}},
 
-{"dscli",      ZRC(59,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
-{"dscli.",     ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
+{"dscli",      ZRC(59,66,0),   Z_MASK,      POWER6,    PPCVLE,         {FRT, FRA, SH16}},
+{"dscli.",     ZRC(59,66,1),   Z_MASK,      POWER6,    PPCVLE,         {FRT, FRA, SH16}},
 
-{"dquai",      ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
-{"dquai.",     ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
+{"dquai",      ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCVLE,         {TE, FRT,FRB,RMC}},
+{"dquai.",     ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCVLE,         {TE, FRT,FRB,RMC}},
 
-{"dscri",      ZRC(59,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
-{"dscri.",     ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
+{"dscri",      ZRC(59,98,0),   Z_MASK,      POWER6,    PPCVLE,         {FRT, FRA, SH16}},
+{"dscri.",     ZRC(59,98,1),   Z_MASK,      POWER6,    PPCVLE,         {FRT, FRA, SH16}},
 
-{"drintx",     ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
-{"drintx.",    ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
+{"drintx",     ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCVLE,         {R, FRT, FRB, RMC}},
+{"drintx.",    ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCVLE,         {R, FRT, FRB, RMC}},
 
-{"dcmpo",      X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
+{"dcmpo",      X(59,130),      X_MASK,      POWER6,    PPCVLE,         {BF,  FRA, FRB}},
 
-{"dtstex",     X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
-{"dtstdc",     Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
-{"dtstdg",     Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
-
-{"drintn",     ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
-{"drintn.",    ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
-
-{"dctdp",      XRC(59,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
-{"dctdp.",     XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
-
-{"dctfix",     XRC(59,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
-{"dctfix.",    XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
-
-{"ddedpd",     XRC(59,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
-{"ddedpd.",    XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
-
-{"dxex",       XRC(59,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
-{"dxex.",      XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
-
-{"dsub",       XRC(59,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-{"dsub.",      XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-
-{"ddiv",       XRC(59,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-{"ddiv.",      XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-
-{"dcmpu",      X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
-
-{"dtstsf",     X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
-{"dtstsfi",    X(59,675),      X_MASK|1<<22,POWER9,    PPCNONE,        {BF, UIM6, FRB}},
-
-{"drsp",       XRC(59,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
-{"drsp.",      XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
-
-{"dcffix",     XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
-{"dcffix.",    XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
-
-{"denbcd",     XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
-{"denbcd.",    XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
-
-{"fcfids",     XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
-{"fcfids.",    XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
-
-{"diex",       XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-{"diex.",      XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
-
-{"fcfidus",    XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
-{"fcfidus.",   XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
-
-{"xsaddsp",    XX3(60,0),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsmaddasp",  XX3(60,1),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xxsldwi",    XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
-{"xscmpeqdp",  XX3(60,3),      XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsrsqrtesp", XX2(60,10),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
-{"xssqrtsp",   XX2(60,11),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
-{"xxsel",      XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
-{"xssubsp",    XX3(60,8),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsmaddmsp",  XX3(60,9),      XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xxspltd",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
-{"xxmrghd",    XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxswapd",    XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
-{"xxmrgld",    XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxpermdi",   XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
-{"xscmpgtdp",  XX3(60,11),     XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsresp",     XX2(60,26),     XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
-{"xsmulsp",    XX3(60,16),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsmsubasp",  XX3(60,17),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xxmrghw",    XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xscmpgedp",  XX3(60,19),     XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsdivsp",    XX3(60,24),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsmsubmsp",  XX3(60,25),     XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xxperm",     XX3(60,26),     XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsadddp",    XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsmaddadp",  XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xscmpudp",   XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
-{"xscvdpuxws", XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsrdpi",     XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsrsqrtedp", XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xssqrtdp",   XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xssubdp",    XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsmaddmdp",  XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xscmpodp",   XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
-{"xscvdpsxws", XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsrdpiz",    XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsredp",     XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsmuldp",    XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsmsubadp",  XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxmrglw",    XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsrdpip",    XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xstsqrtdp",  XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
-{"xsrdpic",    XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsdivdp",    XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsmsubmdp",  XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxpermr",    XX3(60,58),     XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xscmpexpdp", XX3(60,59),     XX3BF_MASK,  PPCVSX3,   PPCNONE,        {BF, XA6, XB6}},
-{"xsrdpim",    XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xstdivdp",   XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
-{"xvaddsp",    XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvmaddasp",  XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpeqsp",  XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvspuxws", XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrspi",     XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrsqrtesp", XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvsqrtsp",   XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvsubsp",    XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvmaddmsp",  XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpgtsp",  XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvspsxws", XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrspiz",    XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvresp",     XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvmulsp",    XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvmsubasp",  XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxspltw",    XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
-{"xxextractuw",        XX2(60,165),    XX2UIM4_MASK,PPCVSX3,   PPCNONE,        {XT6, XB6, UIMM4}},
-{"xvcmpgesp",  XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvuxwsp",  XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrspip",    XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvtsqrtsp",  XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
-{"xvrspic",    XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvdivsp",    XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvmsubmsp",  XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxspltib",   X(60,360),      XX1_MASK|3<<19, PPCVSX3,PPCNONE,        {XT6, IMM8}},
-{"xxinsertw",  XX2(60,181),    XX2UIM4_MASK,PPCVSX3,   PPCNONE,        {XT6, XB6, UIMM4}},
-{"xvcvsxwsp",  XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrspim",    XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvtdivsp",   XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
-{"xvadddp",    XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvmaddadp",  XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpeqdp",  XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvdpuxws", XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrdpi",     XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrsqrtedp", XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvsqrtdp",   XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvsubdp",    XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvmaddmdp",  XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpgtdp",  XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvdpsxws", XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrdpiz",    XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvredp",     XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvmuldp",    XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvmsubadp",  XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpgedp",  XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvuxwdp",  XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrdpip",    XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvtsqrtdp",  XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
-{"xvrdpic",    XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvdivdp",    XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvmsubmdp",  XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvsxwdp",  XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvrdpim",    XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvtdivdp",   XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
-{"xsmaxcdp",   XX3(60,128),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsnmaddasp", XX3(60,129),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xxland",     XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xscvdpsp",   XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xscvdpspn",  XX2(60,267),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
-{"xsmincdp",   XX3(60,136),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsnmaddmsp", XX3(60,137),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xxlandc",    XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsrsp",      XX2(60,281),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
-{"xsmaxjdp",   XX3(60,144),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsnmsubasp", XX3(60,145),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xxlor",      XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xscvuxdsp",  XX2(60,296),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
-{"xststdcsp",  XX2(60,298),    XX2BFD_MASK, PPCVSX3,   PPCNONE,        {BF, XB6, DCMX}},
-{"xsminjdp",   XX3(60,152),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xsnmsubmsp", XX3(60,153),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xxlxor",     XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xscvsxdsp",  XX2(60,312),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
-{"xsmaxdp",    XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsnmaddadp", XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxlnor",     XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xscvdpuxds", XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xscvspdp",   XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xscvspdpn",  XX2(60,331),    XX2_MASK,    PPCVSX2,   PPCNONE,        {XT6, XB6}},
-{"xsmindp",    XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsnmaddmdp", XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxlorc",     XX3(60,170),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xscvdpsxds", XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsabsdp",    XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsxexpdp",   XX2VA(60,347,0),XX2_MASK|1,  PPCVSX3,   PPCNONE,        {RT, XB6}},
-{"xsxsigdp",   XX2VA(60,347,1),XX2_MASK|1,  PPCVSX3,   PPCNONE,        {RT, XB6}},
-{"xscvhpdp",   XX2VA(60,347,16),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xscvdphp",   XX2VA(60,347,17),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xscpsgndp",  XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xsnmsubadp", XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxlnand",    XX3(60,178),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xscvuxddp",  XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsnabsdp",   XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xststdcdp",  XX2(60,362),    XX2BFD_MASK, PPCVSX3,   PPCNONE,        {BF, XB6, DCMX}},
-{"xsnmsubmdp", XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xxleqv",     XX3(60,186),    XX3_MASK,    PPCVSX2,   PPCNONE,        {XT6, XA6, XB6}},
-{"xscvsxddp",  XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsnegdp",    XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvmaxsp",    XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvnmaddasp", XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvspuxds", XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvcvdpsp",   XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvminsp",    XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvnmaddmsp", XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvspsxds", XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvabssp",    XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvmovsp",    XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
-{"xvcpsgnsp",  XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvnmsubasp", XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvuxdsp",  XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvnabssp",   XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvtstdcsp",  XX2(60,426),    XX2DCMXS_MASK,PPCVSX3,  PPCNONE,        {XT6, XB6, DCMXS}},
-{"xviexpsp",   XX3(60,216),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xvnmsubmsp", XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvsxdsp",  XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvnegsp",    XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvmaxdp",    XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvnmaddadp", XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvdpuxds", XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvcvspdp",   XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xsiexpdp",   X(60,918),      XX1_MASK,    PPCVSX3,   PPCNONE,        {XT6, RA, RB}},
-{"xvmindp",    XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvnmaddmdp", XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvdpsxds", XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvabsdp",    XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvxexpdp",   XX2VA(60,475,0),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xvxsigdp",   XX2VA(60,475,1),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xxbrh",      XX2VA(60,475,7),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xvxexpsp",   XX2VA(60,475,8),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xvxsigsp",   XX2VA(60,475,9),XX2_MASK,    PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xxbrw",      XX2VA(60,475,15),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xxbrd",      XX2VA(60,475,23),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xvcvhpsp",   XX2VA(60,475,24),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xvcvsphp",   XX2VA(60,475,25),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xxbrq",      XX2VA(60,475,31),XX2_MASK,   PPCVSX3,   PPCNONE,        {XT6, XB6}},
-{"xvmovdp",    XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
-{"xvcpsgndp",  XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvnmsubadp", XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvuxddp",  XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvnabsdp",   XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvtstdcdp",  XX2(60,490),    XX2DCMXS_MASK,PPCVSX3,  PPCNONE,        {XT6, XB6, DCMXS}},
-{"xviexpdp",   XX3(60,248),    XX3_MASK,    PPCVSX3,   PPCNONE,        {XT6, XA6, XB6}},
-{"xvnmsubmdp", XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
-{"xvcvsxddp",  XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-{"xvnegdp",    XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
-
-{"psq_st",     OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
-{"stfq",       OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
-
-{"lxv",                DQX(61,1),      DQX_MASK,    PPCVSX3,   PPCNONE,        {XTQ6, DQ, RA0}},
-{"stxv",       DQX(61,5),      DQX_MASK,    PPCVSX3,   PPCNONE,        {XSQ6, DQ, RA0}},
-{"stxsd",      DSO(61,2),      DS_MASK,     PPCVSX3,   PPCNONE,        {VS, DS, RA0}},
-{"stxssp",     DSO(61,3),      DS_MASK,     PPCVSX3,   PPCNONE,        {VS, DS, RA0}},
-{"stfdp",      OP(61),         OP_MASK,     POWER6,    POWER7,         {FRSp, DS, RA0}},
-{"psq_stu",    OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
-{"stfqu",      OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
-
-{"std",                DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
-{"stdu",       DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
-{"stq",                DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
-
-{"fcmpu",      X(63,0),        XBF_MASK,    COM,       PPCEFS,         {BF, FRA, FRB}},
-
-{"daddq",      XRC(63,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
-{"daddq.",     XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
-
-{"dquaq",      ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
-{"dquaq.",     ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRAp, FRBp, RMC}},
-
-{"xsaddqp",    XRC(63,4,0),    X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-{"xsaddqpo",   XRC(63,4,1),    X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-
-{"xsrqpi",     ZRC(63,5,0),    Z2_MASK,     PPCVSX3,   PPCNONE,        {R, VD, VB, RMC}},
-{"xsrqpix",    ZRC(63,5,1),    Z2_MASK,     PPCVSX3,   PPCNONE,        {R, VD, VB, RMC}},
-
-{"fcpsgn",     XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
-{"fcpsgn.",    XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
-
-{"frsp",       XRC(63,12,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
-{"frsp.",      XRC(63,12,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
-
-{"fctiw",      XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
-{"fcir",       XRC(63,14,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
-{"fctiw.",     XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
-{"fcir.",      XRC(63,14,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
-
-{"fctiwz",     XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
-{"fcirz",      XRC(63,15,0),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
-{"fctiwz.",    XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS,         {FRT, FRB}},
-{"fcirz.",     XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCNONE,        {FRT, FRB}},
-
-{"fdiv",       A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
-{"fd",         A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
-{"fdiv.",      A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
-{"fd.",                A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
-
-{"fsub",       A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
-{"fs",         A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
-{"fsub.",      A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
-{"fs.",                A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
-
-{"fadd",       A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
-{"fa",         A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
-{"fadd.",      A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRB}},
-{"fa.",                A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
-
-{"fsqrt",      A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
-{"fsqrt.",     A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
-
-{"fsel",       A(63,23,0),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fsel.",      A(63,23,1),     A_MASK,      PPC,       PPCEFS,         {FRT, FRA, FRC, FRB}},
-
-{"fre",                A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
-{"fre",                A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
-{"fre.",       A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
-{"fre.",       A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
+{"dtstex",     X(59,162),      X_MASK,      POWER6,    PPCVLE,         {BF,  FRA, FRB}},
+{"dtstdc",     Z(59,194),      Z_MASK,      POWER6,    PPCVLE,         {BF,  FRA, DCM}},
+{"dtstdg",     Z(59,226),      Z_MASK,      POWER6,    PPCVLE,         {BF,  FRA, DGM}},
+
+{"drintn",     ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCVLE,         {R, FRT, FRB, RMC}},
+{"drintn.",    ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCVLE,         {R, FRT, FRB, RMC}},
+
+{"dctdp",      XRC(59,258,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
+{"dctdp.",     XRC(59,258,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
+
+{"dctfix",     XRC(59,290,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
+{"dctfix.",    XRC(59,290,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
+
+{"ddedpd",     XRC(59,322,0),  X_MASK,      POWER6,    PPCVLE,         {SP, FRT, FRB}},
+{"ddedpd.",    XRC(59,322,1),  X_MASK,      POWER6,    PPCVLE,         {SP, FRT, FRB}},
+
+{"dxex",       XRC(59,354,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
+{"dxex.",      XRC(59,354,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
+
+{"dsub",       XRC(59,514,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
+{"dsub.",      XRC(59,514,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
+
+{"ddiv",       XRC(59,546,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
+{"ddiv.",      XRC(59,546,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
+
+{"dcmpu",      X(59,642),      X_MASK,      POWER6,    PPCVLE,         {BF,  FRA, FRB}},
+
+{"dtstsf",     X(59,674),      X_MASK,      POWER6,    PPCVLE,         {BF,  FRA, FRB}},
+{"dtstsfi",    X(59,675),      X_MASK|1<<22,POWER9,    PPCVLE,         {BF, UIM6, FRB}},
+
+{"drsp",       XRC(59,770,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
+{"drsp.",      XRC(59,770,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
+
+{"dcffix",     XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE,         {FRT, FRB}},
+{"dcffix.",    XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE,         {FRT, FRB}},
+
+{"denbcd",     XRC(59,834,0),  X_MASK,      POWER6,    PPCVLE,         {S, FRT, FRB}},
+{"denbcd.",    XRC(59,834,1),  X_MASK,      POWER6,    PPCVLE,         {S, FRT, FRB}},
+
+{"fcfids",     XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
+{"fcfids.",    XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
+
+{"diex",       XRC(59,866,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
+{"diex.",      XRC(59,866,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRA, FRB}},
+
+{"fcfidus",    XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
+{"fcfidus.",   XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
+
+{"xsaddsp",    XX3(60,0),      XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsmaddasp",  XX3(60,1),      XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xxsldwi",    XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCVLE,         {XT6, XA6, XB6, SHW}},
+{"xscmpeqdp",  XX3(60,3),      XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsrsqrtesp", XX2(60,10),     XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
+{"xssqrtsp",   XX2(60,11),     XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
+{"xxsel",      XX4(60,3),      XX4_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6, XC6}},
+{"xssubsp",    XX3(60,8),      XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsmaddmsp",  XX3(60,9),      XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xxspltd",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCVLE,         {XT6, XA6, XB6S, DMEX}},
+{"xxmrghd",    XX3(60,10),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxswapd",    XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCVLE,         {XT6, XA6, XB6S}},
+{"xxmrgld",    XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxpermdi",   XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCVLE,         {XT6, XA6, XB6, DM}},
+{"xscmpgtdp",  XX3(60,11),     XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsresp",     XX2(60,26),     XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
+{"xsmulsp",    XX3(60,16),     XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsmsubasp",  XX3(60,17),     XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xxmrghw",    XX3(60,18),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xscmpgedp",  XX3(60,19),     XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsdivsp",    XX3(60,24),     XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsmsubmsp",  XX3(60,25),     XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xxperm",     XX3(60,26),     XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsadddp",    XX3(60,32),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsmaddadp",  XX3(60,33),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xscmpudp",   XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCVLE,         {BF, XA6, XB6}},
+{"xscvdpuxws", XX2(60,72),     XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsrdpi",     XX2(60,73),     XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsrsqrtedp", XX2(60,74),     XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xssqrtdp",   XX2(60,75),     XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xssubdp",    XX3(60,40),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsmaddmdp",  XX3(60,41),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xscmpodp",   XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCVLE,         {BF, XA6, XB6}},
+{"xscvdpsxws", XX2(60,88),     XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsrdpiz",    XX2(60,89),     XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsredp",     XX2(60,90),     XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsmuldp",    XX3(60,48),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsmsubadp",  XX3(60,49),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxmrglw",    XX3(60,50),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsrdpip",    XX2(60,105),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xstsqrtdp",  XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCVLE,         {BF, XB6}},
+{"xsrdpic",    XX2(60,107),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsdivdp",    XX3(60,56),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsmsubmdp",  XX3(60,57),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxpermr",    XX3(60,58),     XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xscmpexpdp", XX3(60,59),     XX3BF_MASK,  PPCVSX3,   PPCVLE,         {BF, XA6, XB6}},
+{"xsrdpim",    XX2(60,121),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xstdivdp",   XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCVLE,         {BF, XA6, XB6}},
+{"xvaddsp",    XX3(60,64),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmaddasp",  XX3(60,65),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpeqsp",  XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvspuxws", XX2(60,136),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrspi",     XX2(60,137),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrsqrtesp", XX2(60,138),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvsqrtsp",   XX2(60,139),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvsubsp",    XX3(60,72),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmaddmsp",  XX3(60,73),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpgtsp",  XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvspsxws", XX2(60,152),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrspiz",    XX2(60,153),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvresp",     XX2(60,154),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvmulsp",    XX3(60,80),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmsubasp",  XX3(60,81),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxspltw",    XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCVLE,         {XT6, XB6, UIM}},
+{"xxextractuw",        XX2(60,165),   XX2UIM4_MASK, PPCVSX3,   PPCVLE,         {XT6, XB6, UIMM4}},
+{"xvcmpgesp",  XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvuxwsp",  XX2(60,168),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrspip",    XX2(60,169),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvtsqrtsp",  XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCVLE,         {BF, XB6}},
+{"xvrspic",    XX2(60,171),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvdivsp",    XX3(60,88),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmsubmsp",  XX3(60,89),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxspltib",   X(60,360),   XX1_MASK|3<<19, PPCVSX3,   PPCVLE,         {XT6, IMM8}},
+{"xxinsertw",  XX2(60,181),   XX2UIM4_MASK, PPCVSX3,   PPCVLE,         {XT6, XB6, UIMM4}},
+{"xvcvsxwsp",  XX2(60,184),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrspim",    XX2(60,185),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvtdivsp",   XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCVLE,         {BF, XA6, XB6}},
+{"xvadddp",    XX3(60,96),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmaddadp",  XX3(60,97),     XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpeqdp",  XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvdpuxws", XX2(60,200),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrdpi",     XX2(60,201),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrsqrtedp", XX2(60,202),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvsqrtdp",   XX2(60,203),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvsubdp",    XX3(60,104),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmaddmdp",  XX3(60,105),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpgtdp",  XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvdpsxws", XX2(60,216),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrdpiz",    XX2(60,217),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvredp",     XX2(60,218),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvmuldp",    XX3(60,112),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmsubadp",  XX3(60,113),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpgedp",  XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvuxwdp",  XX2(60,232),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrdpip",    XX2(60,233),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvtsqrtdp",  XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCVLE,         {BF, XB6}},
+{"xvrdpic",    XX2(60,235),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvdivdp",    XX3(60,120),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvmsubmdp",  XX3(60,121),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvsxwdp",  XX2(60,248),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvrdpim",    XX2(60,249),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvtdivdp",   XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCVLE,         {BF, XA6, XB6}},
+{"xsmaxcdp",   XX3(60,128),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsnmaddasp", XX3(60,129),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xxland",     XX3(60,130),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xscvdpsp",   XX2(60,265),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xscvdpspn",  XX2(60,267),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
+{"xsmincdp",   XX3(60,136),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsnmaddmsp", XX3(60,137),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xxlandc",    XX3(60,138),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsrsp",      XX2(60,281),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
+{"xsmaxjdp",   XX3(60,144),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsnmsubasp", XX3(60,145),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xxlor",      XX3(60,146),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xscvuxdsp",  XX2(60,296),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
+{"xststdcsp",  XX2(60,298),    XX2BFD_MASK, PPCVSX3,   PPCVLE,         {BF, XB6, DCMX}},
+{"xsminjdp",   XX3(60,152),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xsnmsubmsp", XX3(60,153),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xxlxor",     XX3(60,154),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xscvsxdsp",  XX2(60,312),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
+{"xsmaxdp",    XX3(60,160),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsnmaddadp", XX3(60,161),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxlnor",     XX3(60,162),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xscvdpuxds", XX2(60,328),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xscvspdp",   XX2(60,329),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xscvspdpn",  XX2(60,331),    XX2_MASK,    PPCVSX2,   PPCVLE,         {XT6, XB6}},
+{"xsmindp",    XX3(60,168),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsnmaddmdp", XX3(60,169),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxlorc",     XX3(60,170),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xscvdpsxds", XX2(60,344),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsabsdp",    XX2(60,345),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsxexpdp",   XX2VA(60,347,0),XX2_MASK|1,  PPCVSX3,   PPCVLE,         {RT, XB6}},
+{"xsxsigdp",   XX2VA(60,347,1),XX2_MASK|1,  PPCVSX3,   PPCVLE,         {RT, XB6}},
+{"xscvhpdp",   XX2VA(60,347,16),XX2_MASK,   PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xscvdphp",   XX2VA(60,347,17),XX2_MASK,   PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xscpsgndp",  XX3(60,176),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xsnmsubadp", XX3(60,177),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxlnand",    XX3(60,178),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xscvuxddp",  XX2(60,360),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsnabsdp",   XX2(60,361),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xststdcdp",  XX2(60,362),    XX2BFD_MASK, PPCVSX3,   PPCVLE,         {BF, XB6, DCMX}},
+{"xsnmsubmdp", XX3(60,185),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xxleqv",     XX3(60,186),    XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
+{"xscvsxddp",  XX2(60,376),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsnegdp",    XX2(60,377),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvmaxsp",    XX3(60,192),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvnmaddasp", XX3(60,193),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvspuxds", XX2(60,392),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvcvdpsp",   XX2(60,393),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvminsp",    XX3(60,200),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvnmaddmsp", XX3(60,201),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvspsxds", XX2(60,408),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvabssp",    XX2(60,409),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvmovsp",    XX3(60,208),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6S}},
+{"xvcpsgnsp",  XX3(60,208),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvnmsubasp", XX3(60,209),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvuxdsp",  XX2(60,424),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvnabssp",   XX2(60,425),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvtstdcsp",  XX2(60,426),  XX2DCMXS_MASK, PPCVSX3,   PPCVLE,         {XT6, XB6, DCMXS}},
+{"xviexpsp",   XX3(60,216),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xvnmsubmsp", XX3(60,217),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvsxdsp",  XX2(60,440),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvnegsp",    XX2(60,441),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvmaxdp",    XX3(60,224),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvnmaddadp", XX3(60,225),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvdpuxds", XX2(60,456),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvcvspdp",   XX2(60,457),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xsiexpdp",   X(60,918),      XX1_MASK,    PPCVSX3,   PPCVLE,         {XT6, RA, RB}},
+{"xvmindp",    XX3(60,232),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvnmaddmdp", XX3(60,233),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvdpsxds", XX2(60,472),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvabsdp",    XX2(60,473),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvxexpdp",   XX2VA(60,475,0),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xvxsigdp",   XX2VA(60,475,1),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xxbrh",      XX2VA(60,475,7),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xvxexpsp",   XX2VA(60,475,8),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xvxsigsp",   XX2VA(60,475,9),XX2_MASK,    PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xxbrw",      XX2VA(60,475,15),XX2_MASK,   PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xxbrd",      XX2VA(60,475,23),XX2_MASK,   PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xvcvhpsp",   XX2VA(60,475,24),XX2_MASK,   PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xvcvsphp",   XX2VA(60,475,25),XX2_MASK,   PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xxbrq",      XX2VA(60,475,31),XX2_MASK,   PPCVSX3,   PPCVLE,         {XT6, XB6}},
+{"xvmovdp",    XX3(60,240),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6S}},
+{"xvcpsgndp",  XX3(60,240),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvnmsubadp", XX3(60,241),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvuxddp",  XX2(60,488),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvnabsdp",   XX2(60,489),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvtstdcdp",  XX2(60,490),  XX2DCMXS_MASK, PPCVSX3,   PPCVLE,         {XT6, XB6, DCMXS}},
+{"xviexpdp",   XX3(60,248),    XX3_MASK,    PPCVSX3,   PPCVLE,         {XT6, XA6, XB6}},
+{"xvnmsubmdp", XX3(60,249),    XX3_MASK,    PPCVSX,    PPCVLE,         {XT6, XA6, XB6}},
+{"xvcvsxddp",  XX2(60,504),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+{"xvnegdp",    XX2(60,505),    XX2_MASK,    PPCVSX,    PPCVLE,         {XT6, XB6}},
+
+{"psq_st",     OP(60),         OP_MASK,     PPCPS,     PPCVLE,         {FRS,PSD,RA,PSW,PSQ}},
+{"stfq",       OP(60),         OP_MASK,     POWER2,    PPCVLE,         {FRS, D, RA}},
+
+{"lxv",                DQX(61,1),      DQX_MASK,    PPCVSX3,   PPCVLE,         {XTQ6, DQ, RA0}},
+{"stxv",       DQX(61,5),      DQX_MASK,    PPCVSX3,   PPCVLE,         {XSQ6, DQ, RA0}},
+{"stxsd",      DSO(61,2),      DS_MASK,     PPCVSX3,   PPCVLE,         {VS, DS, RA0}},
+{"stxssp",     DSO(61,3),      DS_MASK,     PPCVSX3,   PPCVLE,         {VS, DS, RA0}},
+{"stfdp",      OP(61),         OP_MASK,     POWER6,    POWER7|PPCVLE,  {FRSp, DS, RA0}},
+{"psq_stu",    OP(61),         OP_MASK,     PPCPS,     PPCVLE,         {FRS,PSD,RA,PSW,PSQ}},
+{"stfqu",      OP(61),         OP_MASK,     POWER2,    PPCVLE,         {FRS, D, RA}},
+
+{"std",                DSO(62,0),      DS_MASK,     PPC64,     PPCVLE,         {RS, DS, RA0}},
+{"stdu",       DSO(62,1),      DS_MASK,     PPC64,     PPCVLE,         {RS, DS, RAS}},
+{"stq",                DSO(62,2),      DS_MASK,     POWER4,    PPC476|PPCVLE,  {RSQ, DS, RA0}},
+
+{"fcmpu",      X(63,0),        XBF_MASK,    COM,       PPCEFS|PPCVLE,  {BF, FRA, FRB}},
+
+{"daddq",      XRC(63,2,0),    X_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, FRBp}},
+{"daddq.",     XRC(63,2,1),    X_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, FRBp}},
+
+{"dquaq",      ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCVLE,         {FRTp, FRAp, FRBp, RMC}},
+{"dquaq.",     ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCVLE,         {FRTp, FRAp, FRBp, RMC}},
+
+{"xsaddqp",    XRC(63,4,0),    X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+{"xsaddqpo",   XRC(63,4,1),    X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+
+{"xsrqpi",     ZRC(63,5,0),    Z2_MASK,     PPCVSX3,   PPCVLE,         {R, VD, VB, RMC}},
+{"xsrqpix",    ZRC(63,5,1),    Z2_MASK,     PPCVSX3,   PPCVLE,         {R, VD, VB, RMC}},
+
+{"fcpsgn",     XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCVLE,    {FRT, FRA, FRB}},
+{"fcpsgn.",    XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCVLE,    {FRT, FRA, FRB}},
+
+{"frsp",       XRC(63,12,0),   XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
+{"frsp.",      XRC(63,12,1),   XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
+
+{"fctiw",      XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRB}},
+{"fcir",       XRC(63,14,0),   XRA_MASK,    PWR2COM,   PPCVLE,         {FRT, FRB}},
+{"fctiw.",     XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRB}},
+{"fcir.",      XRC(63,14,1),   XRA_MASK,    PWR2COM,   PPCVLE,         {FRT, FRB}},
+
+{"fctiwz",     XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRB}},
+{"fcirz",      XRC(63,15,0),   XRA_MASK,    PWR2COM,   PPCVLE,         {FRT, FRB}},
+{"fctiwz.",    XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRB}},
+{"fcirz.",     XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCVLE,         {FRT, FRB}},
+
+{"fdiv",       A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fd",         A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCVLE,         {FRT, FRA, FRB}},
+{"fdiv.",      A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fd.",                A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCVLE,         {FRT, FRA, FRB}},
+
+{"fsub",       A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fs",         A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCVLE,         {FRT, FRA, FRB}},
+{"fsub.",      A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fs.",                A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCVLE,         {FRT, FRA, FRB}},
+
+{"fadd",       A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fa",         A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCVLE,         {FRT, FRA, FRB}},
+{"fadd.",      A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
+{"fa.",                A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCVLE,         {FRT, FRA, FRB}},
+
+{"fsqrt",      A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN|PPCVLE,   {FRT, FRB}},
+{"fsqrt.",     A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN|PPCVLE,   {FRT, FRB}},
+
+{"fsel",       A(63,23,0),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fsel.",      A(63,23,1),     A_MASK,      PPC,       PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+
+{"fre",                A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCVLE,         {FRT, FRB}},
+{"fre",                A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7|PPCVLE,  {FRT, FRB, A_L}},
+{"fre.",       A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCVLE,         {FRT, FRB}},
+{"fre.",       A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7|PPCVLE,  {FRT, FRB, A_L}},
 
-{"fmul",       A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
-{"fm",         A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
-{"fmul.",      A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCEFS,         {FRT, FRA, FRC}},
-{"fm.",                A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
+{"fmul",       A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC}},
+{"fm",         A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCVLE|PPCVLE,  {FRT, FRA, FRC}},
+{"fmul.",      A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC}},
+{"fm.",                A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCVLE|PPCVLE,  {FRT, FRA, FRC}},
 
-{"frsqrte",    A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
-{"frsqrte",    A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
-{"frsqrte.",   A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
-{"frsqrte.",   A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
+{"frsqrte",    A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCVLE,         {FRT, FRB}},
+{"frsqrte",    A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7|PPCVLE,  {FRT, FRB, A_L}},
+{"frsqrte.",   A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCVLE,         {FRT, FRB}},
+{"frsqrte.",   A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7|PPCVLE,  {FRT, FRB, A_L}},
 
-{"fmsub",      A(63,28,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fms",                A(63,28,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"fmsub.",     A(63,28,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fms.",       A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
+{"fmsub",      A(63,28,0),     A_MASK,      PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fms",                A(63,28,0),     A_MASK,      PWRCOM,    PPCVLE,         {FRT, FRA, FRC, FRB}},
+{"fmsub.",     A(63,28,1),     A_MASK,      PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fms.",       A(63,28,1),     A_MASK,      PWRCOM,    PPCVLE,         {FRT, FRA, FRC, FRB}},
 
-{"fmadd",      A(63,29,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fma",                A(63,29,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"fmadd.",     A(63,29,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fma.",       A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
+{"fmadd",      A(63,29,0),     A_MASK,      PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fma",                A(63,29,0),     A_MASK,      PWRCOM,    PPCVLE,         {FRT, FRA, FRC, FRB}},
+{"fmadd.",     A(63,29,1),     A_MASK,      PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fma.",       A(63,29,1),     A_MASK,      PWRCOM,    PPCVLE,         {FRT, FRA, FRC, FRB}},
 
-{"fnmsub",     A(63,30,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fnms",       A(63,30,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"fnmsub.",    A(63,30,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fnms.",      A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
+{"fnmsub",     A(63,30,0),     A_MASK,      PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fnms",       A(63,30,0),     A_MASK,      PWRCOM,    PPCVLE,         {FRT, FRA, FRC, FRB}},
+{"fnmsub.",    A(63,30,1),     A_MASK,      PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fnms.",      A(63,30,1),     A_MASK,      PWRCOM,    PPCVLE,         {FRT, FRA, FRC, FRB}},
 
-{"fnmadd",     A(63,31,0),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fnma",       A(63,31,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
-{"fnmadd.",    A(63,31,1),     A_MASK,      PPCCOM,    PPCEFS,         {FRT, FRA, FRC, FRB}},
-{"fnma.",      A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
+{"fnmadd",     A(63,31,0),     A_MASK,      PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fnma",       A(63,31,0),     A_MASK,      PWRCOM,    PPCVLE,         {FRT, FRA, FRC, FRB}},
+{"fnmadd.",    A(63,31,1),     A_MASK,      PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRC, FRB}},
+{"fnma.",      A(63,31,1),     A_MASK,      PWRCOM,    PPCVLE,         {FRT, FRA, FRC, FRB}},
 
-{"fcmpo",      X(63,32),       XBF_MASK,    COM,       PPCEFS,         {BF, FRA, FRB}},
+{"fcmpo",      X(63,32),       XBF_MASK,    COM,       PPCEFS|PPCVLE,  {BF, FRA, FRB}},
 
-{"dmulq",      XRC(63,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
-{"dmulq.",     XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
+{"dmulq",      XRC(63,34,0),   X_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, FRBp}},
+{"dmulq.",     XRC(63,34,1),   X_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, FRBp}},
 
-{"drrndq",     ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
-{"drrndq.",    ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRTp, FRA, FRBp, RMC}},
+{"drrndq",     ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCVLE,         {FRTp, FRA, FRBp, RMC}},
+{"drrndq.",    ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCVLE,         {FRTp, FRA, FRBp, RMC}},
 
-{"xsmulqp",    XRC(63,36,0),   X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-{"xsmulqpo",   XRC(63,36,1),   X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xsmulqp",    XRC(63,36,0),   X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+{"xsmulqpo",   XRC(63,36,1),   X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"xsrqpxp",    Z(63,37),       Z2_MASK,     PPCVSX3,   PPCNONE,        {R, VD, VB, RMC}},
+{"xsrqpxp",    Z(63,37),       Z2_MASK,     PPCVSX3,   PPCVLE,         {R, VD, VB, RMC}},
 
-{"mtfsb1",     XRC(63,38,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
-{"mtfsb1.",    XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
+{"mtfsb1",     XRC(63,38,0),   XRARB_MASK,  COM,       PPCVLE,         {BT}},
+{"mtfsb1.",    XRC(63,38,1),   XRARB_MASK,  COM,       PPCVLE,         {BT}},
 
-{"fneg",       XRC(63,40,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
-{"fneg.",      XRC(63,40,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
+{"fneg",       XRC(63,40,0),   XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
+{"fneg.",      XRC(63,40,1),   XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
 
-{"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM,        PPCNONE,        {BF, BFA}},
+{"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM,        PPCVLE,         {BF, BFA}},
 
-{"dscliq",     ZRC(63,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
-{"dscliq.",    ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
+{"dscliq",     ZRC(63,66,0),   Z_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, SH16}},
+{"dscliq.",    ZRC(63,66,1),   Z_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, SH16}},
 
-{"dquaiq",     ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
-{"dquaiq.",    ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRTp, FRBp, RMC}},
+{"dquaiq",     ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCVLE,         {TE, FRTp, FRBp, RMC}},
+{"dquaiq.",    ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCVLE,         {TE, FRTp, FRBp, RMC}},
 
-{"mtfsb0",     XRC(63,70,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
-{"mtfsb0.",    XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
+{"mtfsb0",     XRC(63,70,0),   XRARB_MASK,  COM,       PPCVLE,         {BT}},
+{"mtfsb0.",    XRC(63,70,1),   XRARB_MASK,  COM,       PPCVLE,         {BT}},
 
-{"fmr",                XRC(63,72,0),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
-{"fmr.",       XRC(63,72,1),   XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
+{"fmr",                XRC(63,72,0),   XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
+{"fmr.",       XRC(63,72,1),   XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
 
-{"dscriq",     ZRC(63,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
-{"dscriq.",    ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, SH16}},
+{"dscriq",     ZRC(63,98,0),   Z_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, SH16}},
+{"dscriq.",    ZRC(63,98,1),   Z_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, SH16}},
 
-{"drintxq",    ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
-{"drintxq.",   ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
+{"drintxq",    ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCVLE,         {R, FRTp, FRBp, RMC}},
+{"drintxq.",   ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCVLE,         {R, FRTp, FRBp, RMC}},
 
-{"xscpsgnqp",  X(63,100),      X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xscpsgnqp",  X(63,100),      X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"ftdiv",      X(63,128),      XBF_MASK,    POWER7,    PPCNONE,        {BF, FRA, FRB}},
+{"ftdiv",      X(63,128),      XBF_MASK,    POWER7,    PPCVLE,         {BF, FRA, FRB}},
 
-{"dcmpoq",     X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
+{"dcmpoq",     X(63,130),      X_MASK,      POWER6,    PPCVLE,         {BF, FRAp, FRBp}},
 
-{"xscmpoqp",   X(63,132),      XBF_MASK,    PPCVSX3,   PPCNONE,        {BF, VA, VB}},
+{"xscmpoqp",   X(63,132),      XBF_MASK,    PPCVSX3,   PPCVLE,         {BF, VA, VB}},
 
-{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
-{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
-{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
-{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
+{"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
+{"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
+{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
+{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
 
-{"fnabs",      XRC(63,136,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
-{"fnabs.",     XRC(63,136,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
+{"fnabs",      XRC(63,136,0),  XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
+{"fnabs.",     XRC(63,136,1),  XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
 
-{"fctiwu",     XRC(63,142,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
-{"fctiwu.",    XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
-{"fctiwuz",    XRC(63,143,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
-{"fctiwuz.",   XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
+{"fctiwu",     XRC(63,142,0),  XRA_MASK,    POWER7,    PPCVLE,         {FRT, FRB}},
+{"fctiwu.",    XRC(63,142,1),  XRA_MASK,    POWER7,    PPCVLE,         {FRT, FRB}},
+{"fctiwuz",    XRC(63,143,0),  XRA_MASK,    POWER7,    PPCVLE,         {FRT, FRB}},
+{"fctiwuz.",   XRC(63,143,1),  XRA_MASK,    POWER7,    PPCVLE,         {FRT, FRB}},
 
-{"ftsqrt",     X(63,160),      XBF_MASK|FRA_MASK, POWER7, PPCNONE,     {BF, FRB}},
+{"ftsqrt",     X(63,160),      XBF_MASK|FRA_MASK, POWER7, PPCVLE,      {BF, FRB}},
 
-{"dtstexq",    X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
+{"dtstexq",    X(63,162),      X_MASK,      POWER6,    PPCVLE,         {BF, FRAp, FRBp}},
 
-{"xscmpexpqp", X(63,164),      XBF_MASK,    PPCVSX3,   PPCNONE,        {BF, VA, VB}},
+{"xscmpexpqp", X(63,164),      XBF_MASK,    PPCVSX3,   PPCVLE,         {BF, VA, VB}},
 
-{"dtstdcq",    Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DCM}},
-{"dtstdgq",    Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRAp, DGM}},
+{"dtstdcq",    Z(63,194),      Z_MASK,      POWER6,    PPCVLE,         {BF, FRAp, DCM}},
+{"dtstdgq",    Z(63,226),      Z_MASK,      POWER6,    PPCVLE,         {BF, FRAp, DGM}},
 
-{"drintnq",    ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
-{"drintnq.",   ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRTp, FRBp, RMC}},
+{"drintnq",    ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCVLE,         {R, FRTp, FRBp, RMC}},
+{"drintnq.",   ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCVLE,         {R, FRTp, FRBp, RMC}},
 
-{"dctqpq",     XRC(63,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
-{"dctqpq.",    XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
+{"dctqpq",     XRC(63,258,0),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRB}},
+{"dctqpq.",    XRC(63,258,1),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRB}},
 
-{"fabs",       XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
-{"fabs.",      XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS,         {FRT, FRB}},
+{"fabs",       XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
+{"fabs.",      XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
 
-{"dctfixq",    XRC(63,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
-{"dctfixq.",   XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
+{"dctfixq",    XRC(63,290,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRBp}},
+{"dctfixq.",   XRC(63,290,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRBp}},
 
-{"ddedpdq",    XRC(63,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
-{"ddedpdq.",   XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRTp, FRBp}},
+{"ddedpdq",    XRC(63,322,0),  X_MASK,      POWER6,    PPCVLE,         {SP, FRTp, FRBp}},
+{"ddedpdq.",   XRC(63,322,1),  X_MASK,      POWER6,    PPCVLE,         {SP, FRTp, FRBp}},
 
-{"dxexq",      XRC(63,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
-{"dxexq.",     XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRBp}},
+{"dxexq",      XRC(63,354,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRBp}},
+{"dxexq.",     XRC(63,354,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRBp}},
 
-{"xsmaddqp",   XRC(63,388,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-{"xsmaddqpo",  XRC(63,388,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xsmaddqp",   XRC(63,388,0),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+{"xsmaddqpo",  XRC(63,388,1),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"frin",       XRC(63,392,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
-{"frin.",      XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
+{"frin",       XRC(63,392,0),  XRA_MASK,    POWER5,    PPCVLE,         {FRT, FRB}},
+{"frin.",      XRC(63,392,1),  XRA_MASK,    POWER5,    PPCVLE,         {FRT, FRB}},
 
-{"xsmsubqp",   XRC(63,420,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-{"xsmsubqpo",  XRC(63,420,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xsmsubqp",   XRC(63,420,0),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+{"xsmsubqpo",  XRC(63,420,1),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"friz",       XRC(63,424,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
-{"friz.",      XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
+{"friz",       XRC(63,424,0),  XRA_MASK,    POWER5,    PPCVLE,         {FRT, FRB}},
+{"friz.",      XRC(63,424,1),  XRA_MASK,    POWER5,    PPCVLE,         {FRT, FRB}},
 
-{"xsnmaddqp",  XRC(63,452,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-{"xsnmaddqpo", XRC(63,452,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xsnmaddqp",  XRC(63,452,0),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+{"xsnmaddqpo", XRC(63,452,1),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"frip",       XRC(63,456,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
-{"frip.",      XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
+{"frip",       XRC(63,456,0),  XRA_MASK,    POWER5,    PPCVLE,         {FRT, FRB}},
+{"frip.",      XRC(63,456,1),  XRA_MASK,    POWER5,    PPCVLE,         {FRT, FRB}},
 
-{"xsnmsubqp",  XRC(63,484,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-{"xsnmsubqpo", XRC(63,484,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xsnmsubqp",  XRC(63,484,0),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+{"xsnmsubqpo", XRC(63,484,1),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"frim",       XRC(63,488,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
-{"frim.",      XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
+{"frim",       XRC(63,488,0),  XRA_MASK,    POWER5,    PPCVLE,         {FRT, FRB}},
+{"frim.",      XRC(63,488,1),  XRA_MASK,    POWER5,    PPCVLE,         {FRT, FRB}},
 
-{"dsubq",      XRC(63,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
-{"dsubq.",     XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
+{"dsubq",      XRC(63,514,0),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, FRBp}},
+{"dsubq.",     XRC(63,514,1),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, FRBp}},
 
-{"xssubqp",    XRC(63,516,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-{"xssubqpo",   XRC(63,516,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xssubqp",    XRC(63,516,0),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+{"xssubqpo",   XRC(63,516,1),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"ddivq",      XRC(63,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
-{"ddivq.",     XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRAp, FRBp}},
+{"ddivq",      XRC(63,546,0),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, FRBp}},
+{"ddivq.",     XRC(63,546,1),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRAp, FRBp}},
 
-{"xsdivqp",    XRC(63,548,0),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
-{"xsdivqpo",   XRC(63,548,1),  X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xsdivqp",    XRC(63,548,0),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
+{"xsdivqpo",   XRC(63,548,1),  X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"mffs",       XRC(63,583,0),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
-{"mffs.",      XRC(63,583,1),  XRARB_MASK,  COM,       PPCEFS,         {FRT}},
+{"mffs",       XRC(63,583,0),  XRARB_MASK,  COM,       PPCEFS|PPCVLE,  {FRT}},
+{"mffs.",      XRC(63,583,1),  XRARB_MASK,  COM,       PPCEFS|PPCVLE,  {FRT}},
 
-{"dcmpuq",     X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRAp, FRBp}},
+{"dcmpuq",     X(63,642),      X_MASK,      POWER6,    PPCVLE,         {BF, FRAp, FRBp}},
 
-{"xscmpuqp",   X(63,644),      XBF_MASK,    PPCVSX3,   PPCNONE,        {BF, VA, VB}},
+{"xscmpuqp",   X(63,644),      XBF_MASK,    PPCVSX3,   PPCVLE,         {BF, VA, VB}},
 
-{"dtstsfq",    X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRBp}},
-{"dtstsfiq",   X(63,675),      X_MASK|1<<22,POWER9,    PPCNONE,        {BF, UIM6, FRBp}},
+{"dtstsfq",    X(63,674),      X_MASK,      POWER6,    PPCVLE,         {BF, FRA, FRBp}},
+{"dtstsfiq",   X(63,675),      X_MASK|1<<22,POWER9,    PPCVLE,         {BF, UIM6, FRBp}},
 
-{"xststdcqp",  X(63,708),      X_MASK,      PPCVSX3,   PPCNONE,        {BF, VB, DCMX}},
+{"xststdcqp",  X(63,708),      X_MASK,      PPCVSX3,   PPCVLE,         {BF, VB, DCMX}},
 
-{"mtfsf",      XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
-{"mtfsf",      XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
-{"mtfsf.",     XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
-{"mtfsf.",     XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS,   {FLM, FRB}},
+{"mtfsf",      XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE,  {FLM, FRB, XFL_L, W}},
+{"mtfsf",      XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
+{"mtfsf.",     XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE,  {FLM, FRB, XFL_L, W}},
+{"mtfsf.",     XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
 
-{"drdpq",      XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
-{"drdpq.",     XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRBp}},
+{"drdpq",      XRC(63,770,0),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRBp}},
+{"drdpq.",     XRC(63,770,1),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRBp}},
 
-{"dcffixq",    XRC(63,802,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
-{"dcffixq.",   XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRB}},
+{"dcffixq",    XRC(63,802,0),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRB}},
+{"dcffixq.",   XRC(63,802,1),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRB}},
 
-{"xsabsqp",    XVA(63,804,0),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xsxexpqp",   XVA(63,804,2),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xsnabsqp",   XVA(63,804,8),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xsnegqp",    XVA(63,804,16), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xsxsigqp",   XVA(63,804,18), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xssqrtqp",   XVARC(63,804,27,0), XVA_MASK, PPCVSX3,  PPCNONE,        {VD, VB}},
-{"xssqrtqpo",  XVARC(63,804,27,1), XVA_MASK, PPCVSX3,  PPCNONE,        {VD, VB}},
+{"xsabsqp",    XVA(63,804,0),  XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xsxexpqp",   XVA(63,804,2),  XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xsnabsqp",   XVA(63,804,8),  XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xsnegqp",    XVA(63,804,16), XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xsxsigqp",   XVA(63,804,18), XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xssqrtqp",   XVARC(63,804,27,0), XVA_MASK, PPCVSX3,  PPCVLE,         {VD, VB}},
+{"xssqrtqpo",  XVARC(63,804,27,1), XVA_MASK, PPCVSX3,  PPCVLE,         {VD, VB}},
 
-{"fctid",      XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
-{"fctid",      XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
-{"fctid.",     XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
-{"fctid.",     XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
+{"fctid",      XRC(63,814,0),  XRA_MASK,    PPC64,     PPCVLE,         {FRT, FRB}},
+{"fctid",      XRC(63,814,0),  XRA_MASK,    PPC476,    PPCVLE,         {FRT, FRB}},
+{"fctid.",     XRC(63,814,1),  XRA_MASK,    PPC64,     PPCVLE,         {FRT, FRB}},
+{"fctid.",     XRC(63,814,1),  XRA_MASK,    PPC476,    PPCVLE,         {FRT, FRB}},
 
-{"fctidz",     XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
-{"fctidz",     XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
-{"fctidz.",    XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
-{"fctidz.",    XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
+{"fctidz",     XRC(63,815,0),  XRA_MASK,    PPC64,     PPCVLE,         {FRT, FRB}},
+{"fctidz",     XRC(63,815,0),  XRA_MASK,    PPC476,    PPCVLE,         {FRT, FRB}},
+{"fctidz.",    XRC(63,815,1),  XRA_MASK,    PPC64,     PPCVLE,         {FRT, FRB}},
+{"fctidz.",    XRC(63,815,1),  XRA_MASK,    PPC476,    PPCVLE,         {FRT, FRB}},
 
-{"denbcdq",    XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
-{"denbcdq.",   XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRTp, FRBp}},
+{"denbcdq",    XRC(63,834,0),  X_MASK,      POWER6,    PPCVLE,         {S, FRTp, FRBp}},
+{"denbcdq.",   XRC(63,834,1),  X_MASK,      POWER6,    PPCVLE,         {S, FRTp, FRBp}},
 
-{"xscvqpuwz",  XVA(63,836,1),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xscvudqp",   XVA(63,836,2),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xscvqpswz",  XVA(63,836,9),  XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xscvsdqp",   XVA(63,836,10), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xscvqpudz",  XVA(63,836,17), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xscvqpdp",   XVARC(63,836,20,0), XVA_MASK, PPCVSX3,  PPCNONE,        {VD, VB}},
-{"xscvqpdpo",  XVARC(63,836,20,1), XVA_MASK, PPCVSX3,  PPCNONE,        {VD, VB}},
-{"xscvdpqp",   XVA(63,836,22), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
-{"xscvqpsdz",  XVA(63,836,25), XVA_MASK,    PPCVSX3,   PPCNONE,        {VD, VB}},
+{"xscvqpuwz",  XVA(63,836,1),  XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xscvudqp",   XVA(63,836,2),  XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xscvqpswz",  XVA(63,836,9),  XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xscvsdqp",   XVA(63,836,10), XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xscvqpudz",  XVA(63,836,17), XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xscvqpdp",   XVARC(63,836,20,0), XVA_MASK, PPCVSX3,  PPCVLE,         {VD, VB}},
+{"xscvqpdpo",  XVARC(63,836,20,1), XVA_MASK, PPCVSX3,  PPCVLE,         {VD, VB}},
+{"xscvdpqp",   XVA(63,836,22), XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
+{"xscvqpsdz",  XVA(63,836,25), XVA_MASK,    PPCVSX3,   PPCVLE,         {VD, VB}},
 
-{"fmrgow",     X(63,838),      X_MASK,      PPCVSX2,   PPCNONE,        {FRT, FRA, FRB}},
+{"fmrgow",     X(63,838),      X_MASK,      PPCVSX2,   PPCVLE,         {FRT, FRA, FRB}},
 
-{"fcfid",      XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
-{"fcfid",      XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
-{"fcfid.",     XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
-{"fcfid.",     XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
+{"fcfid",      XRC(63,846,0),  XRA_MASK,    PPC64,     PPCVLE,         {FRT, FRB}},
+{"fcfid",      XRC(63,846,0),  XRA_MASK,    PPC476,    PPCVLE,         {FRT, FRB}},
+{"fcfid.",     XRC(63,846,1),  XRA_MASK,    PPC64,     PPCVLE,         {FRT, FRB}},
+{"fcfid.",     XRC(63,846,1),  XRA_MASK,    PPC476,    PPCVLE,         {FRT, FRB}},
 
-{"diexq",      XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
-{"diexq.",     XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRTp, FRA, FRBp}},
+{"diexq",      XRC(63,866,0),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRA, FRBp}},
+{"diexq.",     XRC(63,866,1),  X_MASK,      POWER6,    PPCVLE,         {FRTp, FRA, FRBp}},
 
-{"xsiexpqp",   X(63,868),      X_MASK,      PPCVSX3,   PPCNONE,        {VD, VA, VB}},
+{"xsiexpqp",   X(63,868),      X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
-{"fctidu",     XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
-{"fctidu.",    XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
+{"fctidu",     XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
+{"fctidu.",    XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
 
-{"fctiduz",    XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
-{"fctiduz.",   XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
+{"fctiduz",    XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
+{"fctiduz.",   XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
 
-{"fmrgew",     X(63,966),      X_MASK,      PPCVSX2,   PPCNONE,        {FRT, FRA, FRB}},
+{"fmrgew",     X(63,966),      X_MASK,      PPCVSX2,   PPCVLE,         {FRT, FRA, FRB}},
 
-{"fcfidu",     XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
-{"fcfidu.",    XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
+{"fcfidu",     XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
+{"fcfidu.",    XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
 };
 
 const int powerpc_num_opcodes =
@@ -6998,226 +6997,225 @@ const int powerpc_num_opcodes =
    The format of this opcode table is the same as the main opcode table.  */
 
 const struct powerpc_opcode vle_opcodes[] = {
-
-{"se_illegal", C(0),           C_MASK,         PPCVLE, PPCNONE,        {}},
-{"se_isync",   C(1),           C_MASK,         PPCVLE, PPCNONE,        {}},
-{"se_sc",      C(2),           C_MASK,         PPCVLE, PPCNONE,        {}},
-{"se_blr",     C_LK(2,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
-{"se_blrl",    C_LK(2,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
-{"se_bctr",    C_LK(3,0),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
-{"se_bctrl",   C_LK(3,1),      C_LK_MASK,      PPCVLE, PPCNONE,        {}},
-{"se_rfi",     C(8),           C_MASK,         PPCVLE, PPCNONE,        {}},
-{"se_rfci",    C(9),           C_MASK,         PPCVLE, PPCNONE,        {}},
-{"se_rfdi",    C(10),          C_MASK,         PPCVLE, PPCNONE,        {}},
-{"se_rfmci",   C(11),          C_MASK,         PPCVLE, PPCNONE,        {}},
-{"se_not",     SE_R(0,2),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_neg",     SE_R(0,3),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_mflr",    SE_R(0,8),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_mtlr",    SE_R(0,9),      SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_mfctr",   SE_R(0,10),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_mtctr",   SE_R(0,11),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_extzb",   SE_R(0,12),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_extsb",   SE_R(0,13),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_extzh",   SE_R(0,14),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_extsh",   SE_R(0,15),     SE_R_MASK,      PPCVLE, PPCNONE,        {RX}},
-{"se_mr",      SE_RR(0,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_mtar",    SE_RR(0,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {ARX, RY}},
-{"se_mfar",    SE_RR(0,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, ARY}},
-{"se_add",     SE_RR(1,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_mullw",   SE_RR(1,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_sub",     SE_RR(1,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_subf",    SE_RR(1,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_cmp",     SE_RR(3,0),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_cmpl",    SE_RR(3,1),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_cmph",    SE_RR(3,2),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_cmphl",   SE_RR(3,3),     SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-
-{"e_cmpi",     SCI8BF(6,0,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
-{"e_cmpli",    SCI8BF(6,1,21), SCI8BF_MASK,    PPCVLE, PPCNONE,        {CRD32, RA, SCLSCI8}},
-{"e_addi",     SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
-{"e_subi",     SCI8(6,16),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
-{"e_addi.",    SCI8(6,17),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
-{"e_addic",    SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
-{"e_subic",    SCI8(6,18),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
-{"e_addic.",   SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
-{"e_subic.",   SCI8(6,19),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8N}},
-{"e_mulli",    SCI8(6,20),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
-{"e_subfic",   SCI8(6,22),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
-{"e_subfic.",  SCI8(6,23),     SCI8_MASK,      PPCVLE, PPCNONE,        {RT, RA, SCLSCI8}},
-{"e_andi",     SCI8(6,24),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
-{"e_andi.",    SCI8(6,25),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
-{"e_nop",      SCI8(6,26),     0xffffffff,     PPCVLE, PPCNONE,        {0}},
-{"e_ori",      SCI8(6,26),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
-{"e_ori.",     SCI8(6,27),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
-{"e_xori",     SCI8(6,28),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
-{"e_xori.",    SCI8(6,29),     SCI8_MASK,      PPCVLE, PPCNONE,        {RA, RS, SCLSCI8}},
-{"e_lbzu",     OPVUP(6,0),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_lhau",     OPVUP(6,3),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_lhzu",     OPVUP(6,1),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_lmw",      OPVUP(6,8),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_lwzu",     OPVUP(6,2),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_stbu",     OPVUP(6,4),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_sthu",     OPVUP(6,5),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_stwu",     OPVUP(6,6),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_stmw",     OPVUP(6,9),     OPVUP_MASK,     PPCVLE, PPCNONE,        {RT, D8, RA0}},
-{"e_add16i",   OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, SI}},
-{"e_la",       OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
-{"e_sub16i",   OP(7),          OP_MASK,        PPCVLE, PPCNONE,        {RT, RA, NSI}},
-
-{"se_addi",    SE_IM5(8,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
-{"se_cmpli",   SE_IM5(8,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
-{"se_subi",    SE_IM5(9,0),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
-{"se_subi.",   SE_IM5(9,1),    SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, OIMM5}},
-{"se_cmpi",    SE_IM5(10,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-{"se_bmaski",  SE_IM5(11,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-{"se_andi",    SE_IM5(11,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-
-{"e_lbz",      OP(12),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
-{"e_stb",      OP(13),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
-{"e_lha",      OP(14),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
-
-{"se_srw",     SE_RR(16,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_sraw",    SE_RR(16,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_slw",     SE_RR(16,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_nop",     SE_RR(17,0),    0xffff,         PPCVLE, PPCNONE,        {0}},
-{"se_or",      SE_RR(17,0),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_andc",    SE_RR(17,1),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_and",     SE_RR(17,2),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_and.",    SE_RR(17,3),    SE_RR_MASK,     PPCVLE, PPCNONE,        {RX, RY}},
-{"se_li",      IM7(9),         IM7_MASK,       PPCVLE, PPCNONE,        {RX, UI7}},
-
-{"e_lwz",      OP(20),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
-{"e_stw",      OP(21),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
-{"e_lhz",      OP(22),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
-{"e_sth",      OP(23),         OP_MASK,        PPCVLE, PPCNONE,        {RT, D, RA0}},
-
-{"se_bclri",   SE_IM5(24,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-{"se_bgeni",   SE_IM5(24,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-{"se_bseti",   SE_IM5(25,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-{"se_btsti",   SE_IM5(25,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-{"se_srwi",    SE_IM5(26,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-{"se_srawi",   SE_IM5(26,1),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-{"se_slwi",    SE_IM5(27,0),   SE_IM5_MASK,    PPCVLE, PPCNONE,        {RX, UI5}},
-
-{"e_lis",      I16L(28,28),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
-{"e_and2is.",  I16L(28,29),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
-{"e_or2is",    I16L(28,26),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
-{"e_and2i.",   I16L(28,25),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
-{"e_or2i",     I16L(28,24),    I16L_MASK,      PPCVLE, PPCNONE,        {RD, VLEUIMML}},
-{"e_cmphl16i", IA16(28,23),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
-{"e_cmph16i",  IA16(28,22),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
-{"e_cmpl16i",  I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLEUIMM}},
-{"e_cmplwi",   I16A(28,21),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
-{"e_mull2i",   I16A(28,20),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
-{"e_cmp16i",   IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
-{"e_cmpwi",    IA16(28,19),    IA16_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
-{"e_sub2is",   I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
-{"e_add2is",   I16A(28,18),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
-{"e_sub2i.",   I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLENSIMM}},
-{"e_add2i.",   I16A(28,17),    I16A_MASK,      PPCVLE, PPCNONE,        {RA, VLESIMM}},
-{"e_li",       LI20(28,0),     LI20_MASK,      PPCVLE, PPCNONE,        {RT, IMM20}},
-{"e_rlwimi",   M(29,0),        M_MASK,         PPCVLE, PPCNONE,        {RA, RS, SH, MB, ME}},
-{"e_rlwinm",   M(29,1),        M_MASK,         PPCVLE, PPCNONE,        {RA, RT, SH, MBE, ME}},
-{"e_b",                BD24(30,0,0),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
-{"e_bl",       BD24(30,0,1),   BD24_MASK,      PPCVLE, PPCNONE,        {B24}},
-{"e_bdnz",     EBD15(30,8,BO32DNZ,0),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
-{"e_bdnzl",    EBD15(30,8,BO32DNZ,1),  EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
-{"e_bdz",      EBD15(30,8,BO32DZ,0),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
-{"e_bdzl",     EBD15(30,8,BO32DZ,1),   EBD15_MASK, PPCVLE, PPCNONE,    {B15}},
-{"e_bge",      EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bgel",     EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bnl",      EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bnll",     EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_blt",      EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bltl",     EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bgt",      EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bgtl",     EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_ble",      EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_blel",     EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bng",      EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bngl",     EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bne",      EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bnel",     EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_beq",      EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_beql",     EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bso",      EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bsol",     EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bun",      EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bunl",     EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bns",      EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bnsl",     EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bnu",      EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bnul",     EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}},
-{"e_bc",       BD15(30,8,0),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
-{"e_bcl",      BD15(30,8,1),   BD15_MASK,      PPCVLE, PPCNONE,        {BO32, BI32, B15}},
-
-{"e_bf",       EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
-{"e_bfl",      EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
-{"e_bt",       EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
-{"e_btl",      EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE,       {BI32,B15}},
-
-{"e_cmph",     X(31,14),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
-{"e_cmphl",    X(31,46),       X_MASK,         PPCVLE, PPCNONE,        {CRD, RA, RB}},
-{"e_crandc",   XL(31,129),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
-{"e_crnand",   XL(31,225),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
-{"e_crnot",    XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
-{"e_crnor",    XL(31,33),      XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
-{"e_crclr",    XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
-{"e_crxor",    XL(31,193),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
-{"e_mcrf",     XL(31,16),      XL_MASK,        PPCVLE, PPCNONE,        {CRD, CR}},
-{"e_slwi",     EX(31,112),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
-{"e_slwi.",    EX(31,113),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
-
-{"e_crand",    XL(31,257),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
-
-{"e_rlw",      EX(31,560),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
-{"e_rlw.",     EX(31,561),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, RB}},
-
-{"e_crset",    XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BAT, BBA}},
-{"e_creqv",    XL(31,289),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
-
-{"e_rlwi",     EX(31,624),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
-{"e_rlwi.",    EX(31,625),     EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
-
-{"e_crorc",    XL(31,417),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
-
-{"e_crmove",   XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BBA}},
-{"e_cror",     XL(31,449),     XL_MASK,        PPCVLE, PPCNONE,        {BT, BA, BB}},
-
-{"mtmas1",     XSPR(31,467,625), XSPR_MASK,    PPCVLE, PPCNONE,        {RS}},
-
-{"e_srwi",     EX(31,1136),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
-{"e_srwi.",    EX(31,1137),    EX_MASK,        PPCVLE, PPCNONE,        {RA, RS, SH}},
-
-{"se_lbz",     SD4(8),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
-
-{"se_stb",     SD4(9),         SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SD, RX}},
-
-{"se_lhz",     SD4(10),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
-
-{"se_sth",     SD4(11),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDH, RX}},
-
-{"se_lwz",     SD4(12),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
-
-{"se_stw",     SD4(13),        SD4_MASK,       PPCVLE, PPCNONE,        {RZ, SE_SDW, RX}},
-
-{"se_bge",     EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bnl",     EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_ble",     EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bng",     EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bne",     EBD8IO(28,0,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bns",     EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bnu",     EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bf",      EBD8IO(28,0,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
-{"se_blt",     EBD8IO(28,1,0), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bgt",     EBD8IO(28,1,1), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_beq",     EBD8IO(28,1,2), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bso",     EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bun",     EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, PPCNONE,        {B8}},
-{"se_bt",      EBD8IO(28,1,0), EBD8IO2_MASK,   PPCVLE, PPCNONE,        {BI16, B8}},
-{"se_bc",      BD8IO(28),      BD8IO_MASK,     PPCVLE, PPCNONE,        {BO16, BI16, B8}},
-{"se_b",       BD8(58,0,0),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
-{"se_bl",      BD8(58,0,1),    BD8_MASK,       PPCVLE, PPCNONE,        {B8}},
+{"se_illegal", C(0),           C_MASK,         PPCVLE, 0,              {}},
+{"se_isync",   C(1),           C_MASK,         PPCVLE, 0,              {}},
+{"se_sc",      C(2),           C_MASK,         PPCVLE, 0,              {}},
+{"se_blr",     C_LK(2,0),      C_LK_MASK,      PPCVLE, 0,              {}},
+{"se_blrl",    C_LK(2,1),      C_LK_MASK,      PPCVLE, 0,              {}},
+{"se_bctr",    C_LK(3,0),      C_LK_MASK,      PPCVLE, 0,              {}},
+{"se_bctrl",   C_LK(3,1),      C_LK_MASK,      PPCVLE, 0,              {}},
+{"se_rfi",     C(8),           C_MASK,         PPCVLE, 0,              {}},
+{"se_rfci",    C(9),           C_MASK,         PPCVLE, 0,              {}},
+{"se_rfdi",    C(10),          C_MASK,         PPCVLE, 0,              {}},
+{"se_rfmci",   C(11),          C_MASK, PPCRFMCI|PPCVLE, 0,             {}},
+{"se_not",     SE_R(0,2),      SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_neg",     SE_R(0,3),      SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_mflr",    SE_R(0,8),      SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_mtlr",    SE_R(0,9),      SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_mfctr",   SE_R(0,10),     SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_mtctr",   SE_R(0,11),     SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_extzb",   SE_R(0,12),     SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_extsb",   SE_R(0,13),     SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_extzh",   SE_R(0,14),     SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_extsh",   SE_R(0,15),     SE_R_MASK,      PPCVLE, 0,              {RX}},
+{"se_mr",      SE_RR(0,1),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_mtar",    SE_RR(0,2),     SE_RR_MASK,     PPCVLE, 0,              {ARX, RY}},
+{"se_mfar",    SE_RR(0,3),     SE_RR_MASK,     PPCVLE, 0,              {RX, ARY}},
+{"se_add",     SE_RR(1,0),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_mullw",   SE_RR(1,1),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_sub",     SE_RR(1,2),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_subf",    SE_RR(1,3),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_cmp",     SE_RR(3,0),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_cmpl",    SE_RR(3,1),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_cmph",    SE_RR(3,2),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_cmphl",   SE_RR(3,3),     SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+
+{"e_cmpi",     SCI8BF(6,0,21), SCI8BF_MASK,    PPCVLE, 0,              {CRD32, RA, SCLSCI8}},
+{"e_cmpli",    SCI8BF(6,1,21), SCI8BF_MASK,    PPCVLE, 0,              {CRD32, RA, SCLSCI8}},
+{"e_addi",     SCI8(6,16),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
+{"e_subi",     SCI8(6,16),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8N}},
+{"e_addi.",    SCI8(6,17),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
+{"e_addic",    SCI8(6,18),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
+{"e_subic",    SCI8(6,18),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8N}},
+{"e_addic.",   SCI8(6,19),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
+{"e_subic.",   SCI8(6,19),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8N}},
+{"e_mulli",    SCI8(6,20),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
+{"e_subfic",   SCI8(6,22),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
+{"e_subfic.",  SCI8(6,23),     SCI8_MASK,      PPCVLE, 0,              {RT, RA, SCLSCI8}},
+{"e_andi",     SCI8(6,24),     SCI8_MASK,      PPCVLE, 0,              {RA, RS, SCLSCI8}},
+{"e_andi.",    SCI8(6,25),     SCI8_MASK,      PPCVLE, 0,              {RA, RS, SCLSCI8}},
+{"e_nop",      SCI8(6,26),     0xffffffff,     PPCVLE, 0,              {0}},
+{"e_ori",      SCI8(6,26),     SCI8_MASK,      PPCVLE, 0,              {RA, RS, SCLSCI8}},
+{"e_ori.",     SCI8(6,27),     SCI8_MASK,      PPCVLE, 0,              {RA, RS, SCLSCI8}},
+{"e_xori",     SCI8(6,28),     SCI8_MASK,      PPCVLE, 0,              {RA, RS, SCLSCI8}},
+{"e_xori.",    SCI8(6,29),     SCI8_MASK,      PPCVLE, 0,              {RA, RS, SCLSCI8}},
+{"e_lbzu",     OPVUP(6,0),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_lhau",     OPVUP(6,3),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_lhzu",     OPVUP(6,1),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_lmw",      OPVUP(6,8),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_lwzu",     OPVUP(6,2),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_stbu",     OPVUP(6,4),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_sthu",     OPVUP(6,5),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_stwu",     OPVUP(6,6),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_stmw",     OPVUP(6,9),     OPVUP_MASK,     PPCVLE, 0,              {RT, D8, RA0}},
+{"e_add16i",   OP(7),          OP_MASK,        PPCVLE, 0,              {RT, RA, SI}},
+{"e_la",       OP(7),          OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
+{"e_sub16i",   OP(7),          OP_MASK,        PPCVLE, 0,              {RT, RA, NSI}},
+
+{"se_addi",    SE_IM5(8,0),    SE_IM5_MASK,    PPCVLE, 0,              {RX, OIMM5}},
+{"se_cmpli",   SE_IM5(8,1),    SE_IM5_MASK,    PPCVLE, 0,              {RX, OIMM5}},
+{"se_subi",    SE_IM5(9,0),    SE_IM5_MASK,    PPCVLE, 0,              {RX, OIMM5}},
+{"se_subi.",   SE_IM5(9,1),    SE_IM5_MASK,    PPCVLE, 0,              {RX, OIMM5}},
+{"se_cmpi",    SE_IM5(10,1),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+{"se_bmaski",  SE_IM5(11,0),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+{"se_andi",    SE_IM5(11,1),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+
+{"e_lbz",      OP(12),         OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
+{"e_stb",      OP(13),         OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
+{"e_lha",      OP(14),         OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
+
+{"se_srw",     SE_RR(16,0),    SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_sraw",    SE_RR(16,1),    SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_slw",     SE_RR(16,2),    SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_nop",     SE_RR(17,0),    0xffff,         PPCVLE, 0,              {0}},
+{"se_or",      SE_RR(17,0),    SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_andc",    SE_RR(17,1),    SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_and",     SE_RR(17,2),    SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_and.",    SE_RR(17,3),    SE_RR_MASK,     PPCVLE, 0,              {RX, RY}},
+{"se_li",      IM7(9),         IM7_MASK,       PPCVLE, 0,              {RX, UI7}},
+
+{"e_lwz",      OP(20),         OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
+{"e_stw",      OP(21),         OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
+{"e_lhz",      OP(22),         OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
+{"e_sth",      OP(23),         OP_MASK,        PPCVLE, 0,              {RT, D, RA0}},
+
+{"se_bclri",   SE_IM5(24,0),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+{"se_bgeni",   SE_IM5(24,1),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+{"se_bseti",   SE_IM5(25,0),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+{"se_btsti",   SE_IM5(25,1),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+{"se_srwi",    SE_IM5(26,0),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+{"se_srawi",   SE_IM5(26,1),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+{"se_slwi",    SE_IM5(27,0),   SE_IM5_MASK,    PPCVLE, 0,              {RX, UI5}},
+
+{"e_lis",      I16L(28,28),    I16L_MASK,      PPCVLE, 0,              {RD, VLEUIMML}},
+{"e_and2is.",  I16L(28,29),    I16L_MASK,      PPCVLE, 0,              {RD, VLEUIMML}},
+{"e_or2is",    I16L(28,26),    I16L_MASK,      PPCVLE, 0,              {RD, VLEUIMML}},
+{"e_and2i.",   I16L(28,25),    I16L_MASK,      PPCVLE, 0,              {RD, VLEUIMML}},
+{"e_or2i",     I16L(28,24),    I16L_MASK,      PPCVLE, 0,              {RD, VLEUIMML}},
+{"e_cmphl16i", IA16(28,23),    IA16_MASK,      PPCVLE, 0,              {RA, VLEUIMM}},
+{"e_cmph16i",  IA16(28,22),    IA16_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
+{"e_cmpl16i",  I16A(28,21),    I16A_MASK,      PPCVLE, 0,              {RA, VLEUIMM}},
+{"e_cmplwi",   I16A(28,21),    I16A_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
+{"e_mull2i",   I16A(28,20),    I16A_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
+{"e_cmp16i",   IA16(28,19),    IA16_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
+{"e_cmpwi",    IA16(28,19),    IA16_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
+{"e_sub2is",   I16A(28,18),    I16A_MASK,      PPCVLE, 0,              {RA, VLENSIMM}},
+{"e_add2is",   I16A(28,18),    I16A_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
+{"e_sub2i.",   I16A(28,17),    I16A_MASK,      PPCVLE, 0,              {RA, VLENSIMM}},
+{"e_add2i.",   I16A(28,17),    I16A_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
+{"e_li",       LI20(28,0),     LI20_MASK,      PPCVLE, 0,              {RT, IMM20}},
+{"e_rlwimi",   M(29,0),        M_MASK,         PPCVLE, 0,              {RA, RS, SH, MB, ME}},
+{"e_rlwinm",   M(29,1),        M_MASK,         PPCVLE, 0,              {RA, RT, SH, MBE, ME}},
+{"e_b",                BD24(30,0,0),   BD24_MASK,      PPCVLE, 0,              {B24}},
+{"e_bl",       BD24(30,0,1),   BD24_MASK,      PPCVLE, 0,              {B24}},
+{"e_bdnz",     EBD15(30,8,BO32DNZ,0),  EBD15_MASK, PPCVLE, 0,          {B15}},
+{"e_bdnzl",    EBD15(30,8,BO32DNZ,1),  EBD15_MASK, PPCVLE, 0,          {B15}},
+{"e_bdz",      EBD15(30,8,BO32DZ,0),   EBD15_MASK, PPCVLE, 0,          {B15}},
+{"e_bdzl",     EBD15(30,8,BO32DZ,1),   EBD15_MASK, PPCVLE, 0,          {B15}},
+{"e_bge",      EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bgel",     EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bnl",      EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bnll",     EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_blt",      EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bltl",     EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bgt",      EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bgtl",     EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_ble",      EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_blel",     EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bng",      EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bngl",     EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bne",      EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bnel",     EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_beq",      EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_beql",     EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bso",      EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bsol",     EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bun",      EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bunl",     EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bns",      EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bnsl",     EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bnu",      EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bnul",     EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0,    {CRS,B15}},
+{"e_bc",       BD15(30,8,0),   BD15_MASK,      PPCVLE, 0,              {BO32, BI32, B15}},
+{"e_bcl",      BD15(30,8,1),   BD15_MASK,      PPCVLE, 0,              {BO32, BI32, B15}},
+
+{"e_bf",       EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0,             {BI32,B15}},
+{"e_bfl",      EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0,             {BI32,B15}},
+{"e_bt",       EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0,             {BI32,B15}},
+{"e_btl",      EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0,             {BI32,B15}},
+
+{"e_cmph",     X(31,14),       X_MASK,         PPCVLE, 0,              {CRD, RA, RB}},
+{"e_cmphl",    X(31,46),       X_MASK,         PPCVLE, 0,              {CRD, RA, RB}},
+{"e_crandc",   XL(31,129),     XL_MASK,        PPCVLE, 0,              {BT, BA, BB}},
+{"e_crnand",   XL(31,225),     XL_MASK,        PPCVLE, 0,              {BT, BA, BB}},
+{"e_crnot",    XL(31,33),      XL_MASK,        PPCVLE, 0,              {BT, BA, BBA}},
+{"e_crnor",    XL(31,33),      XL_MASK,        PPCVLE, 0,              {BT, BA, BB}},
+{"e_crclr",    XL(31,193),     XL_MASK,        PPCVLE, 0,              {BT, BAT, BBA}},
+{"e_crxor",    XL(31,193),     XL_MASK,        PPCVLE, 0,              {BT, BA, BB}},
+{"e_mcrf",     XL(31,16),      XL_MASK,        PPCVLE, 0,              {CRD, CR}},
+{"e_slwi",     EX(31,112),     EX_MASK,        PPCVLE, 0,              {RA, RS, SH}},
+{"e_slwi.",    EX(31,113),     EX_MASK,        PPCVLE, 0,              {RA, RS, SH}},
+
+{"e_crand",    XL(31,257),     XL_MASK,        PPCVLE, 0,              {BT, BA, BB}},
+
+{"e_rlw",      EX(31,560),     EX_MASK,        PPCVLE, 0,              {RA, RS, RB}},
+{"e_rlw.",     EX(31,561),     EX_MASK,        PPCVLE, 0,              {RA, RS, RB}},
+
+{"e_crset",    XL(31,289),     XL_MASK,        PPCVLE, 0,              {BT, BAT, BBA}},
+{"e_creqv",    XL(31,289),     XL_MASK,        PPCVLE, 0,              {BT, BA, BB}},
+
+{"e_rlwi",     EX(31,624),     EX_MASK,        PPCVLE, 0,              {RA, RS, SH}},
+{"e_rlwi.",    EX(31,625),     EX_MASK,        PPCVLE, 0,              {RA, RS, SH}},
+
+{"e_crorc",    XL(31,417),     XL_MASK,        PPCVLE, 0,              {BT, BA, BB}},
+
+{"e_crmove",   XL(31,449),     XL_MASK,        PPCVLE, 0,              {BT, BA, BBA}},
+{"e_cror",     XL(31,449),     XL_MASK,        PPCVLE, 0,              {BT, BA, BB}},
+
+{"mtmas1",     XSPR(31,467,625), XSPR_MASK,    PPCVLE, 0,              {RS}},
+
+{"e_srwi",     EX(31,1136),    EX_MASK,        PPCVLE, 0,              {RA, RS, SH}},
+{"e_srwi.",    EX(31,1137),    EX_MASK,        PPCVLE, 0,              {RA, RS, SH}},
+
+{"se_lbz",     SD4(8),         SD4_MASK,       PPCVLE, 0,              {RZ, SE_SD, RX}},
+
+{"se_stb",     SD4(9),         SD4_MASK,       PPCVLE, 0,              {RZ, SE_SD, RX}},
+
+{"se_lhz",     SD4(10),        SD4_MASK,       PPCVLE, 0,              {RZ, SE_SDH, RX}},
+
+{"se_sth",     SD4(11),        SD4_MASK,       PPCVLE, 0,              {RZ, SE_SDH, RX}},
+
+{"se_lwz",     SD4(12),        SD4_MASK,       PPCVLE, 0,              {RZ, SE_SDW, RX}},
+
+{"se_stw",     SD4(13),        SD4_MASK,       PPCVLE, 0,              {RZ, SE_SDW, RX}},
+
+{"se_bge",     EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bnl",     EBD8IO(28,0,0), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_ble",     EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bng",     EBD8IO(28,0,1), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bne",     EBD8IO(28,0,2), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bns",     EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bnu",     EBD8IO(28,0,3), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bf",      EBD8IO(28,0,0), EBD8IO2_MASK,   PPCVLE, 0,              {BI16, B8}},
+{"se_blt",     EBD8IO(28,1,0), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bgt",     EBD8IO(28,1,1), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_beq",     EBD8IO(28,1,2), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bso",     EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bun",     EBD8IO(28,1,3), EBD8IO3_MASK,   PPCVLE, 0,              {B8}},
+{"se_bt",      EBD8IO(28,1,0), EBD8IO2_MASK,   PPCVLE, 0,              {BI16, B8}},
+{"se_bc",      BD8IO(28),      BD8IO_MASK,     PPCVLE, 0,              {BO16, BI16, B8}},
+{"se_b",       BD8(58,0,0),    BD8_MASK,       PPCVLE, 0,              {B8}},
+{"se_bl",      BD8(58,0,1),    BD8_MASK,       PPCVLE, 0,              {B8}},
 };
 
 const int vle_num_opcodes =
@@ -7251,7 +7249,7 @@ const struct powerpc_macro powerpc_macros[] = {
 {"clrrdi",   3,        PPC64,  "rldicr %0,%1,0,63-(%2)"},
 {"clrrdi.",  3,        PPC64,  "rldicr. %0,%1,0,63-(%2)"},
 {"clrlsldi", 4,        PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
-{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
+{"clrlsldi.",4,        PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
 
 {"extlwi",   4,        PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
 {"extlwi.",  4,        PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},