ethtool: Add support for 400Gbps (50Gbps per lane) link modes

Add support for 400Gbps speed, link modes of 50Gbps per lane

Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 9412669..4d96f7a 100644 (file)
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -8,7 +8,7 @@
 
 const char *phy_speed_to_str(int speed)
 {
-       BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 69,
+       BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 74,
                "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
                "If a speed or mode has been added please update phy_speed_to_str "
                "and the PHY settings array.\n");
@@ -42,6 +42,8 @@ const char *phy_speed_to_str(int speed)
                return "100Gbps";
        case SPEED_200000:
                return "200Gbps";
+       case SPEED_400000:
+               return "400Gbps";
        case SPEED_UNKNOWN:
                return "Unknown";
        default:
@@ -70,6 +72,12 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str);
                               .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
 
 static const struct phy_setting settings[] = {
+       /* 400G */
+       PHY_SETTING( 400000, FULL, 400000baseCR8_Full           ),
+       PHY_SETTING( 400000, FULL, 400000baseKR8_Full           ),
+       PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full   ),
+       PHY_SETTING( 400000, FULL, 400000baseDR8_Full           ),
+       PHY_SETTING( 400000, FULL, 400000baseSR8_Full           ),
        /* 200G */
        PHY_SETTING( 200000, FULL, 200000baseCR4_Full           ),
        PHY_SETTING( 200000, FULL, 200000baseKR4_Full           ),

diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 8938b76..d459179 100644 (file)
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1507,6 +1507,11 @@ enum ethtool_link_mode_bit_indices {
        ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT         = 66,
        ETHTOOL_LINK_MODE_100baseT1_Full_BIT             = 67,
        ETHTOOL_LINK_MODE_1000baseT1_Full_BIT            = 68,
+       ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT         = 69,
+       ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT         = 70,
+       ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,
+       ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT         = 72,
+       ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT         = 73,
 
        /* must be last entry */
        __ETHTOOL_LINK_MODE_MASK_NBITS
@@ -1618,6 +1623,7 @@ enum ethtool_link_mode_bit_indices {
 #define SPEED_56000            56000
 #define SPEED_100000           100000
 #define SPEED_200000           200000
+#define SPEED_400000           400000
 
 #define SPEED_UNKNOWN          -1