This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass.
- Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer).
- Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension).
To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D40554
default:
return false;
case PPC::COPY:
- return TII->isSignExtended(MI);
+ return TII->isSignExtended(MI.getOperand(1).getReg(),
+ &MI.getMF()->getRegInfo());
case PPC::LHA:
case PPC::LHA8:
case PPC::LHAU:
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
"li $rD, $imm", IIC_IntSimple,
- [(set i64:$rD, imm64SExt16:$imm)]>;
+ [(set i64:$rD, imm64SExt16:$imm)]>, SExt32To64;
def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
"lis $rD, $imm", IIC_IntSimple,
- [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
+ [(set i64:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64;
}
// Logical ops.
def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
"andi. $dst, $src1, $src2", IIC_IntGeneral,
[(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
- isRecordForm;
+ isRecordForm, SExt32To64, ZExt32To64;
def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
"andis. $dst, $src1, $src2", IIC_IntGeneral,
[(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
- isRecordForm;
+ isRecordForm, ZExt32To64;
}
def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
"ori $dst, $src1, $src2", IIC_IntSimple,
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS),
- "cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
+ "cntlzw", "$rA, $rS", IIC_IntGeneral, []>,
+ ZExt32To64, SExt32To64;
defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS),
"cnttzw", "$rA, $rS", IIC_IntGeneral, []>,
- Requires<[IsISA3_0]>;
+ Requires<[IsISA3_0]>, ZExt32To64, SExt32To64;
defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
"extsb", "$rA, $rS", IIC_IntSimple,
- [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
+ [(set i64:$rA, (sext_inreg i64:$rS, i8))]>, SExt32To64;
defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
"extsh", "$rA, $rS", IIC_IntSimple,
- [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
+ [(set i64:$rA, (sext_inreg i64:$rS, i16))]>, SExt32To64;
defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
- "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
+ "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64;
defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
- "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
+ "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64;
} // Interpretation64Bit
// For fast-isel:
let isCodeGenOnly = 1 in {
def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
- "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
+ "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64,
+ SExt32To64;
def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
- "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
+ "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64,
+ SExt32To64;
} // isCodeGenOnly for fast-isel
defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
"extsw", "$rA, $rS", IIC_IntSimple,
- [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
+ [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64,
+ SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
"extsw", "$rA, $rS", IIC_IntSimple,
- [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
+ [(set i64:$rA, (sext i32:$rS))]>, isPPC64,
+ SExt32To64;
let isCodeGenOnly = 1 in
def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS),
"extsw $rA, $rS", IIC_IntSimple,
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
"cntlzd", "$rA, $rS", IIC_IntGeneral,
- [(set i64:$rA, (ctlz i64:$rS))]>;
+ [(set i64:$rA, (ctlz i64:$rS))]>,
+ ZExt32To64, SExt32To64;
defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS),
"cnttzd", "$rA, $rS", IIC_IntGeneral,
- [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>;
+ [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>,
+ ZExt32To64, SExt32To64;
def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
"popcntd $rA, $rS", IIC_IntGeneral,
- [(set i64:$rA, (ctpop i64:$rS))]>;
+ [(set i64:$rA, (ctpop i64:$rS))]>,
+ ZExt32To64, SExt32To64;
def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"bpermd $rA, $rS, $rB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>,
[(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
isPPC64;
def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
- "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
+ "setb $RT, $BFA", IIC_IntGeneral>, isPPC64, SExt32To64;
}
def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
"addpcis $RT, $D", IIC_BrB, []>, isPPC64;
def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
"lha $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi16 DForm:$src))]>,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
"lwa $rD, $src", IIC_LdStLWA,
[(set i64:$rD,
(sextloadi32 DSForm:$src))]>, isPPC64,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src),
"lhax $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi16 XForm:$src))]>,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src),
"lwax $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
// For fast-isel:
let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in {
def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
"lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src),
"lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
} // end fast-isel isCodeGenOnly
// Update forms.
let PPC970_Unit = 2 in {
def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
"lbz $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi8 DForm:$src))]>;
+ [(set i64:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
"lhz $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi16 DForm:$src))]>;
+ [(set i64:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
"lwz $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64;
+ [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64,
+ ZExt32To64;
def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src),
"lbzx $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi8 XForm:$src))]>;
+ [(set i64:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src),
"lhzx $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi16 XForm:$src))]>;
+ [(set i64:$rD, (zextloadi16 XForm:$src))]>,
+ ZExt32To64, SExt32To64;
def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src),
"lwzx $rD, $src", IIC_LdStLoad,
- [(set i64:$rD, (zextloadi32 XForm:$src))]>;
+ [(set i64:$rD, (zextloadi32 XForm:$src))]>,
+ ZExt32To64;
// Update forms.
let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src),
- "lhbrx $rD, $src", IIC_LdStLoad, []>;
+ "lhbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64;
def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src),
- "lwbrx $rD, $src", IIC_LdStLoad, []>;
+ "lwbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64;
}
let mayLoad = 1, hasSideEffects = 0 in {
// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
let hasSideEffects = 0 in {
-def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
-def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
-def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
-def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
-def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
-def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
+def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>, ZExt32To64;
+def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>, ZExt32To64;
+def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>, ZExt32To64;
+def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>, ZExt32To64;
+def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>, ZExt32To64;
+def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>, ZExt32To64;
}
// Vector Insert Element Instructions
// Indicate that this instruction is prefixed.
bits<1> Prefixed = 0;
let TSFlags{7} = Prefixed;
+
+ // Indicate that this instruction produces a result that is sign extended from
+ // 32 bits to 64 bits.
+ bits<1> SExt32To64 = 0;
+ let TSFlags{8} = SExt32To64;
+
+ // Indicate that this instruction produces a result that is zero extended from
+ // 32 bits to 64 bits.
+ bits<1> ZExt32To64 = 0;
+ let TSFlags{9} = ZExt32To64;
// Fields used for relation models.
string BaseName = "";
class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
class XFormMemOp { bits<1> XFormMemOp = 1; }
+class SExt32To64 { bits<1> SExt32To64 = 1; }
+class ZExt32To64 { bits<1> ZExt32To64 = 1; }
// Two joined instructions; used to emit two adjacent instructions as one.
// The itinerary from the first instruction is used for scheduling and
#include "PPCInstrBuilder.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCTargetMachine.h"
+#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
bool noSub = false;
if (isPPC64) {
if (is32BitSignedCompare) {
- // We can perform this optimization only if MI is sign-extending.
- if (isSignExtended(*MI))
+ // We can perform this optimization only if SrcReg is sign-extending.
+ if (isSignExtended(SrcReg, MRI))
noSub = true;
else
return false;
} else if (is32BitUnsignedCompare) {
- // We can perform this optimization, equality only, if MI is
+ // We can perform this optimization, equality only, if SrcReg is
// zero-extending.
- if (isZeroExtended(*MI)) {
+ if (isZeroExtended(SrcReg, MRI)) {
noSub = true;
equalityOnly = true;
} else
return PPC::getRecordFormOpcode(Opcode);
}
-// This function returns true if the machine instruction
-// always outputs a value by sign-extending a 32 bit value,
-// i.e. 0 to 31-th bits are same as 32-th bit.
-static bool isSignExtendingOp(const MachineInstr &MI) {
- int Opcode = MI.getOpcode();
- if (Opcode == PPC::LI || Opcode == PPC::LI8 || Opcode == PPC::LIS ||
- Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec ||
- Opcode == PPC::SRAWI || Opcode == PPC::SRAWI_rec || Opcode == PPC::LWA ||
- Opcode == PPC::LWAX || Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
- Opcode == PPC::LHA || Opcode == PPC::LHAX || Opcode == PPC::LHA8 ||
- Opcode == PPC::LHAX8 || Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
- Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || Opcode == PPC::LBZU ||
- Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
- Opcode == PPC::LHZ || Opcode == PPC::LHZX || Opcode == PPC::LHZ8 ||
- Opcode == PPC::LHZX8 || Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
- Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || Opcode == PPC::EXTSB ||
- Opcode == PPC::EXTSB_rec || Opcode == PPC::EXTSH ||
- Opcode == PPC::EXTSH_rec || Opcode == PPC::EXTSB8 ||
- Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSW ||
- Opcode == PPC::EXTSW_rec || Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
- Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
- Opcode == PPC::EXTSB8_32_64)
+static bool isOpZeroOfSubwordPreincLoad(int Opcode) {
+ return (Opcode == PPC::LBZU || Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 ||
+ Opcode == PPC::LBZUX8 || Opcode == PPC::LHZU ||
+ Opcode == PPC::LHZUX || Opcode == PPC::LHZU8 ||
+ Opcode == PPC::LHZUX8);
+}
+
+// This function checks for sign extension from 32 bits to 64 bits.
+static bool definedBySignExtendingOp(const unsigned Reg,
+ const MachineRegisterInfo *MRI) {
+ if (!Register::isVirtualRegister(Reg))
+ return false;
+
+ MachineInstr *MI = MRI->getVRegDef(Reg);
+ if (!MI)
+ return false;
+
+ int Opcode = MI->getOpcode();
+ const PPCInstrInfo *TII =
+ MI->getMF()->getSubtarget<PPCSubtarget>().getInstrInfo();
+ if (TII->isSExt32To64(Opcode))
+ return true;
+
+ // The first def of LBZU/LHZU is sign extended.
+ if (isOpZeroOfSubwordPreincLoad(Opcode) && MI->getOperand(0).getReg() == Reg)
return true;
- if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
+ // RLDICL generates sign-extended output if it clears at least
+ // 33 bits from the left (MSB).
+ if (Opcode == PPC::RLDICL && MI->getOperand(3).getImm() >= 33)
return true;
+ // If at least one bit from left in a lower word is masked out,
+ // all of 0 to 32-th bits of the output are cleared.
+ // Hence the output is already sign extended.
if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) &&
- MI.getOperand(3).getImm() > 0 &&
- MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+ MI->getOperand(3).getImm() > 0 &&
+ MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
return true;
+ // If the most significant bit of immediate in ANDIS is zero,
+ // all of 0 to 32-th bits are cleared.
+ if (Opcode == PPC::ANDIS_rec || Opcode == PPC::ANDIS8_rec) {
+ uint16_t Imm = MI->getOperand(2).getImm();
+ if ((Imm & 0x8000) == 0)
+ return true;
+ }
+
return false;
}
-// This function returns true if the machine instruction
-// always outputs zeros in higher 32 bits.
-static bool isZeroExtendingOp(const MachineInstr &MI) {
- int Opcode = MI.getOpcode();
+// This function checks the machine instruction that defines the input register
+// Reg. If that machine instruction always outputs a value that has only zeros
+// in the higher 32 bits then this function will return true.
+static bool definedByZeroExtendingOp(const unsigned Reg,
+ const MachineRegisterInfo *MRI) {
+ if (!Register::isVirtualRegister(Reg))
+ return false;
+
+ MachineInstr *MI = MRI->getVRegDef(Reg);
+ if (!MI)
+ return false;
+
+ int Opcode = MI->getOpcode();
+ const PPCInstrInfo *TII =
+ MI->getMF()->getSubtarget<PPCSubtarget>().getInstrInfo();
+ if (TII->isZExt32To64(Opcode))
+ return true;
+
+ // The first def of LBZU/LHZU/LWZU are zero extended.
+ if ((isOpZeroOfSubwordPreincLoad(Opcode) || Opcode == PPC::LWZU ||
+ Opcode == PPC::LWZUX || Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8) &&
+ MI->getOperand(0).getReg() == Reg)
+ return true;
+
// The 16-bit immediate is sign-extended in li/lis.
// If the most significant bit is zero, all higher bits are zero.
if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
Opcode == PPC::LIS || Opcode == PPC::LIS8) {
- int64_t Imm = MI.getOperand(1).getImm();
+ int64_t Imm = MI->getOperand(1).getImm();
if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
return true;
}
if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec ||
Opcode == PPC::RLDICL_32_64) &&
- MI.getOperand(3).getImm() >= 32)
+ MI->getOperand(3).getImm() >= 32)
return true;
if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
- MI.getOperand(3).getImm() >= 32 &&
- MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
+ MI->getOperand(3).getImm() >= 32 &&
+ MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
return true;
if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
- MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
- return true;
-
- // There are other instructions that clear higher 32-bits.
- if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
- Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
- Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
- Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
- Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec ||
- Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW ||
- Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec ||
- Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || Opcode == PPC::SLWI ||
- Opcode == PPC::SLWI_rec || Opcode == PPC::SRWI ||
- Opcode == PPC::SRWI_rec || Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
- Opcode == PPC::LWZU || Opcode == PPC::LWZUX || Opcode == PPC::LWBRX ||
- Opcode == PPC::LHBRX || Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
- Opcode == PPC::LHZU || Opcode == PPC::LHZUX || Opcode == PPC::LBZ ||
- Opcode == PPC::LBZX || Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
- Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || Opcode == PPC::LWZU8 ||
- Opcode == PPC::LWZUX8 || Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
- Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || Opcode == PPC::LHZU8 ||
- Opcode == PPC::LHZUX8 || Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
- Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
- Opcode == PPC::ANDI_rec || Opcode == PPC::ANDIS_rec ||
- Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWI_rec ||
- Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWI_rec ||
- Opcode == PPC::MFVSRWZ)
+ MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
return true;
return false;
// We limit the max depth to track incoming values of PHIs or binary ops
// (e.g. AND) to avoid excessive cost.
-const unsigned MAX_DEPTH = 1;
-
-bool
-PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
- const unsigned Depth) const {
- const MachineFunction *MF = MI.getParent()->getParent();
- const MachineRegisterInfo *MRI = &MF->getRegInfo();
-
- // If we know this instruction returns sign- or zero-extended result,
- // return true.
- if (SignExt ? isSignExtendingOp(MI):
- isZeroExtendingOp(MI))
- return true;
-
- switch (MI.getOpcode()) {
+const unsigned MAX_BINOP_DEPTH = 1;
+// The isSignOrZeroExtended function is recursive. The parameter BinOpDepth
+// does not count all of the recursions. The parameter BinOpDepth is incremented
+// only when isSignOrZeroExtended calls itself more than once. This is done to
+// prevent expontential recursion. There is no parameter to track linear
+// recursion.
+std::pair<bool, bool>
+PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg,
+ const unsigned BinOpDepth,
+ const MachineRegisterInfo *MRI) const {
+ if (!Register::isVirtualRegister(Reg))
+ return std::pair<bool, bool>(false, false);
+
+ MachineInstr *MI = MRI->getVRegDef(Reg);
+ if (!MI)
+ return std::pair<bool, bool>(false, false);
+
+ bool IsSExt = definedBySignExtendingOp(Reg, MRI);
+ bool IsZExt = definedByZeroExtendingOp(Reg, MRI);
+
+ // If we know the instruction always returns sign- and zero-extended result,
+ // return here.
+ if (IsSExt && IsZExt)
+ return std::pair<bool, bool>(IsSExt, IsZExt);
+
+ switch (MI->getOpcode()) {
case PPC::COPY: {
- Register SrcReg = MI.getOperand(1).getReg();
+ Register SrcReg = MI->getOperand(1).getReg();
// In both ELFv1 and v2 ABI, method parameters and the return value
// are sign- or zero-extended.
- if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
- const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
- // We check the ZExt/SExt flags for a method parameter.
- if (MI.getParent()->getBasicBlock() ==
- &MF->getFunction().getEntryBlock()) {
- Register VReg = MI.getOperand(0).getReg();
- if (MF->getRegInfo().isLiveIn(VReg))
- return SignExt ? FuncInfo->isLiveInSExt(VReg) :
- FuncInfo->isLiveInZExt(VReg);
- }
+ const MachineFunction *MF = MI->getMF();
- // For a method return value, we check the ZExt/SExt flags in attribute.
- // We assume the following code sequence for method call.
- // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
- // BL8_NOP @func,...
- // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
- // %5 = COPY %x3; G8RC:%5
- if (SrcReg == PPC::X3) {
- const MachineBasicBlock *MBB = MI.getParent();
- MachineBasicBlock::const_instr_iterator II =
- MachineBasicBlock::const_instr_iterator(&MI);
- if (II != MBB->instr_begin() &&
- (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
- const MachineInstr &CallMI = *(--II);
- if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
- const Function *CalleeFn =
- dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
- if (!CalleeFn)
- return false;
- const IntegerType *IntTy =
- dyn_cast<IntegerType>(CalleeFn->getReturnType());
- const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
- if (IntTy && IntTy->getBitWidth() <= 32)
- return Attrs.hasAttribute(SignExt ? Attribute::SExt :
- Attribute::ZExt);
- }
- }
+ if (!MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
+ // If this is a copy from another register, we recursively check source.
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+ return std::pair<bool, bool>(SrcExt.first || IsSExt,
+ SrcExt.second || IsZExt);
+ }
+
+ // From here on everything is SVR4ABI
+ const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
+ // We check the ZExt/SExt flags for a method parameter.
+ if (MI->getParent()->getBasicBlock() ==
+ &MF->getFunction().getEntryBlock()) {
+ Register VReg = MI->getOperand(0).getReg();
+ if (MF->getRegInfo().isLiveIn(VReg)) {
+ IsSExt |= FuncInfo->isLiveInSExt(VReg);
+ IsZExt |= FuncInfo->isLiveInZExt(VReg);
+ return std::pair<bool, bool>(IsSExt, IsZExt);
}
}
- // If this is a copy from another register, we recursively check source.
- if (!Register::isVirtualRegister(SrcReg))
- return false;
- const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
- if (SrcMI != nullptr)
- return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
+ if (SrcReg != PPC::X3) {
+ // If this is a copy from another register, we recursively check source.
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+ return std::pair<bool, bool>(SrcExt.first || IsSExt,
+ SrcExt.second || IsZExt);
+ }
- return false;
+ // For a method return value, we check the ZExt/SExt flags in attribute.
+ // We assume the following code sequence for method call.
+ // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
+ // BL8_NOP @func,...
+ // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
+ // %5 = COPY %x3; G8RC:%5
+ const MachineBasicBlock *MBB = MI->getParent();
+ std::pair<bool, bool> IsExtendPair = std::pair<bool, bool>(IsSExt, IsZExt);
+ MachineBasicBlock::const_instr_iterator II =
+ MachineBasicBlock::const_instr_iterator(MI);
+ if (II == MBB->instr_begin() || (--II)->getOpcode() != PPC::ADJCALLSTACKUP)
+ return IsExtendPair;
+
+ const MachineInstr &CallMI = *(--II);
+ if (!CallMI.isCall() || !CallMI.getOperand(0).isGlobal())
+ return IsExtendPair;
+
+ const Function *CalleeFn =
+ dyn_cast_if_present<Function>(CallMI.getOperand(0).getGlobal());
+ if (!CalleeFn)
+ return IsExtendPair;
+ const IntegerType *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
+ if (IntTy && IntTy->getBitWidth() <= 32) {
+ const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
+ IsSExt |= Attrs.hasAttribute(Attribute::SExt);
+ IsZExt |= Attrs.hasAttribute(Attribute::ZExt);
+ return std::pair<bool, bool>(IsSExt, IsZExt);
+ }
+
+ return IsExtendPair;
}
- case PPC::ANDI_rec:
- case PPC::ANDIS_rec:
+ // OR, XOR with 16-bit immediate does not change the upper 48 bits.
+ // So, we track the operand register as we do for register copy.
case PPC::ORI:
- case PPC::ORIS:
case PPC::XORI:
- case PPC::XORIS:
- case PPC::ANDI8_rec:
- case PPC::ANDIS8_rec:
case PPC::ORI8:
+ case PPC::XORI8: {
+ unsigned SrcReg = MI->getOperand(1).getReg();
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+ return std::pair<bool, bool>(SrcExt.first || IsSExt,
+ SrcExt.second || IsZExt);
+ }
+
+ // OR, XOR with shifted 16-bit immediate does not change the upper
+ // 32 bits. So, we track the operand register for zero extension.
+ // For sign extension when the MSB of the immediate is zero, we also
+ // track the operand register since the upper 33 bits are unchanged.
+ case PPC::ORIS:
+ case PPC::XORIS:
case PPC::ORIS8:
- case PPC::XORI8:
case PPC::XORIS8: {
- // logical operation with 16-bit immediate does not change the upper bits.
- // So, we track the operand register as we do for register copy.
- Register SrcReg = MI.getOperand(1).getReg();
- if (!Register::isVirtualRegister(SrcReg))
- return false;
- const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
- if (SrcMI != nullptr)
- return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
-
- return false;
+ unsigned SrcReg = MI->getOperand(1).getReg();
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+ uint16_t Imm = MI->getOperand(2).getImm();
+ if (Imm & 0x8000)
+ return std::pair<bool, bool>(false, SrcExt.second || IsZExt);
+ else
+ return std::pair<bool, bool>(SrcExt.first || IsSExt,
+ SrcExt.second || IsZExt);
}
// If all incoming values are sign-/zero-extended,
case PPC::OR8:
case PPC::ISEL:
case PPC::PHI: {
- if (Depth >= MAX_DEPTH)
- return false;
+ if (BinOpDepth >= MAX_BINOP_DEPTH)
+ return std::pair<bool, bool>(false, false);
// The input registers for PHI are operand 1, 3, ...
// The input registers for others are operand 1 and 2.
- unsigned E = 3, D = 1;
- if (MI.getOpcode() == PPC::PHI) {
- E = MI.getNumOperands();
- D = 2;
+ unsigned OperandEnd = 3, OperandStride = 1;
+ if (MI->getOpcode() == PPC::PHI) {
+ OperandEnd = MI->getNumOperands();
+ OperandStride = 2;
}
- for (unsigned I = 1; I != E; I += D) {
- if (MI.getOperand(I).isReg()) {
- Register SrcReg = MI.getOperand(I).getReg();
- if (!Register::isVirtualRegister(SrcReg))
- return false;
- const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
- if (SrcMI == nullptr ||
- !isSignOrZeroExtended(*SrcMI, SignExt, Depth + 1))
- return false;
- }
- else
- return false;
+ IsSExt = true;
+ IsZExt = true;
+ for (unsigned I = 1; I != OperandEnd; I += OperandStride) {
+ if (!MI->getOperand(I).isReg())
+ return std::pair<bool, bool>(false, false);
+
+ unsigned SrcReg = MI->getOperand(I).getReg();
+ auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth + 1, MRI);
+ IsSExt &= SrcExt.first;
+ IsZExt &= SrcExt.second;
}
- return true;
+ return std::pair<bool, bool>(IsSExt, IsZExt);
}
// If at least one of the incoming values of an AND is zero extended
// are sign-extended then the output is also sign extended.
case PPC::AND:
case PPC::AND8: {
- if (Depth >= MAX_DEPTH)
- return false;
-
- assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
-
- Register SrcReg1 = MI.getOperand(1).getReg();
- Register SrcReg2 = MI.getOperand(2).getReg();
-
- if (!Register::isVirtualRegister(SrcReg1) ||
- !Register::isVirtualRegister(SrcReg2))
- return false;
-
- const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
- const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
- if (!MISrc1 || !MISrc2)
- return false;
-
- if(SignExt)
- return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
- isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
- else
- return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
- isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+ if (BinOpDepth >= MAX_BINOP_DEPTH)
+ return std::pair<bool, bool>(false, false);
+
+ unsigned SrcReg1 = MI->getOperand(1).getReg();
+ unsigned SrcReg2 = MI->getOperand(2).getReg();
+ auto Src1Ext = isSignOrZeroExtended(SrcReg1, BinOpDepth + 1, MRI);
+ auto Src2Ext = isSignOrZeroExtended(SrcReg2, BinOpDepth + 1, MRI);
+ return std::pair<bool, bool>(Src1Ext.first && Src2Ext.first,
+ Src1Ext.second || Src2Ext.second);
}
default:
break;
}
- return false;
+ return std::pair<bool, bool>(IsSExt, IsZExt);
}
bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
/// This instruction is an X-Form memory operation.
XFormMemOp = 0x1 << NewDef_Shift,
/// This instruction is prefixed.
- Prefixed = 0x1 << (NewDef_Shift+1)
+ Prefixed = 0x1 << (NewDef_Shift + 1),
+ /// This instruction produced a sign extended result.
+ SExt32To64 = 0x1 << (NewDef_Shift + 2),
+ /// This instruction produced a zero extended result.
+ ZExt32To64 = 0x1 << (NewDef_Shift + 3)
};
} // end namespace PPCII
bool isPrefixed(unsigned Opcode) const {
return get(Opcode).TSFlags & PPCII::Prefixed;
}
+ bool isSExt32To64(unsigned Opcode) const {
+ return get(Opcode).TSFlags & PPCII::SExt32To64;
+ }
+ bool isZExt32To64(unsigned Opcode) const {
+ return get(Opcode).TSFlags & PPCII::ZExt32To64;
+ }
/// Check if Opcode corresponds to a call instruction that should be marked
/// with the NOTOC relocation.
bool isTOCSaveMI(const MachineInstr &MI) const;
- bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
- const unsigned PhiDepth) const;
+ std::pair<bool, bool>
+ isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
+ const MachineRegisterInfo *MRI) const;
- /// Return true if the output of the instruction is always a sign-extended,
- /// i.e. 0 to 31-th bits are same as 32-th bit.
- bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
- return isSignOrZeroExtended(MI, true, depth);
+ // Return true if the register is sign-extended from 32 to 64 bits.
+ bool isSignExtended(const unsigned Reg,
+ const MachineRegisterInfo *MRI) const {
+ return isSignOrZeroExtended(Reg, 0, MRI).first;
}
- /// Return true if the output of the instruction is always zero-extended,
- /// i.e. 0 to 31-th bits are all zeros
- bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
- return isSignOrZeroExtended(MI, false, depth);
+ // Return true if the register is zero-extended from 32 to 64 bits.
+ bool isZeroExtended(const unsigned Reg,
+ const MachineRegisterInfo *MRI) const {
+ return isSignOrZeroExtended(Reg, 0, MRI).second;
}
bool convertToImmediateForm(MachineInstr &MI,
let PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
"lbz $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (zextloadi8 DForm:$src))]>;
+ [(set i32:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
"lha $rD, $src", IIC_LdStLHA,
[(set i32:$rD, (sextloadi16 DForm:$src))]>,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
"lhz $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (zextloadi16 DForm:$src))]>;
+ [(set i32:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
"lwz $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (load DForm:$src))]>;
+ [(set i32:$rD, (load DForm:$src))]>, ZExt32To64;
let Predicates = [HasFPU] in {
def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src),
"lbzx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (zextloadi8 XForm:$src))]>;
+ [(set i32:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src),
"lhax $rD, $src", IIC_LdStLHA,
[(set i32:$rD, (sextloadi16 XForm:$src))]>,
- PPC970_DGroup_Cracked;
+ PPC970_DGroup_Cracked, SExt32To64;
def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src),
"lhzx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (zextloadi16 XForm:$src))]>;
+ [(set i32:$rD, (zextloadi16 XForm:$src))]>, ZExt32To64,
+ SExt32To64;
def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src),
"lwzx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (load XForm:$src))]>;
+ [(set i32:$rD, (load XForm:$src))]>, ZExt32To64;
def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src),
"lhbrx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>;
+ [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>, ZExt32To64;
def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src),
"lwbrx $rD, $src", IIC_LdStLoad,
- [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>;
+ [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>, ZExt32To64;
let Predicates = [HasFPU] in {
def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src),
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
"li $rD, $imm", IIC_IntSimple,
- [(set i32:$rD, imm32SExt16:$imm)]>;
+ [(set i32:$rD, imm32SExt16:$imm)]>, SExt32To64;
def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
"lis $rD, $imm", IIC_IntSimple,
- [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
+ [(set i32:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64;
}
}
def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
"andi. $dst, $src1, $src2", IIC_IntGeneral,
[(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
- isRecordForm;
+ isRecordForm, ZExt32To64, SExt32To64;
def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
"andis. $dst, $src1, $src2", IIC_IntGeneral,
[(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
- isRecordForm;
+ isRecordForm, ZExt32To64;
}
def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
"ori $dst, $src1, $src2", IIC_IntSimple,
} // isCommutable
defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
"slw", "$rA, $rS, $rB", IIC_IntGeneral,
- [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
+ [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>, ZExt32To64;
defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
"srw", "$rA, $rS, $rB", IIC_IntGeneral,
- [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
+ [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>, ZExt32To64;
defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
"sraw", "$rA, $rS, $rB", IIC_IntShift,
- [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
+ [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>, SExt32To64;
}
def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;
let hasSideEffects = 0 in {
defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
"srawi", "$rA, $rS, $SH", IIC_IntShift,
- [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
+ [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>,
+ SExt32To64;
defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
"cntlzw", "$rA, $rS", IIC_IntGeneral,
- [(set i32:$rA, (ctlz i32:$rS))]>;
+ [(set i32:$rA, (ctlz i32:$rS))]>, ZExt32To64;
defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
"cnttzw", "$rA, $rS", IIC_IntGeneral,
- [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
+ [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>,
+ ZExt32To64;
defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
"extsb", "$rA, $rS", IIC_IntSimple,
- [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
+ [(set i32:$rA, (sext_inreg i32:$rS, i8))]>, SExt32To64;
defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
"extsh", "$rA, $rS", IIC_IntSimple,
- [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
+ [(set i32:$rA, (sext_inreg i32:$rS, i16))]>, SExt32To64;
let isCommutable = 1 in
def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
(ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
- (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>,
+ ZExt32To64;
def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
- (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>,
+ ZExt32To64;
def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n",
- (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
+ (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64;
def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
(ins gprc:$rA, gprc:$rS, u5imm:$n)>;
def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA),
- "setb $RT, $BFA", IIC_IntGeneral>;
+ "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64;
} // IsISA3_0
let Predicates = [IsISA3_0] in {
let Predicates = [IsISA3_1] in {
def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI),
- "setbc $RT, $BI", IIC_IntCompare, []>;
+ "setbc $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64, ZExt32To64;
def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI),
- "setbcr $RT, $BI", IIC_IntCompare, []>;
+ "setbcr $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64, ZExt32To64;
def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI),
- "setnbc $RT, $BI", IIC_IntCompare, []>;
+ "setnbc $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64;
def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI),
- "setnbcr $RT, $BI", IIC_IntCompare, []>;
+ "setnbcr $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI),
- "setbc $RT, $BI", IIC_IntCompare, []>;
+ "setbc $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64, ZExt32To64;
def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI),
- "setbcr $RT, $BI", IIC_IntCompare, []>;
+ "setbcr $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64, ZExt32To64;
def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI),
- "setnbc $RT, $BI", IIC_IntCompare, []>;
+ "setnbc $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64;
def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI),
- "setnbcr $RT, $BI", IIC_IntCompare, []>;
+ "setnbcr $RT, $BI", IIC_IntCompare, []>,
+ SExt32To64;
}
def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB),
"vextractbm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
- (int_ppc_altivec_vextractbm v16i8:$vB))]>;
+ (int_ppc_altivec_vextractbm v16i8:$vB))]>,
+ ZExt32To64;
def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB),
"vextracthm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
- (int_ppc_altivec_vextracthm v8i16:$vB))]>;
+ (int_ppc_altivec_vextracthm v8i16:$vB))]>,
+ ZExt32To64;
def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB),
"vextractwm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
- (int_ppc_altivec_vextractwm v4i32:$vB))]>;
+ (int_ppc_altivec_vextractwm v4i32:$vB))]>,
+ ZExt32To64;
def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB),
"vextractdm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
- (int_ppc_altivec_vextractdm v2i64:$vB))]>;
+ (int_ppc_altivec_vextractdm v2i64:$vB))]>,
+ ZExt32To64;
def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB),
"vextractqm $rD, $vB", IIC_VecGeneral,
[(set i32:$rD,
Requires<[In64BitMode]>;
def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
"mfvsrwz $rA, $XT", IIC_VecGeneral,
- [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
+ [(set i32:$rA, (PPCmfvsr f64:$XT))]>, ZExt32To64;
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
let isCodeGenOnly = 1, hasSideEffects = 1 in
def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
static cl::opt<bool>
EnableSExtElimination("ppc-eliminate-signext",
cl::desc("enable elimination of sign-extensions"),
- cl::init(false), cl::Hidden);
+ cl::init(true), cl::Hidden);
static cl::opt<bool>
EnableZExtElimination("ppc-eliminate-zeroext",
cl::desc("enable elimination of zero-extensions"),
- cl::init(false), cl::Hidden);
+ cl::init(true), cl::Hidden);
static cl::opt<bool>
EnableTrapOptimization("ppc-opt-conditional-trap",
// This function returns number of known zero bits in output of MI
// starting from the most significant bit.
-static unsigned
-getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
+static unsigned getKnownLeadingZeroCount(const unsigned Reg,
+ const PPCInstrInfo *TII,
+ const MachineRegisterInfo *MRI) {
+ MachineInstr *MI = MRI->getVRegDef(Reg);
unsigned Opcode = MI->getOpcode();
if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec)
Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
return 56;
- if (TII->isZeroExtended(*MI))
+ if (TII->isZeroExtended(Reg, MRI))
return 32;
return 0;
SrcMI->getOpcode() == PPC::LHZX) {
if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
break;
- auto is64Bit = [] (unsigned Opcode) {
- return Opcode == PPC::EXTSH8;
+ auto is64Bit = [](unsigned Opcode) {
+ return Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSH8_32_64;
};
auto isXForm = [] (unsigned Opcode) {
return Opcode == PPC::LHZX;
};
unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
isXForm(SrcMI->getOpcode()));
+
LLVM_DEBUG(dbgs() << "Zero-extending load\n");
LLVM_DEBUG(SrcMI->dump());
LLVM_DEBUG(dbgs() << "and sign-extension\n");
if (isXForm) return PPC::LWAX_32;
else return PPC::LWA_32;
};
+
+ // The transformation from a zero-extending load to a sign-extending
+ // load is only legal when the displacement is a multiple of 4.
+ // If the displacement is not at least 4 byte aligned, don't perform
+ // the transformation.
+ bool IsWordAligned = false;
+ if (SrcMI->getOperand(1).isGlobal()) {
+ const GlobalObject *GO =
+ dyn_cast<GlobalObject>(SrcMI->getOperand(1).getGlobal());
+ if (GO && GO->getAlignment() >= 4)
+ IsWordAligned = true;
+ } else if (SrcMI->getOperand(1).isImm()) {
+ int64_t Value = SrcMI->getOperand(1).getImm();
+ if (Value % 4 == 0)
+ IsWordAligned = true;
+ }
+
unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
isXForm(SrcMI->getOpcode()));
+
+ if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))
+ break;
+
LLVM_DEBUG(dbgs() << "Zero-extending load\n");
LLVM_DEBUG(SrcMI->dump());
LLVM_DEBUG(dbgs() << "and sign-extension\n");
Simplified = true;
NumEliminatedSExt++;
} else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
- TII->isSignExtended(*SrcMI)) {
+ TII->isSignExtended(NarrowReg, MRI)) {
// We can eliminate EXTSW if the input is known to be already
// sign-extended.
LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
if (Register::isVirtualRegister(CopyReg))
SrcMI = MRI->getVRegDef(CopyReg);
}
+ if (!SrcMI->getOperand(0).isReg())
+ break;
- unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
+ unsigned KnownZeroCount =
+ getKnownLeadingZeroCount(SrcMI->getOperand(0).getReg(), TII, MRI);
if (MI.getOperand(3).getImm() <= KnownZeroCount) {
LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
; ASM32PWR4-DAG: lwz [[REG10:[0-9]+]], 92(1)
; ASM64PWR4-DAG: ld [[REG1:[0-9]+]], 112(1)
-; ASM64PWR4-DAG: lwz [[REG2:[0-9]+]], 124(1)
+; ASM64PWR4-DAG: lwa [[REG2:[0-9]+]], 124(1)
; ASM64PWR4-DAG: lwz [[REG3:[0-9]+]], 132(1)
; ASM64PWR4-DAG: lwz [[REG4:[0-9]+]], 140(1)
; ASM64PWR4-DAG: lwa [[REG5:[0-9]+]], 148(1)
; CHECK-LABEL: ld_0_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
; CHECK-LABEL: ld_align16_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int16_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint8_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int16_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int16_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_int16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int16_t_uint8_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
; CHECK-LABEL: ld_0_uint16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
; CHECK-LABEL: ld_align16_uint16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint16_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint8_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
; CHECK-LABEL: ld_0_uint16_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
; CHECK-LABEL: ld_align16_uint16_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint16_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint16_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint16_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
; CHECK-LABEL: ld_0_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
; CHECK-LABEL: ld_align16_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int32_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint8_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_int32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint8_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
; CHECK-LABEL: ld_0_int32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
; CHECK-LABEL: ld_align16_int32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int32_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_int32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint16_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_int32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint16_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
define dso_local signext i32 @ld_0_int32_t_uint32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
define dso_local signext i32 @ld_align16_int32_t_uint32_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 8(r3)
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int32_t_uint32_t:
; CHECK-PREP10-NEXT: lis r4, 3725
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
define dso_local signext i32 @ld_reg_int32_t_uint32_t(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwax r3, r3, r4
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-LABEL: ld_or_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-LABEL: ld_not_disjoint16_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-LABEL: ld_disjoint_align16_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
-; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 24(r3)
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
-; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: extsw r3, r3
+; CHECK-P9-NEXT: lwax r3, r3, r4
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint32_t:
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
-; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: extsw r3, r3
+; CHECK-P8-NEXT: lwax r3, r3, r4
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint32_t:
; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint32_t:
; CHECK-PREP10-NEXT: rldicr r3, r3, 0, 23
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
define dso_local signext i32 @ld_cst_align16_int32_t_uint32_t() {
; CHECK-LABEL: ld_cst_align16_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 4080(0)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
; CHECK-LABEL: ld_cst_align32_int32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
-; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, -27108(r3)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint32_t:
; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
; CHECK-LABEL: ld_0_uint32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
; CHECK-LABEL: ld_align16_uint32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint32_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint8_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
; CHECK-LABEL: ld_0_uint32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
; CHECK-LABEL: ld_align16_uint32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint32_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint16_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
define dso_local zeroext i32 @ld_0_uint32_t_int16_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 0(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
define dso_local zeroext i32 @ld_align16_uint32_t_int16_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 8(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
-; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lhax r3, r3, r4
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: extsh r3, r3
+; CHECK-P10-NEXT: lhax r3, r3, r4
; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-NEXT: lis r4, 3725
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lhax r3, r3, r4
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
define dso_local zeroext i32 @ld_reg_uint32_t_int16_t(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lhax r3, r3, r4
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK-LABEL: ld_or_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 0(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK-LABEL: ld_not_disjoint16_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
-; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 0(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK-LABEL: ld_disjoint_align16_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
-; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 24(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
-; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 0(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
-; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: extsh r3, r3
+; CHECK-P9-NEXT: lhax r3, r3, r4
; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
-; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: extsh r3, r3
+; CHECK-P8-NEXT: lhax r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
-; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: extsh r3, r3
+; CHECK-P10-NEXT: lha r3, 0(r3)
; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
-; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lha r3, 0(r3)
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: extsh r3, r3
+; CHECK-P10-NEXT: lhax r3, r3, r4
; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-NEXT: rldicr r3, r3, 0, 23
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lhax r3, r3, r4
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
define dso_local zeroext i32 @ld_cst_align16_uint32_t_int16_t() {
; CHECK-LABEL: ld_cst_align16_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, 4080(0)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK-LABEL: ld_cst_align32_uint32_t_int16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
-; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: extsh r3, r3
+; CHECK-NEXT: lha r3, -27108(r3)
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
-; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: extsh r3, r3
+; CHECK-P10-NEXT: lha r3, 0(r3)
; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsh r3, r3
+; CHECK-PREP10-NEXT: lha r3, 0(r3)
; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
; CHECK-LABEL: ld_0_uint32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
; CHECK-LABEL: ld_align16_uint32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint32_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint32_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint32_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
; CHECK-LABEL: ld_0_int64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
; CHECK-LABEL: ld_align16_int64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int64_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_int64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint8_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_int64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint8_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
; CHECK-LABEL: ld_0_int64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
; CHECK-LABEL: ld_align16_int64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int64_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_int64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint16_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_int64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint16_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
; CHECK-LABEL: ld_0_int64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
; CHECK-LABEL: ld_align16_int64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int64_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_int64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint32_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_int64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint32_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
define dso_local i64 @ld_0_int64_t_int32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
define dso_local i64 @ld_align16_int64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 8(r3)
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_int64_t_int32_t:
; CHECK-PREP10-NEXT: lis r4, 3725
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
define dso_local i64 @ld_reg_int64_t_int32_t(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwax r3, r3, r4
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-LABEL: ld_or_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-LABEL: ld_not_disjoint16_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-LABEL: ld_disjoint_align16_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
-; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 24(r3)
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
-; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: extsw r3, r3
+; CHECK-P9-NEXT: lwax r3, r3, r4
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_int32_t:
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
-; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: extsw r3, r3
+; CHECK-P8-NEXT: lwax r3, r3, r4
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_int32_t:
; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_int32_t:
; CHECK-PREP10-NEXT: rldicr r3, r3, 0, 23
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
define dso_local i64 @ld_cst_align16_int64_t_int32_t() {
; CHECK-LABEL: ld_cst_align16_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 4080(0)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
; CHECK-LABEL: ld_cst_align32_int64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
-; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, -27108(r3)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_int32_t:
; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
; CHECK-LABEL: ld_0_uint64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
; CHECK-LABEL: ld_align16_uint64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint8_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint64_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint8_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
; CHECK-LABEL: ld_0_uint64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i16*
; CHECK-LABEL: ld_align16_uint64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lhz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lhz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lhzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint16_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lhzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lhzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint16_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lhzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint64_t_uint16_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lhz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lhz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint16_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lhz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
; CHECK-LABEL: ld_0_uint64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
; CHECK-LABEL: ld_align16_uint64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint32_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint32_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint64_t_uint32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint32_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
define dso_local i64 @ld_0_uint64_t_int32_t(i64 %ptr) {
; CHECK-LABEL: ld_0_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i32*
define dso_local i64 @ld_align16_uint64_t_int32_t(i8* nocapture readonly %ptr) {
; CHECK-LABEL: ld_align16_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 8(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 8(r3)
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10: # %bb.0: # %entry
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint64_t_int32_t:
; CHECK-PREP10-NEXT: lis r4, 3725
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
define dso_local i64 @ld_reg_uint64_t_int32_t(i8* nocapture readonly %ptr, i64 %off) {
; CHECK-LABEL: ld_reg_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwzx r3, r3, r4
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwax r3, r3, r4
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-LABEL: ld_or_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-LABEL: ld_not_disjoint16_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-LABEL: ld_disjoint_align16_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
-; CHECK-NEXT: lwz r3, 24(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 24(r3)
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
-; CHECK-NEXT: lwz r3, 0(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 0(r3)
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: and r3, r3, r4
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
-; CHECK-P9-NEXT: lwzx r3, r3, r4
-; CHECK-P9-NEXT: extsw r3, r3
+; CHECK-P9-NEXT: lwax r3, r3, r4
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_int32_t:
; CHECK-P8-NEXT: lis r5, 15258
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
-; CHECK-P8-NEXT: lwzx r3, r3, r4
-; CHECK-P8-NEXT: extsw r3, r3
+; CHECK-P8-NEXT: lwax r3, r3, r4
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: pli r5, 3567587329
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_int32_t:
; CHECK-PREP10-NEXT: oris r4, r4, 54437
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
-; CHECK-P10-NEXT: lwzx r3, r3, r4
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwax r3, r3, r4
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_int32_t:
; CHECK-PREP10-NEXT: rldicr r3, r3, 0, 23
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT: lwzx r3, r3, r4
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwax r3, r3, r4
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
define dso_local i64 @ld_cst_align16_uint64_t_int32_t() {
; CHECK-LABEL: ld_cst_align16_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lwz r3, 4080(0)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, 4080(0)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
; CHECK-LABEL: ld_cst_align32_uint64_t_int32_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
-; CHECK-NEXT: lwz r3, -27108(r3)
-; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: lwa r3, -27108(r3)
; CHECK-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
; CHECK-P10: # %bb.0: # %entry
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
-; CHECK-P10-NEXT: lwz r3, 0(r3)
-; CHECK-P10-NEXT: extsw r3, r3
+; CHECK-P10-NEXT: lwa r3, 0(r3)
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_int32_t:
; CHECK-PREP10-NEXT: lis r3, 3725
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT: lwz r3, 0(r3)
-; CHECK-PREP10-NEXT: extsw r3, r3
+; CHECK-PREP10-NEXT: lwa r3, 0(r3)
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
; CHECK-LABEL: ld_0_uint8_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to i8*
; CHECK-LABEL: ld_align16_uint8_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 8(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-PREP10-NEXT: lis r4, 1525
; CHECK-PREP10-NEXT: ori r4, r4, 56600
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: pli r4, 244140625
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint8_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-LABEL: ld_reg_uint8_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbzx r3, r3, r4
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori r3, r3, 6
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rldicr r3, r3, 0, 51
; CHECK-NEXT: lbz r3, 24(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: ori r3, r3, 34463
; CHECK-NEXT: oris r3, r3, 1
; CHECK-NEXT: lbz r3, 0(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P9-NEXT: lis r4, 15258
; CHECK-P9-NEXT: ori r4, r4, 41712
; CHECK-P9-NEXT: lbzx r3, r3, r4
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
; CHECK-P8-NEXT: and r3, r3, r4
; CHECK-P8-NEXT: ori r4, r5, 41712
; CHECK-P8-NEXT: lbzx r3, r3, r4
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: rldimi r5, r4, 32, 0
; CHECK-P10-NEXT: or r3, r3, r5
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 4097
; CHECK-PREP10-NEXT: or r3, r3, r4
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: rldicr r3, r3, 0, 23
; CHECK-P10-NEXT: rldic r4, r4, 12, 24
; CHECK-P10-NEXT: lbzx r3, r3, r4
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_uint8_t:
; CHECK-PREP10-NEXT: ori r4, r4, 19025
; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24
; CHECK-PREP10-NEXT: lbzx r3, r3, r4
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-LABEL: ld_cst_align16_uint8_t_uint8_t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lbz r3, 4080(0)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis r3, 153
; CHECK-NEXT: lbz r3, -27108(r3)
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
; CHECK-P10-NEXT: pli r3, 244140625
; CHECK-P10-NEXT: rldic r3, r3, 12, 24
; CHECK-P10-NEXT: lbz r3, 0(r3)
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_uint8_t:
; CHECK-PREP10-NEXT: ori r3, r3, 19025
; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24
; CHECK-PREP10-NEXT: lbz r3, 0(r3)
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v2, 0
; CHECK-NEXT: setbc r3, 4*cr6+un
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_invalid:
; CHECK-P9-NEXT: bcdsub. v2, v2, v2, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 6, <16 x i8> %a, <16 x i8> %a) #2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdadd. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+un
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_add_ofl:
; CHECK-P9-NEXT: bcdadd. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdadd.p(i32 6, <16 x i8> %a, <16 x i8> %b) #2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+un
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_sub_ofl:
; CHECK-P9-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 6, <16 x i8> %a, <16 x i8> %b) #2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+lt
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmplt:
; CHECK-P9-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 25, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 2, <16 x i8> %a, <16 x i8> %b) #2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+gt
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmpgt:
; CHECK-P9-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 26, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 4, <16 x i8> %a, <16 x i8> %b) #2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbc r3, 4*cr6+eq
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmpeq:
; CHECK-P9-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 27, 31, 31
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 0, <16 x i8> %a, <16 x i8> %b) #2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbcr r3, 4*cr6+lt
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmpge:
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 25, 31, 31
; CHECK-P9-NEXT: xori r3, r3, 1
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 3, <16 x i8> %a, <16 x i8> %b) #2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsub. v2, v2, v3, 0
; CHECK-NEXT: setbcr r3, 4*cr6+gt
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P9-LABEL: test_cmple:
; CHECK-P9-NEXT: mfocrf r3, 2
; CHECK-P9-NEXT: rlwinm r3, r3, 26, 31, 31
; CHECK-P9-NEXT: xori r3, r3, 1
-; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: blr
entry:
%0 = tail call i32 @llvm.ppc.bcdsub.p(i32 5, <16 x i8> %a, <16 x i8> %b) #2
; CHECK-PWR9-NEXT: bl callNonVoid
; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: .LBB1_3: # %return
-; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: addi r1, r1, 48
; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: nop
; CHECK-NEXT: .LBB1_3: # %return
; CHECK-NEXT: ld r30, 112(r1) # 8-byte Folded Reload
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: addi r1, r1, 128
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-PWR9-NEXT: beq cr0, .LBB2_2
; CHECK-PWR9-NEXT: # %bb.1: # %land.rhs
; CHECK-PWR9-NEXT: mr r29, r3
-; CHECK-PWR9-NEXT: clrldi r4, r4, 32
; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl bar
; CHECK-PWR9-NEXT: nop
; CHECK-NEXT: beq cr0, .LBB2_2
; CHECK-NEXT: # %bb.1: # %land.rhs
; CHECK-NEXT: mr r29, r3
-; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: mr r3, r30
; CHECK-NEXT: bl bar
; CHECK-NEXT: nop
; CHECK-NEXT: cmplwi r3, 0
; CHECK-NEXT: beqlr cr0
; CHECK-NEXT: # %bb.1: # %for.body.lr.ph
-; CHECK-NEXT: clrldi r6, r3, 32
-; CHECK-NEXT: addi r3, r4, 64
-; CHECK-NEXT: addi r4, r5, 64
-; CHECK-NEXT: mtctr r6
+; CHECK-NEXT: addi r4, r4, 64
+; CHECK-NEXT: addi r5, r5, 64
+; CHECK-NEXT: mtctr r3
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: #
-; CHECK-NEXT: lxvp vsp34, -64(r3)
-; CHECK-NEXT: lxvp vsp36, -32(r3)
-; CHECK-NEXT: lxvp vsp32, 0(r3)
-; CHECK-NEXT: lxvp vsp38, 32(r3)
-; CHECK-NEXT: addi r3, r3, 1
-; CHECK-NEXT: stxvp vsp34, -64(r4)
-; CHECK-NEXT: stxvp vsp36, -32(r4)
-; CHECK-NEXT: stxvp vsp32, 0(r4)
-; CHECK-NEXT: stxvp vsp38, 32(r4)
+; CHECK-NEXT: lxvp vsp34, -64(r4)
+; CHECK-NEXT: lxvp vsp36, -32(r4)
+; CHECK-NEXT: lxvp vsp32, 0(r4)
+; CHECK-NEXT: lxvp vsp38, 32(r4)
; CHECK-NEXT: addi r4, r4, 1
+; CHECK-NEXT: stxvp vsp34, -64(r5)
+; CHECK-NEXT: stxvp vsp36, -32(r5)
+; CHECK-NEXT: stxvp vsp32, 0(r5)
+; CHECK-NEXT: stxvp vsp38, 32(r5)
+; CHECK-NEXT: addi r5, r5, 1
; CHECK-NEXT: bdnz .LBB0_2
; CHECK-NEXT: # %bb.3: # %for.cond.cleanup
; CHECK-NEXT: blr
; CHECK-BE-NEXT: cmplwi r3, 0
; CHECK-BE-NEXT: beqlr cr0
; CHECK-BE-NEXT: # %bb.1: # %for.body.lr.ph
-; CHECK-BE-NEXT: clrldi r6, r3, 32
-; CHECK-BE-NEXT: addi r3, r4, 64
-; CHECK-BE-NEXT: addi r4, r5, 64
-; CHECK-BE-NEXT: mtctr r6
+; CHECK-BE-NEXT: addi r4, r4, 64
+; CHECK-BE-NEXT: addi r5, r5, 64
+; CHECK-BE-NEXT: mtctr r3
; CHECK-BE-NEXT: .p2align 4
; CHECK-BE-NEXT: .LBB0_2: # %for.body
; CHECK-BE-NEXT: #
-; CHECK-BE-NEXT: lxvp vsp34, -64(r3)
-; CHECK-BE-NEXT: lxvp vsp36, -32(r3)
-; CHECK-BE-NEXT: lxvp vsp32, 0(r3)
-; CHECK-BE-NEXT: lxvp vsp38, 32(r3)
-; CHECK-BE-NEXT: addi r3, r3, 1
-; CHECK-BE-NEXT: stxvp vsp34, -64(r4)
-; CHECK-BE-NEXT: stxvp vsp36, -32(r4)
-; CHECK-BE-NEXT: stxvp vsp32, 0(r4)
-; CHECK-BE-NEXT: stxvp vsp38, 32(r4)
+; CHECK-BE-NEXT: lxvp vsp34, -64(r4)
+; CHECK-BE-NEXT: lxvp vsp36, -32(r4)
+; CHECK-BE-NEXT: lxvp vsp32, 0(r4)
+; CHECK-BE-NEXT: lxvp vsp38, 32(r4)
; CHECK-BE-NEXT: addi r4, r4, 1
+; CHECK-BE-NEXT: stxvp vsp34, -64(r5)
+; CHECK-BE-NEXT: stxvp vsp36, -32(r5)
+; CHECK-BE-NEXT: stxvp vsp32, 0(r5)
+; CHECK-BE-NEXT: stxvp vsp38, 32(r5)
+; CHECK-BE-NEXT: addi r5, r5, 1
; CHECK-BE-NEXT: bdnz .LBB0_2
; CHECK-BE-NEXT: # %bb.3: # %for.cond.cleanup
; CHECK-BE-NEXT: blr
; CHECK-LABEL: @testComplexISEL
; CHECK: cmplwi r3, 0
; CHECK: li r3, 1
-; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]]
-; CHECK: clrldi r3, r3, 32
-; CHECK: blr
-; CHECK: [[TGT]]
+; CHECK: bnelr cr0
; CHECK: xor [[XOR:r[0-9]+]]
; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
; CHECK-P8-NEXT: xscvdpuxws f0, f1
; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpuxws f0, f1
; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uw:
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uw_03:
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uhw:
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uhw_03:
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2ub:
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2ub_03:
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca float, align 4
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca double, align 8
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca float, align 4
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca double, align 8
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca float, align 4
; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca double, align 8
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca float, align 4
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%arg.addr = alloca double, align 8
; P9: # %bb.0: # %entry
; P9-NEXT: xscvqpuwz v2, v2
; P9-NEXT: mfvsrwz r3, v2
-; P9-NEXT: clrldi r3, r3, 32
; P9-NEXT: blr
;
; NOVSX-LABEL: q_to_u32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; NOVSX-LABEL: d_to_u32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; NOVSX-LABEL: f_to_u32:
; CHECK-NEXT: vcmpgtsw. 2, 4, 3
; CHECK-NEXT: mfocrf 3, 2
; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31
-; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: li 3, 0
; CHECK-AIX-64-NEXT: vcmpgtsw. 2, 4, 3
; CHECK-AIX-64-NEXT: mfocrf 3, 2
; CHECK-AIX-64-NEXT: rlwinm 3, 3, 25, 31, 31
-; CHECK-AIX-64-NEXT: clrldi 3, 3, 32
; CHECK-AIX-64-NEXT: blr
; CHECK-AIX-64-NEXT: L..BB0_2:
; CHECK-AIX-64-NEXT: li 3, 0
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: addi r6, r3, 5
; CHECK-NEXT: addi r3, r4, -1
-; CHECK-NEXT: extsw r5, r5
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: mtctr r3
; CHECK-NEXT: cmpwi r4, 1
; CHECK-NEXT: blt cr0, .LBB1_4
; CHECK-NEXT: # %bb.1: # %for.body.preheader
-; CHECK-NEXT: extsw r5, r5
; CHECK-NEXT: sub r3, r3, r5
; CHECK-NEXT: addi r6, r3, 1000
; CHECK-NEXT: addi r3, r4, -1
; CHECK-P9-NEXT: bge cr0, .LBB1_7
; CHECK-P9-NEXT: .LBB1_4: # %while.cond
; CHECK-P9-NEXT: #
-; CHECK-P9-NEXT: extsw r3, r29
+; CHECK-P9-NEXT: mr r3, r29
; CHECK-P9-NEXT: bl bar
; CHECK-P9-NEXT: nop
; CHECK-P9-NEXT: mr r29, r3
-; CHECK-P9-NEXT: extsw r3, r30
+; CHECK-P9-NEXT: mr r3, r30
; CHECK-P9-NEXT: bl bar
; CHECK-P9-NEXT: nop
; CHECK-P9-NEXT: mr r30, r3
; CHECK-NEXT: ld 4, 8(4)
; CHECK-NEXT: cmpld 3, 4
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: beq 0, .LBB1_3
+; CHECK-NEXT: beqlr 0
; CHECK-NEXT: .LBB1_2: # %res_block
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: .LBB1_3: # %endblock
-; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
%call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16)
%not.tobool = icmp ne i32 %call, 0
; CHECK-NEXT: lbz 4, 6(4)
; CHECK-NEXT: cmplw 3, 4
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: beq 0, .LBB2_4
+; CHECK-NEXT: beqlr 0
; CHECK-NEXT: .LBB2_3: # %res_block
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: .LBB2_4: # %endblock
-; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
%call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7)
%not.lnot = icmp ne i32 %call, 0
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpw 3, 4
-; CHECK-NEXT: iselgt 6, 3, 4
-; CHECK-NEXT: sub 4, 3, 4
-; CHECK-NEXT: extsw 3, 6
-; CHECK-NEXT: stw 4, 0(5)
+; CHECK-NEXT: sub 6, 3, 4
+; CHECK-NEXT: iselgt 3, 3, 4
+; CHECK-NEXT: stw 6, 0(5)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foo:
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: cmpw 3, 4
+; CHECK-NO-ISEL-NEXT: sub 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB0_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT: ori 6, 4, 0
-; CHECK-NO-ISEL-NEXT: b .LBB0_3
+; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
+; CHECK-NO-ISEL-NEXT: b .LBB0_2
; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry
-; CHECK-NO-ISEL-NEXT: addi 6, 3, 0
-; CHECK-NO-ISEL-NEXT: .LBB0_3: # %entry
-; CHECK-NO-ISEL-NEXT: sub 4, 3, 4
-; CHECK-NO-ISEL-NEXT: extsw 3, 6
-; CHECK-NO-ISEL-NEXT: stw 4, 0(5)
+; CHECK-NO-ISEL-NEXT: stw 6, 0(5)
; CHECK-NO-ISEL-NEXT: blr
entry:
%sub = sub nsw i32 %a, %b
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 8, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc0:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: clrldi r3, r3, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc0:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 8, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 0
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 16, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc1:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 56, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc1:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 16, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 24, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc2:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 48, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc2:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 24, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 32, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc3:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 40, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc3:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 32, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 40, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc4:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 32, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc4:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 40, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 48, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc5:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 24, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc5:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 48, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 5
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 56, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc6:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 16, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc6:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 56, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: clrldi r3, r3, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc7:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 8, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc7:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: clrldi 3, 3, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 7
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 8, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc8:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: clrldi r3, r3, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc8:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 8, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 8
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 16, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc9:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 56, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc9:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 16, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 9
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 24, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc10:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 48, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc10:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 24, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 10
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 32, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc11:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 40, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc11:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 32, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 11
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 40, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc12:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 32, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc12:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 40, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 12
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 48, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc13:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 24, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc13:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 48, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 13
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 56, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc14:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 16, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc14:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 56, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 14
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: clrldi r3, r3, 56
-; CHECK-NEXT: clrldi r3, r3, 56
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getuc15:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 8, 56
-; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getuc15:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: clrldi 3, 3, 56
-; CHECK-AIX-NEXT: clrldi 3, 3, 56
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <16 x i8> %vuc, i32 15
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 16, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus0:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: clrldi r3, r3, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus0:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 16, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 0
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 32, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus1:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 48, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus1:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 32, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: rldicl r3, r3, 48, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus2:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 32, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus2:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: rldicl 3, 3, 48, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: clrldi r3, r3, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus3:
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprd r3, f0
; CHECK-LE-NEXT: rldicl r3, r3, 16, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus3:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrd 3, 34
; CHECK-AIX-NEXT: clrldi 3, 3, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 3
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 16, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus4:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: clrldi r3, r3, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus4:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 16, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 4
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 32, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus5:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 48, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus5:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 32, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 5
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: rldicl r3, r3, 48, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus6:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 32, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus6:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: rldicl 3, 3, 48, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 6
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: clrldi r3, r3, 48
-; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getus7:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrd r3, v2
; CHECK-LE-NEXT: rldicl r3, r3, 16, 48
-; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getus7:
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprd 3, 0
; CHECK-AIX-NEXT: clrldi 3, 3, 48
-; CHECK-AIX-NEXT: clrldi 3, 3, 48
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <8 x i16> %vus, i32 7
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getui0:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xxswapd vs0, v2
; CHECK-LE-NEXT: mffprwz r3, f0
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getui0:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: xxsldwi 0, 34, 34, 3
; CHECK-AIX-NEXT: mffprwz 3, 0
-; CHECK-AIX-NEXT: clrldi 3, 3, 32
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %vui, i32 0
; CHECK-LABEL: getui1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfvsrwz r3, v2
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getui1:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-LE-NEXT: mffprwz r3, f0
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getui1:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mfvsrwz 3, 34
-; CHECK-AIX-NEXT: clrldi 3, 3, 32
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %vui, i32 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getui2:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mfvsrwz r3, v2
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getui2:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: xxsldwi 0, 34, 34, 1
; CHECK-AIX-NEXT: mffprwz 3, 0
-; CHECK-AIX-NEXT: clrldi 3, 3, 32
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %vui, i32 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-LE-LABEL: getui3:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-LE-NEXT: mffprwz r3, f0
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-AIX-LABEL: getui3:
; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: xxswapd 0, 34
; CHECK-AIX-NEXT: mffprwz 3, 0
-; CHECK-AIX-NEXT: clrldi 3, 3, 32
; CHECK-AIX-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %vui, i32 3
; CHECK-LABEL: limit_loop
; CHECK: mtctr
; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK: bdnz
+; CHECK: bdzlr
; CHECK: blr
}
; CHECK: # %bb.0:
; CHECK-NEXT: cmpd r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-PWR8-LABEL: setb27:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpd r3, r4
; CHECK-NEXT: setb r3, cr0
-; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-PWR8-LABEL: setb28:
; CHECK-PWR8-NEXT: extsb r4, r4
; CHECK-PWR8-NEXT: extsb r3, r3
; CHECK-PWR8-NEXT: li r5, -1
-; CHECK-PWR8-NEXT: extsw r4, r4
-; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: sub r6, r4, r3
; CHECK-PWR8-NEXT: cmpw r3, r4
; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63
; CHECK-PWR8-NEXT: extsb r4, r4
; CHECK-PWR8-NEXT: extsb r3, r3
; CHECK-PWR8-NEXT: li r5, -1
-; CHECK-PWR8-NEXT: extsw r4, r4
-; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: sub r6, r4, r3
; CHECK-PWR8-NEXT: cmpw r4, r3
; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63
; CHECK-PWR8-NEXT: li r5, -1
; CHECK-PWR8-NEXT: srawi r4, r4, 28
; CHECK-PWR8-NEXT: srawi r3, r3, 28
-; CHECK-PWR8-NEXT: extsw r4, r4
-; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: sub r6, r4, r3
; CHECK-PWR8-NEXT: cmpw r3, r4
; CHECK-PWR8-NEXT: rldicl r3, r6, 1, 63
; PPC64LE-NEXT: nop
; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: .LBB3_1: # %return
-; PPC64LE-NEXT: extsw r3, r3
; PPC64LE-NEXT: addi r1, r1, 32
; PPC64LE-NEXT: ld r0, 16(r1)
; PPC64LE-NEXT: mtlr r0
; PPC64BE-NEXT: nop
; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: .LBB3_1: # %return
-; PPC64BE-NEXT: extsw r3, r3
; PPC64BE-NEXT: addi r1, r1, 48
; PPC64BE-NEXT: ld r0, 16(r1)
; PPC64BE-NEXT: mtlr r0
; PPC64LE-NEXT: nop
; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: # %bb.1: # %return
-; PPC64LE-NEXT: extsw r3, r3
; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB4_2: # Block address taken
; PPC64LE-NEXT: # %return_early
; PPC64LE-NEXT: # Label of block must be emitted
; PPC64LE-NEXT: li r3, 0
-; PPC64LE-NEXT: extsw r3, r3
; PPC64LE-NEXT: blr
;
; PPC64BE-LABEL: ClobberR5_BR:
; PPC64BE-NEXT: nop
; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: # %bb.1: # %return
-; PPC64BE-NEXT: extsw r3, r3
; PPC64BE-NEXT: blr
; PPC64BE-NEXT: .LBB4_2: # Block address taken
; PPC64BE-NEXT: # %return_early
; PPC64BE-NEXT: # Label of block must be emitted
; PPC64BE-NEXT: li r3, 0
-; PPC64BE-NEXT: extsw r3, r3
; PPC64BE-NEXT: blr
entry:
callbr void asm sideeffect "nop", "!i,~{r5}"()
; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
-; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: li r4, 0
; CHECK-NEXT: # %bb.1: # %bb9
; CHECK-NEXT: bl test5
; CHECK-NEXT: nop
-; CHECK-NEXT: rlwinm r3, r3, 8, 16, 23
+; CHECK-NEXT: rlwinm r4, r3, 8, 16, 23
; CHECK-NEXT: # %bb.2: # %bb12
-; CHECK-NEXT: clrldi r4, r3, 32
; CHECK-NEXT: bl test3
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32
; CHECK-LE-NEXT: xsmuldp f0, f0, f1
; CHECK-LE-NEXT: xscvdpsxws f0, f0
; CHECK-LE-NEXT: mffprwz r3, f0
-; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: _Z1f1c:
; CHECK-BE-NEXT: fctiwz f0, f0
; CHECK-BE-NEXT: stfd f0, -8(r1)
; CHECK-BE-NEXT: lwz r3, -4(r1)
-; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: blr
entry:
%0 = and i24 %g.coerce, 255
; CHECK-P9-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
; CHECK-P9-NEXT: extswsli r5, r5, 3
; CHECK-P9-NEXT: extsw r10, r4
+; CHECK-P9-NEXT: lwa r4, 0(r7)
; CHECK-P9-NEXT: add r5, r8, r5
-; CHECK-P9-NEXT: clrldi r8, r3, 32
-; CHECK-P9-NEXT: lwa r3, 0(r7)
-; CHECK-P9-NEXT: addi r4, r8, 1
-; CHECK-P9-NEXT: addi r5, r5, -8
-; CHECK-P9-NEXT: lxvdsx vs0, 0, r5
-; CHECK-P9-NEXT: sub r3, r4, r3
+; CHECK-P9-NEXT: addi r8, r5, -8
+; CHECK-P9-NEXT: addi r5, r3, 1
+; CHECK-P9-NEXT: sub r3, r10, r3
+; CHECK-P9-NEXT: rldicl r3, r3, 60, 4
+; CHECK-P9-NEXT: lxvdsx vs0, 0, r8
+; CHECK-P9-NEXT: sub r4, r5, r4
+; CHECK-P9-NEXT: sldi r5, r5, 3
+; CHECK-P9-NEXT: addi r3, r3, 1
; CHECK-P9-NEXT: sldi r4, r4, 3
-; CHECK-P9-NEXT: sldi r3, r3, 3
-; CHECK-P9-NEXT: add r4, r9, r4
-; CHECK-P9-NEXT: add r3, r6, r3
-; CHECK-P9-NEXT: sub r6, r10, r8
-; CHECK-P9-NEXT: rldicl r6, r6, 60, 4
-; CHECK-P9-NEXT: addi r6, r6, 1
-; CHECK-P9-NEXT: mtctr r6
+; CHECK-P9-NEXT: add r5, r9, r5
+; CHECK-P9-NEXT: mtctr r3
+; CHECK-P9-NEXT: add r4, r6, r4
; CHECK-P9-NEXT: .p2align 4
; CHECK-P9-NEXT: .LBB0_2: # %_loop_2_do_
; CHECK-P9-NEXT: #
-; CHECK-P9-NEXT: lxv vs1, -16(r4)
-; CHECK-P9-NEXT: lxv vs2, 0(r4)
-; CHECK-P9-NEXT: lxv vs3, -16(r3)
-; CHECK-P9-NEXT: lxv vs4, 0(r3)
-; CHECK-P9-NEXT: addi r3, r3, 128
+; CHECK-P9-NEXT: lxv vs1, -16(r5)
+; CHECK-P9-NEXT: lxv vs2, 0(r5)
+; CHECK-P9-NEXT: lxv vs3, -16(r4)
+; CHECK-P9-NEXT: lxv vs4, 0(r4)
+; CHECK-P9-NEXT: addi r4, r4, 128
; CHECK-P9-NEXT: xvmaddadp vs1, vs3, vs1
-; CHECK-P9-NEXT: stxv vs1, -16(r4)
+; CHECK-P9-NEXT: stxv vs1, -16(r5)
; CHECK-P9-NEXT: xvmaddadp vs2, vs4, vs0
-; CHECK-P9-NEXT: stxv vs2, 0(r4)
-; CHECK-P9-NEXT: addi r4, r4, 128
+; CHECK-P9-NEXT: stxv vs2, 0(r5)
+; CHECK-P9-NEXT: addi r5, r5, 128
; CHECK-P9-NEXT: bdnz .LBB0_2
; CHECK-P9-NEXT: # %bb.3: # %_return_bb
; CHECK-P9-NEXT: blr
; CHECK-P10-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
; CHECK-P10-NEXT: extswsli r5, r5, 3
; CHECK-P10-NEXT: extsw r10, r4
+; CHECK-P10-NEXT: lwa r4, 0(r7)
; CHECK-P10-NEXT: add r5, r8, r5
-; CHECK-P10-NEXT: clrldi r8, r3, 32
-; CHECK-P10-NEXT: lwa r3, 0(r7)
-; CHECK-P10-NEXT: addi r4, r8, 1
-; CHECK-P10-NEXT: addi r5, r5, -8
-; CHECK-P10-NEXT: lxvdsx vs0, 0, r5
-; CHECK-P10-NEXT: sub r3, r4, r3
+; CHECK-P10-NEXT: addi r8, r5, -8
+; CHECK-P10-NEXT: addi r5, r3, 1
+; CHECK-P10-NEXT: sub r3, r10, r3
+; CHECK-P10-NEXT: sub r4, r5, r4
+; CHECK-P10-NEXT: rldicl r3, r3, 60, 4
+; CHECK-P10-NEXT: sldi r5, r5, 3
+; CHECK-P10-NEXT: add r5, r9, r5
+; CHECK-P10-NEXT: lxvdsx vs0, 0, r8
+; CHECK-P10-NEXT: addi r3, r3, 1
; CHECK-P10-NEXT: sldi r4, r4, 3
-; CHECK-P10-NEXT: add r4, r9, r4
-; CHECK-P10-NEXT: sldi r3, r3, 3
-; CHECK-P10-NEXT: add r3, r6, r3
-; CHECK-P10-NEXT: sub r6, r10, r8
-; CHECK-P10-NEXT: rldicl r6, r6, 60, 4
-; CHECK-P10-NEXT: addi r6, r6, 1
-; CHECK-P10-NEXT: mtctr r6
+; CHECK-P10-NEXT: add r4, r6, r4
+; CHECK-P10-NEXT: mtctr r3
; CHECK-P10-NEXT: .p2align 4
; CHECK-P10-NEXT: .LBB0_2: # %_loop_2_do_
; CHECK-P10-NEXT: #
-; CHECK-P10-NEXT: lxv vs1, -16(r4)
-; CHECK-P10-NEXT: lxv vs2, 0(r4)
-; CHECK-P10-NEXT: lxv vs3, -16(r3)
+; CHECK-P10-NEXT: lxv vs1, -16(r5)
+; CHECK-P10-NEXT: lxv vs2, 0(r5)
+; CHECK-P10-NEXT: lxv vs3, -16(r4)
; CHECK-P10-NEXT: xvmaddadp vs1, vs3, vs1
-; CHECK-P10-NEXT: lxv vs4, 0(r3)
+; CHECK-P10-NEXT: lxv vs4, 0(r4)
; CHECK-P10-NEXT: xvmaddadp vs2, vs4, vs0
-; CHECK-P10-NEXT: addi r3, r3, 128
-; CHECK-P10-NEXT: stxv vs1, -16(r4)
-; CHECK-P10-NEXT: stxv vs2, 0(r4)
; CHECK-P10-NEXT: addi r4, r4, 128
+; CHECK-P10-NEXT: stxv vs1, -16(r5)
+; CHECK-P10-NEXT: stxv vs2, 0(r5)
+; CHECK-P10-NEXT: addi r5, r5, 128
; CHECK-P10-NEXT: bdnz .LBB0_2
; CHECK-P10-NEXT: # %bb.3: # %_return_bb
; CHECK-P10-NEXT: blr
; CHECK-NEXT: lfs f0, 8(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-P10-NEXT: plfs f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint16_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint16_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P10-NEXT: plfs f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_float:
; CHECK-P9-NEXT: lfsx f0, r3, r4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_float:
; CHECK-P8-NEXT: lfsx f0, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_float:
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-NEXT: lfs f0, 4080(0)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16
; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_float:
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to double*
; CHECK-NEXT: lfd f0, 8(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-P10-NEXT: plfd f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint16_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint16_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-NEXT: lfdx f0, r3, r4
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P10-NEXT: plfd f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_double:
; CHECK-P9-NEXT: lfdx f0, r3, r4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_double:
; CHECK-P8-NEXT: lfdx f0, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_double:
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-NEXT: lfd f0, 4080(0)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16
; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_double:
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to float*
; CHECK-NEXT: lfs f0, 8(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-P10-NEXT: plfs f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint32_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P10-NEXT: plfs f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_float:
; CHECK-P9-NEXT: lfsx f0, r3, r4
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_float:
; CHECK-P8-NEXT: lfsx f0, r3, r4
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_float:
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-NEXT: lfs f0, 4080(0)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16
; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_float:
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to double*
; CHECK-NEXT: lfd f0, 8(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-P10-NEXT: plfd f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint32_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint32_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-NEXT: lfdx f0, r3, r4
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P10-NEXT: plfd f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_double:
; CHECK-P9-NEXT: lfdx f0, r3, r4
; CHECK-P9-NEXT: xscvdpuxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_double:
; CHECK-P8-NEXT: lfdx f0, r3, r4
; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_double:
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-NEXT: lfd f0, 4080(0)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16
; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-NEXT: xscvdpuxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpuxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_double:
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpuxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to float*
; CHECK-NEXT: lfs f0, 8(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-P10-NEXT: plfs f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint8_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: lfsx f0, r3, r5
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_unalign64_uint8_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000001
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint8_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-NEXT: lfs f0, 24(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: lfs f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P10-NEXT: plfs f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_float:
; CHECK-P9-NEXT: lfsx f0, r3, r4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_float:
; CHECK-P8-NEXT: lfsx f0, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_float:
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: lfsx f0, r3, r5
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_unalign64_uint8_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-P10-NEXT: lfsx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_float:
; CHECK-PREP10-NEXT: lfsx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-NEXT: lfs f0, 4080(0)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 4080 to float*), align 16
; CHECK-NEXT: lfs f0, -27108(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 9999900 to float*), align 4
; CHECK-P10-NEXT: lfs f0, 0(r4)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_float:
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 1000000000001 to float*), align 4
; CHECK-P10-NEXT: lfs f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_float:
; CHECK-PREP10-NEXT: lfs f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = inttoptr i64 %ptr to double*
; CHECK-NEXT: lfd f0, 8(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
; CHECK-P10-NEXT: plfd f0, 99999000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align32_uint8_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
; CHECK-P10-NEXT: lfdx f0, r3, r5
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_unalign64_uint8_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000001
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_align64_uint8_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
; CHECK-NEXT: lfdx f0, r3, r4
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%conv = zext i8 %off to i64
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 6
; CHECK-NEXT: lfd f0, 24(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%and = and i64 %ptr, -4096
; CHECK-NEXT: lfd f0, 0(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%or = or i64 %ptr, 99999
; CHECK-P10-NEXT: plfd f0, 999990000(r3), 0
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_double:
; CHECK-P9-NEXT: lfdx f0, r3, r4
; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: clrldi r3, r3, 32
; CHECK-P9-NEXT: blr
;
; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_double:
; CHECK-P8-NEXT: lfdx f0, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mffprwz r3, f0
-; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: blr
entry:
%and = and i64 %ptr, -1000341504
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_double:
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%or = or i64 %ptr, 1000000000001
; CHECK-P10-NEXT: lfdx f0, r3, r5
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_unalign64_uint8_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-P10-NEXT: lfdx f0, r3, r4
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_double:
; CHECK-PREP10-NEXT: lfdx f0, r3, r4
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%and = and i64 %ptr, -1099511627776
; CHECK-NEXT: lfd f0, 4080(0)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 4080 to double*), align 16
; CHECK-NEXT: lfd f0, -27108(r3)
; CHECK-NEXT: xscvdpsxws f0, f0
; CHECK-NEXT: mffprwz r3, f0
-; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 9999900 to double*), align 8
; CHECK-P10-NEXT: lfd f0, 0(r4)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_double:
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 1000000000001 to double*), align 8
; CHECK-P10-NEXT: lfd f0, 0(r3)
; CHECK-P10-NEXT: xscvdpsxws f0, f0
; CHECK-P10-NEXT: mffprwz r3, f0
-; CHECK-P10-NEXT: clrldi r3, r3, 32
; CHECK-P10-NEXT: blr
;
; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_double:
; CHECK-PREP10-NEXT: lfd f0, 0(r3)
; CHECK-PREP10-NEXT: xscvdpsxws f0, f0
; CHECK-PREP10-NEXT: mffprwz r3, f0
-; CHECK-PREP10-NEXT: clrldi r3, r3, 32
; CHECK-PREP10-NEXT: blr
entry:
%0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
; CHECK-LABEL: selecti32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: srawi 3, 3, 31
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: xori 3, 3, 65535
; CHECK-NEXT: xoris 3, 3, 32767
; CHECK-NEXT: blr
; CHECK-LABEL: selecti32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: srawi 3, 3, 31
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i32 %a, -1
; CHECK-LABEL: selecti32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: srawi 3, 3, 31
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i32 %a, -1
; CHECK: # %bb.0:
; CHECK-NEXT: extsb 3, 3
; CHECK-NEXT: srawi 3, 3, 7
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: xori 3, 3, 84
; CHECK-NEXT: blr
%c = icmp sgt i8 %a, -1
--- /dev/null
+# RUN: llc -run-pass ppc-mi-peepholes -ppc-eliminate-signext -ppc-eliminate-zeroext -verify-machineinstrs -o - %s | FileCheck %s
+
+--- |
+ target datalayout = "E-m:e-i64:64-n32:64"
+ target triple = "powerpc64le-unknown-linux-gnu"
+ define i8* @func(i8* %a) {
+ entry:
+ ret i8* %a
+ }
+
+...
+---
+name: func
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x3', virtual-reg: '%0' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ maxCallFrameSize: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+body: |
+ bb.0.entry:
+ liveins: $x3
+
+ ; CHECK-LABEL: bb.0.entry:
+ ; CHECK: %4:g8rc = EXTSW_32_64 %3
+ ; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
+ ; CHECK: %7:g8rc = EXTSW_32_64 %6
+ ; CHECK: %9:g8rc = INSERT_SUBREG %16, %8, %subreg.sub_32
+ ; CHECK: %11:g8rc = INSERT_SUBREG %17, %10, %subreg.sub_32
+ ; CHECK: %14:g8rc = COPY %1
+
+ %0:g8rc_nox0 = COPY $x3
+ %1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
+ %3:gprc = COPY %2:g8rc_nox0
+ %4:g8rc = EXTSW_32_64 %3:gprc ; should not be eliminated
+ %5:g8rc = EXTSW_32_64 %1:gprc
+
+ %6:gprc = ORIS %1:gprc, 32768 ; should not be eliminated
+ %7:g8rc = EXTSW_32_64 %6:gprc
+
+ %8:gprc = ORIS %1:gprc, 32767
+ %9:g8rc = EXTSW_32_64 %8:gprc
+
+ %10:gprc = ORI %1:gprc, 32768
+ %11:g8rc = EXTSW_32_64 %10:gprc
+
+ %12:g8rc = IMPLICIT_DEF
+ %13:g8rc = INSERT_SUBREG %12:g8rc, %1:gprc, %subreg.sub_32
+ %14:g8rc = RLDICL %13:g8rc, 0, 32
+
+...
define i16 @noSEXTLoad(i16 *%p) #0 {
; CHECK-LABEL: noSEXTLoad:
; CHECK: # %bb.0: # %top
-; CHECK-NEXT: lhz 5, 0(3)
+; CHECK-NEXT: lha 3, 0(3)
; CHECK-NEXT: li 4, 0
-; CHECK-NEXT: addi 3, 1, -4
; CHECK-NEXT: sth 4, -4(1)
-; CHECK-NEXT: extsh 4, 5
+; CHECK-NEXT: addi 4, 1, -4
; CHECK-NEXT: lwsync
; CHECK-NEXT: .LBB2_1: # %top
; CHECK-NEXT: #
-; CHECK-NEXT: lharx 5, 0, 3
+; CHECK-NEXT: lharx 5, 0, 4
; CHECK-NEXT: extsh 5, 5
-; CHECK-NEXT: cmpw 4, 5
+; CHECK-NEXT: cmpw 3, 5
; CHECK-NEXT: bge 0, .LBB2_3
; CHECK-NEXT: # %bb.2: # %top
; CHECK-NEXT: #
-; CHECK-NEXT: sthcx. 4, 0, 3
+; CHECK-NEXT: sthcx. 3, 0, 4
; CHECK-NEXT: bne 0, .LBB2_1
; CHECK-NEXT: .LBB2_3: # %top
; CHECK-NEXT: lwsync
; CHECK-NEXT: nop
; CHECK-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-NEXT: .LBB0_3: # %return
-; CHECK-NEXT: extsw 3, 3
+; CHECK-NEXT: # kill: def $r3 killed $r3 def $x3
; CHECK-NEXT: addi 1, 31, 784
; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: lwz 12, 8(1)
; BE-NEXT: nop
; BE-NEXT: # kill: def $r3 killed $r3 killed $x3
; BE-NEXT: .LBB0_3: # %return
-; BE-NEXT: extsw 3, 3
+; BE-NEXT: # kill: def $r3 killed $r3 def $x3
; BE-NEXT: addi 1, 31, 800
; BE-NEXT: ld 0, 16(1)
; BE-NEXT: lwz 12, 8(1)
; CHECK-NEXT: std 3, 48(1)
; CHECK-NEXT: lwz 3, 48(1)
; CHECK-NEXT: srawi 3, 3, 8
-; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: blr
entry:
%a = getelementptr inbounds %struct.ST, %struct.ST* %s, i32 0, i32 0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: mr r29, r5
-; CHECK-NEXT: mr r30, r3
-; CHECK-NEXT: extsw r28, r4
+; CHECK-NEXT: mr r30, r4
+; CHECK-NEXT: mr r28, r3
; CHECK-NEXT: std r2, 24(r1)
; CHECK-NEXT: cmpwi r29, 1
; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: cmpwi r4, 11
+; CHECK-NEXT: cmpwi r30, 11
; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # %for.body.us
; CHECK-NEXT: #
-; CHECK-NEXT: mtctr r30
-; CHECK-NEXT: mr r3, r28
-; CHECK-NEXT: mr r12, r30
+; CHECK-NEXT: mtctr r28
+; CHECK-NEXT: mr r3, r30
+; CHECK-NEXT: mr r12, r28
; CHECK-NEXT: bctrl
; CHECK-NEXT: ld 2, 24(r1)
; CHECK-NEXT: addi r29, r29, -1
; CHECK-NEXT: cmplwi r29, 0
; CHECK-NEXT: bne cr0, .LBB0_2
; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
-; CHECK-NEXT: mtctr r30
-; CHECK-NEXT: mr r3, r28
-; CHECK-NEXT: mr r12, r30
+; CHECK-NEXT: mtctr r28
+; CHECK-NEXT: mr r3, r30
+; CHECK-NEXT: mr r12, r28
; CHECK-NEXT: bctrl
; CHECK-NEXT: ld 2, 24(r1)
; CHECK-NEXT: addi r1, r1, 64