cpu_register_physical_memory(SVGA_MEM_BASE, vga_ram_size,
iomemtype);
- register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_INDEX_PORT,
- 1, 4, vmsvga_index_read, s);
- register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_INDEX_PORT,
- 1, 4, vmsvga_index_write, s);
- register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_VALUE_PORT,
- 1, 4, vmsvga_value_read, s);
- register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_VALUE_PORT,
- 1, 4, vmsvga_value_write, s);
- register_ioport_read(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_BIOS_PORT,
- 1, 4, vmsvga_bios_read, s);
- register_ioport_write(SVGA_IO_BASE + SVGA_IO_MUL * SVGA_BIOS_PORT,
- 1, 4, vmsvga_bios_write, s);
-
graphic_console_init(ds, vmsvga_update_display,
vmsvga_invalidate_display, vmsvga_screen_dump, s);
return 0;
}
+static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
+ uint32_t addr, uint32_t size, int type)
+{
+ struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
+ struct vmsvga_state_s *s = &d->chip;
+
+ register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
+ 1, 4, vmsvga_index_read, s);
+ register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
+ 1, 4, vmsvga_index_write, s);
+ register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
+ 1, 4, vmsvga_value_read, s);
+ register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
+ 1, 4, vmsvga_value_write, s);
+ register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
+ 1, 4, vmsvga_bios_read, s);
+ register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
+ 1, 4, vmsvga_bios_write, s);
+}
+
#define PCI_VENDOR_ID_VMWARE 0x15ad
#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
s->card.config[0x3c] = 0xff; /* End */
+ pci_register_io_region(&s->card, 0, 0x10,
+ PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
+
vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);