phy: cadence: salvo: decrease delay value to zero for txvalid

For USB2 L1 use cases, some hosts may start transferring less than 20us
after End of Resume, it causes the host seeing corrupt packet from the
device side. The reason is the delay time between PHY powers up and
txvalid is 20us. To fix it, we change the delay value as 0us.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-3-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
index 06c5dbd..2e3d4d8 100644 (file)
--- a/drivers/phy/cadence/phy-cadence-salvo.c
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -89,8 +89,20 @@
 #define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR  0x40f2
 #define TB_ADDR_TX_RCVDETSC_CTRL               0x4124
 
+/* USB2 PHY register definition */
+#define UTMI_REG15                             0xaf
+
 /* TB_ADDR_TX_RCVDETSC_CTRL */
 #define RXDET_IN_P3_32KHZ                      BIT(0)
+/*
+ * UTMI_REG15
+ *
+ * Gate how many us for the txvalid signal until analog
+ * HS/FS transmitters have powered up
+ */
+#define TXVALID_GATE_THRESHOLD_HS_MASK         (BIT(4) | BIT(5))
+/* 0us, txvalid is ready just after HS/FS transmitters have powered up */
+#define TXVALID_GATE_THRESHOLD_HS_0US          (BIT(4) | BIT(5))
 
 struct cdns_reg_pairs {
        u16 val;
@@ -230,6 +242,11 @@ static int cdns_salvo_phy_init(struct phy *phy)
        cdns_salvo_write(salvo_phy, USB3_PHY_OFFSET, TB_ADDR_TX_RCVDETSC_CTRL,
                         RXDET_IN_P3_32KHZ);
 
+       value = cdns_salvo_read(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15);
+       value &= ~TXVALID_GATE_THRESHOLD_HS_MASK;
+       cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15,
+                        value | TXVALID_GATE_THRESHOLD_HS_0US);
+
        udelay(10);
 
        clk_disable_unprepare(salvo_phy->clk);