if (!desc->buffer)
return false;
+ desc->list = ptr;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
desc->buffer, RADEON_USAGE_READ,
RADEON_PRIO_DESCRIPTORS);
si_init_descriptors(sctx, &sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
4, SI_NUM_VERTEX_BUFFERS, 0, 0, NULL);
+ FREE(sctx->vertex_buffers.list); /* not used */
+ sctx->vertex_buffers.list = NULL;
sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
sctx->total_ce_ram_allocated = ce_offset;
for (i = 0; i < SI_NUM_DESCS; ++i)
si_release_descriptors(&sctx->descriptors[i]);
+
+ sctx->vertex_buffers.list = NULL; /* points into a mapped buffer */
si_release_descriptors(&sctx->vertex_buffers);
}