re PR target/45800 ([M32C] compile error on increment volatile long var)

PR target/45800
* config/m32c/m32c.c (m32c_subreg): Force adjustment of subregs of
volatile MEMs.

From-SVN: r164705

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2aded97..0fe8fbb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2010-09-28  DJ Delorie  <dj@redhat.com>
+
+       PR target/45800
+       * config/m32c/m32c.c (m32c_subreg): Force adjustment of subregs of
+       volatile MEMs.
+
 2010-09-28  Iain Sandoe  <iains@gcc.gnu.org>
 
        * c-parser.c (c_parser_declaration_or_fndef): Diagnose incorrect prefix

diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 066d1a8..d62b4f2 100644 (file)
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -3317,7 +3317,19 @@ m32c_subreg (enum machine_mode outer,
     return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
 
   if (GET_CODE (x) != REG)
-    return simplify_gen_subreg (outer, x, inner, byte);
+    {
+      rtx r = simplify_gen_subreg (outer, x, inner, byte);
+      if (GET_CODE (r) == SUBREG
+         && GET_CODE (x) == MEM
+         && MEM_VOLATILE_P (x))
+       {
+         /* Volatile MEMs don't get simplified, but we need them to
+            be.  We are little endian, so the subreg byte is the
+            offset.  */
+         r = adjust_address (x, outer, byte);
+       }
+      return r;
+    }
 
   r = REGNO (x);
   if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)