eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
data = 0;
- for(i = 0; i < 16; i++) {
+ for (i = 0; i < 16; i++) {
data = data << 1;
ixgb_raise_clock(hw, &eecd_reg);
* signal that the command has been completed by raising the DO signal.
* If DO does not go high in 10 milliseconds, then error out.
*/
- for(i = 0; i < 200; i++) {
+ for (i = 0; i < 200; i++) {
eecd_reg = IXGB_READ_REG(hw, EECD);
if (eecd_reg & IXGB_EECD_DO)
u16 checksum = 0;
u16 i;
- for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
+ for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
checksum += ixgb_read_eeprom(hw, i);
if (checksum == (u16) EEPROM_SUM)
u16 checksum = 0;
u16 i;
- for(i = 0; i < EEPROM_CHECKSUM_REG; i++)
+ for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
checksum += ixgb_read_eeprom(hw, i);
checksum = (u16) EEPROM_SUM - checksum;
ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
DEBUGOUT("ixgb_ee: Reading eeprom data\n");
- for(i = 0; i < IXGB_EEPROM_SIZE ; i++) {
+ for (i = 0; i < IXGB_EEPROM_SIZE ; i++) {
u16 ee_data;
ee_data = ixgb_read_eeprom(hw, i);
checksum += ee_data;
*reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */
/* there are 16 RAR entries in hardware, we only use 3 */
- for(i = 0; i < IXGB_ALL_RAR_ENTRIES; i++) {
+ for (i = 0; i < IXGB_ALL_RAR_ENTRIES; i++) {
*reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */
*reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */
}
return -ENOMEM;
/* note the eeprom was good because the driver loaded */
- for(i = 0; i <= (last_word - first_word); i++) {
+ for (i = 0; i <= (last_word - first_word); i++)
eeprom_buff[i] = ixgb_get_eeprom_word(hw, (first_word + i));
- }
- memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
- eeprom->len);
+ memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
kfree(eeprom_buff);
geeprom_error:
}
memcpy(ptr, bytes, eeprom->len);
- for(i = 0; i <= (last_word - first_word); i++)
+ for (i = 0; i <= (last_word - first_word); i++)
ixgb_write_eeprom(hw, first_word + i, eeprom_buff[i]);
/* Update the checksum over the first part of the EEPROM if needed */
int i;
ixgb_update_stats(adapter);
- for(i = 0; i < IXGB_STATS_LEN; i++) {
+ for (i = 0; i < IXGB_STATS_LEN; i++) {
char *p = (char *)adapter+ixgb_gstrings_stats[i].stat_offset;
data[i] = (ixgb_gstrings_stats[i].sizeof_stat ==
sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
switch(stringset) {
case ETH_SS_STATS:
- for(i=0; i < IXGB_STATS_LEN; i++) {
+ for (i = 0; i < IXGB_STATS_LEN; i++) {
memcpy(data + i * ETH_GSTRING_LEN,
ixgb_gstrings_stats[i].stat_string,
ETH_GSTRING_LEN);
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
- for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
+ for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
/* Zero out the VLAN Filter Table Array */
/* Zero out the other 15 receive addresses. */
DEBUGOUT("Clearing RAR[1-15]\n");
- for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
+ for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
/* Write high reg first to disable the AV bit first */
IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
/* Clear RAR[1-15] */
DEBUGOUT(" Clearing RAR[1-15]\n");
- for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
+ for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
}
/* Clear the MTA */
DEBUGOUT(" Clearing MTA\n");
- for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
+ for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
- }
/* Add the new addresses */
- for(i = 0; i < mc_addr_count; i++) {
+ for (i = 0; i < mc_addr_count; i++) {
DEBUGOUT(" Adding the multicast addresses:\n");
DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
{
u32 offset;
- for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
+ for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
return;
}
** from the CPU Write to the Ready bit assertion.
**************************************************************/
- for(i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
{
udelay(10);
** from the CPU Write to the Ready bit assertion.
**************************************************************/
- for(i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
{
udelay(10);
** from the CPU Write to the Ready bit assertion.
**************************************************************/
- for(i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
{
udelay(10);
** from the CPU Write to the Ready bit assertion.
**************************************************************/
- for(i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
{
udelay(10);
goto err_ioremap;
}
- for(i = BAR_1; i <= BAR_5; i++) {
+ for (i = BAR_1; i <= BAR_5; i++) {
if (pci_resource_len(pdev, i) == 0)
continue;
if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
/* Free all the Tx ring sk_buffs */
- for(i = 0; i < tx_ring->count; i++) {
+ for (i = 0; i < tx_ring->count; i++) {
buffer_info = &tx_ring->buffer_info[i];
ixgb_unmap_and_free_tx_resource(adapter, buffer_info);
}
/* Free all the Rx ring sk_buffs */
- for(i = 0; i < rx_ring->count; i++) {
+ for (i = 0; i < rx_ring->count; i++) {
buffer_info = &rx_ring->buffer_info[i];
if (buffer_info->skb) {
if (++i == tx_ring->count) i = 0;
}
- for(f = 0; f < nr_frags; f++) {
+ for (f = 0; f < nr_frags; f++) {
struct skb_frag_struct *frag;
frag = &skb_shinfo(skb)->frags[f];
* every pass through this for loop checks both receive and
* transmit queues for completed descriptors, intended to
* avoid starvation issues and assist tx/rx fairness. */
- for(i = 0; i < IXGB_MAX_INTR; i++)
+ for (i = 0; i < IXGB_MAX_INTR; i++)
if (!ixgb_clean_rx_irq(adapter) &
!ixgb_clean_tx_irq(adapter))
break;
if (adapter->vlgrp) {
u16 vid;
- for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
+ for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
if (!vlan_group_get_device(adapter->vlgrp, vid))
continue;
ixgb_vlan_rx_add_vid(adapter->netdev, vid);
int i;
struct ixgb_opt_list *ent;
- for(i = 0; i < opt->arg.l.nr; i++) {
+ for (i = 0; i < opt->arg.l.nr; i++) {
ent = &opt->arg.l.p[i];
if (*value == ent->i) {
if (ent->str[0] != '\0')