(struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
&tx_ring->tx_desc_ring_pa);
if (!adapter->tx_ring.tx_desc_ring) {
- dev_err(&adapter->pdev->dev, "Cannot alloc memory for Tx Ring\n");
+ dev_err(&adapter->pdev->dev,
+ "Cannot alloc memory for Tx Ring\n");
return -ENOMEM;
}
if (adapter->tx_ring.tx_desc_ring) {
/* Free memory relating to Tx rings here */
desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
- + 4096 - 1;
+ + 4096 - 1;
pci_free_consistent(adapter->pdev,
desc_size,
adapter->tx_ring.tx_desc_ring,
/**
* ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
* @etdev: pointer to our private adapter structure
+ *
+ * Configure the transmit engine with the ring buffers we have created
+ * and prepare it for use.
*/
void ConfigTxDmaRegs(struct et131x_adapter *etdev)
{
/* Go through and set up each TCB */
for (ct = 0; ct++ < NUM_TCB; tcb++)
/* Set the link pointer in HW TCB to the next TCB in the
- * chain. If this is the last TCB in the chain, also set the
- * tail pointer.
+ * chain
*/
tcb->next = tcb + 1;
+ /* Set the tail pointer */
tcb--;
tx_ring->tcb_qtail = tcb;
tcb->next = NULL;
tcb->skb = skb;
- if ((skb->data != NULL) && ((skb->len - skb->data_len) >= 6)) {
+ if (skb->data != NULL && skb->len - skb->data_len >= 6) {
shbufva = (u16 *) skb->data;
if ((shbufva[0] == 0xffff) &&
if (status != 0) {
spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
- if (etdev->tx_ring.tcb_qtail) {
+ if (etdev->tx_ring.tcb_qtail)
etdev->tx_ring.tcb_qtail->next = tcb;
- } else {
+ else
/* Apparently ready Q is empty. */
etdev->tx_ring.tcb_qhead = tcb;
- }
etdev->tx_ring.tcb_qtail = tcb;
spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
return -EIO;
if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
- if (++etdev->tx_ring.since_irq ==
- PARM_TX_NUM_BUFS_DEF) {
- /* Last element & Interrupt flag */
+ if (++etdev->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
+ /* Last element & Interrupt flag */
desc[frag - 1].flags = 0x5;
etdev->tx_ring.since_irq = 0;
} else { /* Last element */
add_10bit(&etdev->tx_ring.send_idx, thiscopy);
- if (INDEX10(etdev->tx_ring.send_idx)== 0 ||
- INDEX10(etdev->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
- etdev->tx_ring.send_idx &= ~ET_DMA10_MASK;
- etdev->tx_ring.send_idx ^= ET_DMA10_WRAP;
+ if (INDEX10(etdev->tx_ring.send_idx) == 0 ||
+ INDEX10(etdev->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
+ etdev->tx_ring.send_idx &= ~ET_DMA10_MASK;
+ etdev->tx_ring.send_idx ^= ET_DMA10_WRAP;
}
if (remainder) {
if (etdev->tx_ring.send_idx)
tcb->index = NUM_DESC_PER_RING_TX - 1;
else
- tcb->index= ET_DMA10_WRAP | (NUM_DESC_PER_RING_TX - 1);
+ tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
} else
tcb->index = etdev->tx_ring.send_idx - 1;
* they point to
*/
do {
- desc =(struct tx_desc *) (etdev->tx_ring.tx_desc_ring +
- INDEX10(tcb->index_start));
+ desc = (struct tx_desc *)(etdev->tx_ring.tx_desc_ring +
+ INDEX10(tcb->index_start));
pci_unmap_single(etdev->pdev,
desc->addr_lo,
add_10bit(&tcb->index_start, 1);
if (INDEX10(tcb->index_start) >=
- NUM_DESC_PER_RING_TX) {
- tcb->index_start &= ~ET_DMA10_MASK;
- tcb->index_start ^= ET_DMA10_WRAP;
+ NUM_DESC_PER_RING_TX) {
+ tcb->index_start &= ~ET_DMA10_MASK;
+ tcb->index_start ^= ET_DMA10_WRAP;
}
} while (desc != (etdev->tx_ring.tx_desc_ring +
INDEX10(tcb->index)));
tcb = etdev->tx_ring.send_head;
- while ((tcb != NULL) && (freed < NUM_TCB)) {
+ while (tcb != NULL && freed < NUM_TCB) {
struct tcb *next = tcb->next;
etdev->tx_ring.send_head = next;
{
unsigned long flags;
u32 serviced;
- struct tcb * tcb;
+ struct tcb *tcb;
u32 index;
serviced = readl(&etdev->regs->txdma.NewServiceComplete);
}
/* Wake up the queue when we hit a low-water mark */
- if (etdev->tx_ring.used <= (NUM_TCB / 3))
+ if (etdev->tx_ring.used <= NUM_TCB / 3)
netif_wake_queue(etdev->netdev);
spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);