drm/amdgpu: add internal reg offset translation for VCN inst 1

Add range for vcn instance 1 for translation for internal register offset, which
is needed for VCN3.0

V2: update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 7a2d5f8..25a0770 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -53,7 +53,9 @@
 #define VCN_ENC_CMD_REG_WAIT           0x0000000c
 
 #define VCN_VID_SOC_ADDRESS_2_0        0x1fa00
+#define VCN1_VID_SOC_ADDRESS_3_0       0x48200
 #define VCN_AON_SOC_ADDRESS_2_0        0x1f800
+#define VCN1_AON_SOC_ADDRESS_3_0       0x48000
 #define VCN_VID_IP_ADDRESS_2_0         0x0
 #define VCN_AON_IP_ADDRESS_2_0         0x30000
 
@@ -89,20 +91,30 @@
 #define SOC15_DPG_MODE_OFFSET_2_0(ip, inst_idx, reg)                                           \
        ({                                                                                      \
                uint32_t internal_reg_offset, addr;                                             \
-               bool video_range, aon_range;                                                    \
+               bool video_range, video1_range, aon_range, aon1_range;                          \
                                                                                                \
                addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);           \
                addr <<= 2;                                                                     \
                video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) &&              \
                                ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600)))));    \
+               video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) &&            \
+                               ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600)))));   \
                aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) &&              \
                                ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600)))));     \
+               aon1_range   = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) &&            \
+                               ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600)))));    \
                if (video_range)                                                                \
                        internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) +   \
                                (VCN_VID_IP_ADDRESS_2_0));                                      \
                else if (aon_range)                                                             \
                        internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) +   \
                                (VCN_AON_IP_ADDRESS_2_0));                                      \
+               else if (video1_range)                                                          \
+                       internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) +  \
+                               (VCN_VID_IP_ADDRESS_2_0));                                      \
+               else if (aon1_range)                                                            \
+                       internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) +  \
+                               (VCN_AON_IP_ADDRESS_2_0));                                      \
                else                                                                            \
                        internal_reg_offset = (0xFFFFF & addr);                                 \
                                                                                                \