--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+
+define i64 @addimm_mulimm_accept_00(i64 %a) {
+; CHECK-LABEL: addimm_mulimm_accept_00:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: mul x8, x0, x8
+; CHECK-NEXT: add x0, x8, #1147
+; CHECK-NEXT: ret
+ %tmp0 = add i64 %a, 31
+ %tmp1 = mul i64 %tmp0, 37
+ ret i64 %tmp1
+}
+
+define i64 @addimm_mulimm_accept_01(i64 %a) {
+; CHECK-LABEL: addimm_mulimm_accept_01:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: mul x8, x0, x8
+; CHECK-NEXT: sub x0, x8, #1147
+; CHECK-NEXT: ret
+ %tmp0 = add i64 %a, -31
+ %tmp1 = mul i64 %tmp0, 37
+ ret i64 %tmp1
+}
+
+define signext i32 @addimm_mulimm_accept_02(i32 signext %a) {
+; CHECK-LABEL: addimm_mulimm_accept_02:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: mul w8, w0, w8
+; CHECK-NEXT: add w0, w8, #1147
+; CHECK-NEXT: ret
+ %tmp0 = add i32 %a, 31
+ %tmp1 = mul i32 %tmp0, 37
+ ret i32 %tmp1
+}
+
+define signext i32 @addimm_mulimm_accept_03(i32 signext %a) {
+; CHECK-LABEL: addimm_mulimm_accept_03:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: mul w8, w0, w8
+; CHECK-NEXT: sub w0, w8, #1147
+; CHECK-NEXT: ret
+ %tmp0 = add i32 %a, -31
+ %tmp1 = mul i32 %tmp0, 37
+ ret i32 %tmp1
+}
+
+define i64 @addimm_mulimm_accept_10(i64 %a) {
+; CHECK-LABEL: addimm_mulimm_accept_10:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w9, #32888
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: movk w9, #17, lsl #16
+; CHECK-NEXT: madd x0, x0, x8, x9
+; CHECK-NEXT: ret
+ %tmp0 = add i64 %a, 31000
+ %tmp1 = mul i64 %tmp0, 37
+ ret i64 %tmp1
+}
+
+define i64 @addimm_mulimm_accept_11(i64 %a) {
+; CHECK-LABEL: addimm_mulimm_accept_11:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x9, #-32888
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: movk x9, #65518, lsl #16
+; CHECK-NEXT: madd x0, x0, x8, x9
+; CHECK-NEXT: ret
+ %tmp0 = add i64 %a, -31000
+ %tmp1 = mul i64 %tmp0, 37
+ ret i64 %tmp1
+}
+
+define signext i32 @addimm_mulimm_accept_12(i32 signext %a) {
+; CHECK-LABEL: addimm_mulimm_accept_12:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w9, #32888
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: movk w9, #17, lsl #16
+; CHECK-NEXT: madd w0, w0, w8, w9
+; CHECK-NEXT: ret
+ %tmp0 = add i32 %a, 31000
+ %tmp1 = mul i32 %tmp0, 37
+ ret i32 %tmp1
+}
+
+define signext i32 @addimm_mulimm_accept_13(i32 signext %a) {
+; CHECK-LABEL: addimm_mulimm_accept_13:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w9, #32648
+; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: movk w9, #65518, lsl #16
+; CHECK-NEXT: madd w0, w0, w8, w9
+; CHECK-NEXT: ret
+ %tmp0 = add i32 %a, -31000
+ %tmp1 = mul i32 %tmp0, 37
+ ret i32 %tmp1
+}
+
+define i64 @addimm_mulimm_reject_00(i64 %a) {
+; CHECK-LABEL: addimm_mulimm_reject_00:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w9, #1200
+; CHECK-NEXT: mov w8, #3700
+; CHECK-NEXT: movk w9, #175, lsl #16
+; CHECK-NEXT: madd x0, x0, x8, x9
+; CHECK-NEXT: ret
+ %tmp0 = add i64 %a, 3100
+ %tmp1 = mul i64 %tmp0, 3700
+ ret i64 %tmp1
+}
+
+define i64 @addimm_mulimm_reject_01(i64 %a) {
+; CHECK-LABEL: addimm_mulimm_reject_01:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x9, #-1200
+; CHECK-NEXT: mov w8, #3700
+; CHECK-NEXT: movk x9, #65360, lsl #16
+; CHECK-NEXT: madd x0, x0, x8, x9
+; CHECK-NEXT: ret
+ %tmp0 = add i64 %a, -3100
+ %tmp1 = mul i64 %tmp0, 3700
+ ret i64 %tmp1
+}
+
+define signext i32 @addimm_mulimm_reject_02(i32 signext %a) {
+; CHECK-LABEL: addimm_mulimm_reject_02:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w9, #1200
+; CHECK-NEXT: mov w8, #3700
+; CHECK-NEXT: movk w9, #175, lsl #16
+; CHECK-NEXT: madd w0, w0, w8, w9
+; CHECK-NEXT: ret
+ %tmp0 = add i32 %a, 3100
+ %tmp1 = mul i32 %tmp0, 3700
+ ret i32 %tmp1
+}
+
+define signext i32 @addimm_mulimm_reject_03(i32 signext %a) {
+; CHECK-LABEL: addimm_mulimm_reject_03:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w9, #64336
+; CHECK-NEXT: mov w8, #3700
+; CHECK-NEXT: movk w9, #65360, lsl #16
+; CHECK-NEXT: madd w0, w0, w8, w9
+; CHECK-NEXT: ret
+ %tmp0 = add i32 %a, -3100
+ %tmp1 = mul i32 %tmp0, 3700
+ ret i32 %tmp1
+}