#define CONTROL_RST_RX 0x02
#define CONTROL_IE 0x10
-struct xlx_uartlite
-{
+typedef struct XilinxUARTLite {
SysBusDevice busdev;
MemoryRegion mmio;
CharDriverState *chr;
unsigned int rx_fifo_len;
uint32_t regs[R_MAX];
-};
+} XilinxUARTLite;
-static void uart_update_irq(struct xlx_uartlite *s)
+static void uart_update_irq(XilinxUARTLite *s)
{
unsigned int irq;
qemu_set_irq(s->irq, irq);
}
-static void uart_update_status(struct xlx_uartlite *s)
+static void uart_update_status(XilinxUARTLite *s)
{
uint32_t r;
static uint64_t
uart_read(void *opaque, hwaddr addr, unsigned int size)
{
- struct xlx_uartlite *s = opaque;
+ XilinxUARTLite *s = opaque;
uint32_t r = 0;
addr >>= 2;
switch (addr)
uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
- struct xlx_uartlite *s = opaque;
+ XilinxUARTLite *s = opaque;
uint32_t value = val64;
unsigned char ch = value;
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
- struct xlx_uartlite *s = opaque;
+ XilinxUARTLite *s = opaque;
/* Got a byte. */
if (s->rx_fifo_len >= 8) {
static int uart_can_rx(void *opaque)
{
- struct xlx_uartlite *s = opaque;
+ XilinxUARTLite *s = opaque;
return s->rx_fifo_len < sizeof(s->rx_fifo);
}
static int xilinx_uartlite_init(SysBusDevice *dev)
{
- struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
+ XilinxUARTLite *s = FROM_SYSBUS(typeof (*s), dev);
sysbus_init_irq(dev, &s->irq);
static const TypeInfo xilinx_uartlite_info = {
.name = "xlnx.xps-uartlite",
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof (struct xlx_uartlite),
+ .instance_size = sizeof(XilinxUARTLite),
.class_init = xilinx_uartlite_class_init,
};