This removes another use of 'long' to mean xlen from builtins.
I've also converted the types to unsigned as proposed in D154616.
clmul_32 is available to RV64 as its emulation is clmul+sext.w
clmulh_32 and clmulr_32 are not available on RV64 as their emulation
is currently 6 instructions in the worst case.
TARGET_BUILTIN(__builtin_riscv_ctz_64, "UiUWi", "nc", "zbb,64bit")
// Zbc or Zbkc extension
-TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")
-TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc")
-TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc")
+TARGET_BUILTIN(__builtin_riscv_clmul_32, "UiUiUi", "nc", "zbc|zbkc")
+TARGET_BUILTIN(__builtin_riscv_clmul_64, "UWiUWiUWi", "nc", "zbc|zbkc,64bit")
+TARGET_BUILTIN(__builtin_riscv_clmulh_32, "UiUiUi", "nc", "zbc|zbkc,32bit")
+TARGET_BUILTIN(__builtin_riscv_clmulh_64, "UWiUWiUWi", "nc", "zbc|zbkc,64bit")
+TARGET_BUILTIN(__builtin_riscv_clmulr_32, "UiUiUi", "nc", "zbc,32bit")
+TARGET_BUILTIN(__builtin_riscv_clmulr_64, "UWiUWiUWi", "nc", "zbc,64bit")
// Zbkx
TARGET_BUILTIN(__builtin_riscv_xperm4_32, "iii", "nc", "zbkx,32bit")
case RISCV::BI__builtin_riscv_clz_64:
case RISCV::BI__builtin_riscv_ctz_32:
case RISCV::BI__builtin_riscv_ctz_64:
- case RISCV::BI__builtin_riscv_clmul:
- case RISCV::BI__builtin_riscv_clmulh:
- case RISCV::BI__builtin_riscv_clmulr:
+ case RISCV::BI__builtin_riscv_clmul_32:
+ case RISCV::BI__builtin_riscv_clmul_64:
+ case RISCV::BI__builtin_riscv_clmulh_32:
+ case RISCV::BI__builtin_riscv_clmulh_64:
+ case RISCV::BI__builtin_riscv_clmulr_32:
+ case RISCV::BI__builtin_riscv_clmulr_64:
case RISCV::BI__builtin_riscv_xperm4_32:
case RISCV::BI__builtin_riscv_xperm4_64:
case RISCV::BI__builtin_riscv_xperm8_32:
}
// Zbc
- case RISCV::BI__builtin_riscv_clmul:
+ case RISCV::BI__builtin_riscv_clmul_32:
+ case RISCV::BI__builtin_riscv_clmul_64:
ID = Intrinsic::riscv_clmul;
break;
- case RISCV::BI__builtin_riscv_clmulh:
+ case RISCV::BI__builtin_riscv_clmulh_32:
+ case RISCV::BI__builtin_riscv_clmulh_64:
ID = Intrinsic::riscv_clmulh;
break;
- case RISCV::BI__builtin_riscv_clmulr:
+ case RISCV::BI__builtin_riscv_clmulr_32:
+ case RISCV::BI__builtin_riscv_clmulr_64:
ID = Intrinsic::riscv_clmulr;
break;
// RUN: %clang_cc1 -triple riscv32 -target-feature +zbc -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV32ZBC
-// RV32ZBC-LABEL: @clmul(
+#include <stdint.h>
+
+// RV32ZBC-LABEL: @clmul_32(
// RV32ZBC-NEXT: entry:
// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBC-NEXT: ret i32 [[TMP2]]
//
-long clmul(long a, long b) {
- return __builtin_riscv_clmul(a, b);
+uint32_t clmul_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmul_32(a, b);
}
-// RV32ZBC-LABEL: @clmulh(
+// RV32ZBC-LABEL: @clmulh_32(
// RV32ZBC-NEXT: entry:
// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBC-NEXT: ret i32 [[TMP2]]
//
-long clmulh(long a, long b) {
- return __builtin_riscv_clmulh(a, b);
+uint32_t clmulh_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmulh_32(a, b);
}
-// RV32ZBC-LABEL: @clmulr(
+// RV32ZBC-LABEL: @clmulr_32(
// RV32ZBC-NEXT: entry:
// RV32ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// RV32ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBC-NEXT: ret i32 [[TMP2]]
//
-long clmulr(long a, long b) {
- return __builtin_riscv_clmulr(a, b);
+uint32_t clmulr_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmulr_32(a, b);
}
// RUN: %clang_cc1 -triple riscv32 -target-feature +zbkc -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV32ZBKC
-// RV32ZBKC-LABEL: @clmul(
+#include <stdint.h>
+
+// RV32ZBKC-LABEL: @clmul_32(
// RV32ZBKC-NEXT: entry:
// RV32ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// RV32ZBKC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBKC-NEXT: ret i32 [[TMP2]]
//
-long clmul(long a, long b) {
- return __builtin_riscv_clmul(a, b);
+uint32_t clmul_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmul_32(a, b);
}
-// RV32ZBKC-LABEL: @clmulh(
+// RV32ZBKC-LABEL: @clmulh_32(
// RV32ZBKC-NEXT: entry:
// RV32ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// RV32ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// RV32ZBKC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[TMP0]], i32 [[TMP1]])
// RV32ZBKC-NEXT: ret i32 [[TMP2]]
//
-long clmulh(long a, long b) {
- return __builtin_riscv_clmulh(a, b);
+uint32_t clmulh_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmulh_32(a, b);
}
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbc -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZBC
-// RV64ZBC-LABEL: @clmul(
+#include <stdint.h>
+
+// RV64ZBC-LABEL: @clmul_64(
// RV64ZBC-NEXT: entry:
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBC-NEXT: ret i64 [[TMP2]]
//
-long clmul(long a, long b) {
- return __builtin_riscv_clmul(a, b);
+uint64_t clmul_64(uint64_t a, uint64_t b) {
+ return __builtin_riscv_clmul_64(a, b);
}
-// RV64ZBC-LABEL: @clmulh(
+// RV64ZBC-LABEL: @clmulh_64(
// RV64ZBC-NEXT: entry:
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBC-NEXT: ret i64 [[TMP2]]
//
-long clmulh(long a, long b) {
- return __builtin_riscv_clmulh(a, b);
+uint64_t clmulh_64(uint64_t a, uint64_t b) {
+ return __builtin_riscv_clmulh_64(a, b);
}
-// RV64ZBC-LABEL: @clmulr(
+// RV64ZBC-LABEL: @clmulr_64(
// RV64ZBC-NEXT: entry:
// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// RV64ZBC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulr.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBC-NEXT: ret i64 [[TMP2]]
//
-long clmulr(long a, long b) {
- return __builtin_riscv_clmulr(a, b);
+uint64_t clmulr_64(uint64_t a, uint64_t b) {
+ return __builtin_riscv_clmulr_64(a, b);
+}
+
+// RV64ZBC-LABEL: @clmul_32(
+// RV64ZBC-NEXT: entry:
+// RV64ZBC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV64ZBC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// RV64ZBC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBC-NEXT: ret i32 [[TMP2]]
+//
+uint32_t clmul_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmul_32(a, b);
}
+
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkc -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZBKC
-// RV64ZBKC-LABEL: @clmul(
+#include <stdint.h>
+
+// RV64ZBKC-LABEL: @clmul_64(
// RV64ZBKC-NEXT: entry:
// RV64ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmul.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBKC-NEXT: ret i64 [[TMP2]]
//
-long clmul(long a, long b) {
- return __builtin_riscv_clmul(a, b);
+uint64_t clmul_64(uint64_t a, uint64_t b) {
+ return __builtin_riscv_clmul_64(a, b);
}
-// RV64ZBKC-LABEL: @clmulh(
+// RV64ZBKC-LABEL: @clmulh_64(
// RV64ZBKC-NEXT: entry:
// RV64ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKC-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBKC-NEXT: ret i64 [[TMP2]]
//
-long clmulh(long a, long b) {
- return __builtin_riscv_clmulh(a, b);
+uint64_t clmulh_64(uint64_t a, uint64_t b) {
+ return __builtin_riscv_clmulh_64(a, b);
+}
+
+// RV64ZBKC-LABEL: @clmul_32(
+// RV64ZBKC-NEXT: entry:
+// RV64ZBKC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKC-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKC-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBKC-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV64ZBKC-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBKC-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// RV64ZBKC-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.clmul.i32(i32 [[TMP0]], i32 [[TMP1]])
+// RV64ZBKC-NEXT: ret i32 [[TMP2]]
+//
+uint32_t clmul_32(uint32_t a, uint32_t b) {
+ return __builtin_riscv_clmul_32(a, b);
}