drm/exynos/hdmi: fix PLL for 27MHz settings

Current settings for 27MHz and 27.027MHz do not work. Use the settings from
vendor code instead.

Change-Id: I701555eff3fca430736664e0f628fc50d9a6dc4f
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 206d94566e4772c8967a5c7736b5407aa9b9b5c5..f3e3cd728f2a19d48d9e48ff890163214a1c3827 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -527,9 +527,9 @@ static const struct hdmiphy_config hdmiphy_5430_configs[] = {
        {
                .pixel_clock = 27000000,
                .conf = {
-                       0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46,
-                       0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
-                       0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
+                       0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
+                       0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
+                       0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
                        0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
                },
        },
@@ -537,9 +537,9 @@ static const struct hdmiphy_config hdmiphy_5430_configs[] = {
                .pixel_clock = 27027000,
                .conf = {
                        0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
-                       0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5,
-                       0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
-                       0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
+                       0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
+                       0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
+                       0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
                },
        },
        {