Add the missing 3D pipeline command for rendering on BDW

Signed-off-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

diff --git a/src/i965_defines.h b/src/i965_defines.h
index 52ae85f..5b4a076 100755 (executable)
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -178,6 +178,10 @@
 #define GEN6_3DSTATE_CONSTANT_GS               CMD(3, 0, 0x16)
 #define GEN6_3DSTATE_CONSTANT_PS               CMD(3, 0, 0x17)
 
+/* Gen8 WM_HZ_OP */
+#define GEN8_3DSTATE_WM_HZ_OP                  CMD(3, 0, 0x52)
+
+
 # define GEN6_3DSTATE_CONSTANT_BUFFER_3_ENABLE  (1 << 15)
 # define GEN6_3DSTATE_CONSTANT_BUFFER_2_ENABLE  (1 << 14)
 # define GEN6_3DSTATE_CONSTANT_BUFFER_1_ENABLE  (1 << 13)
@@ -212,6 +216,10 @@
 
 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS     CMD(3, 1, 0x12)
 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS     CMD(3, 1, 0x16)
+
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS     CMD(3, 1, 0x14)
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS     CMD(3, 1, 0x13)
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS     CMD(3, 1, 0x15)
 /* DW1 */
 # define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16
 # define GEN8_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT        16
@@ -316,6 +324,8 @@
 #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS          CMD(3, 0, 0x2b)
 #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS          CMD(3, 0, 0x2e)
 #define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS          CMD(3, 0, 0x2f)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS          CMD(3, 0, 0x2c)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS          CMD(3, 0, 0x2d)
 
 #define MFX(pipeline, op, sub_opa, sub_opb)     \
     (3 << 29 |                                  \

diff --git a/src/i965_render.c b/src/i965_render.c
index 7e438c5..a48acc9 100644 (file)
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -3487,6 +3487,17 @@ gen8_emit_vs_state(VADriverContextP ctx)
     OUT_BATCH(batch, 0); /* pass-through */
     OUT_BATCH(batch, 0);
     ADVANCE_BATCH(batch);
+
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
 }
 
 /*
@@ -3505,10 +3516,31 @@ gen8_emit_urb(VADriverContextP ctx)
     /* The minimum urb entries is 64 */
 
     BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
+    /* Size is 8Kbs and base address is 0Kb */
+    BEGIN_BATCH(batch, 2);
     OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
     /* Size is 8Kbs and base address is 0Kb */
     OUT_BATCH(batch,
-               (0 << GEN8_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT) |
+               (1 << GEN8_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT) |
                (4 << GEN8_PUSH_CONSTANT_BUFFER_SIZE_SHIFT));
     ADVANCE_BATCH(batch);
 
@@ -3584,6 +3616,11 @@ gen8_emit_bypass_state(VADriverContextP ctx)
     OUT_BATCH(batch, 0);
     ADVANCE_BATCH(batch);
 
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
     /* disable HS */
     BEGIN_BATCH(batch, 11);
     OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (11 - 2));
@@ -3619,6 +3656,11 @@ gen8_emit_bypass_state(VADriverContextP ctx)
     OUT_BATCH(batch, 0);
     ADVANCE_BATCH(batch);
 
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
     /* Disable TE */
     BEGIN_BATCH(batch, 4);
     OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
@@ -3663,6 +3705,11 @@ gen8_emit_bypass_state(VADriverContextP ctx)
     OUT_BATCH(batch, 0);
     ADVANCE_BATCH(batch);
 
+    BEGIN_BATCH(batch, 2);
+    OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS | (2 - 2));
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+
     /* Disable STREAMOUT */
     BEGIN_BATCH(batch, 5);
     OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (5 - 2));
@@ -3936,6 +3983,21 @@ gen8_emit_depth_stencil_state(VADriverContextP ctx)
 }
 
 static void
+gen8_emit_wm_hz_op(VADriverContextP ctx)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    struct intel_batchbuffer *batch = i965->batch;
+
+    BEGIN_BATCH(batch, 5);
+    OUT_BATCH(batch, GEN8_3DSTATE_WM_HZ_OP | (5 - 2));
+    OUT_BATCH(batch, 0);
+    OUT_BATCH(batch, 0);
+    OUT_BATCH(batch, 0);
+    OUT_BATCH(batch, 0);
+    ADVANCE_BATCH(batch);
+}
+
+static void
 gen8_render_emit_states(VADriverContextP ctx, int kernel)
 {
     struct i965_driver_data *i965 = i965_driver_data(ctx);
@@ -3949,6 +4011,7 @@ gen8_render_emit_states(VADriverContextP ctx, int kernel)
     gen8_emit_urb(ctx);
     gen8_emit_cc_state_pointers(ctx);
     gen7_emit_sampler_state_pointers(ctx);
+    gen8_emit_wm_hz_op(ctx);
     gen8_emit_bypass_state(ctx);
     gen8_emit_vs_state(ctx);
     gen8_emit_clip_state(ctx);