freedreno/ir3: Scalarize load_ssbo

The benefits of turning it into isam (which needs to be scalar as the
SSBO is sampled as a single component R32 texture) outweigh the benefits
of vectorizing.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20975>

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 1830fd2..dd9cc08 100644 (file)
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -39,6 +39,14 @@ ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
 {
    unsigned byte_size = bit_size / 8;
 
+   /* Don't vectorize load_ssbo's that we could otherwise lower to isam,
+    * as the tex cache benefit outweighs the benefit of vectorizing
+    */
+   if ((low->intrinsic == nir_intrinsic_load_ssbo) &&
+       (nir_intrinsic_access(low) & ACCESS_CAN_REORDER)) {
+      return false;
+   }
+
    if (low->intrinsic != nir_intrinsic_load_ubo) {
       return bit_size <= 32 && align_mul >= byte_size &&
          align_offset % byte_size == 0 &&
@@ -628,6 +636,8 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
 
    bool progress = false;
 
+   NIR_PASS_V(s, nir_lower_io_to_scalar, nir_var_mem_ssbo);
+
    if (so->key.has_gs || so->key.tessellation) {
       switch (so->type) {
       case MESA_SHADER_VERTEX: