* @nic: pointer to the nic data
* @hw_params: see struct iwl_hw_params
* @lock: protect general shared data
- * @wait_command_queue: the wait_queue for SYNC host command nad uCode load
+ * @wait_command_queue: the wait_queue for SYNC host commands
* @eeprom: pointer to the eeprom/OTP image
* @ucode_type: indicator of loaded ucode image
* @device_pointers: pointers to ucode event tables
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/skbuff.h>
+#include <linux/wait.h>
#include <linux/pci.h>
#include "iwl-fh.h"
* queue_stop_count: tracks what SW queue is stopped
* @pci_dev: basic pci-network driver stuff
* @hw_base: pci hardware address support
+ * @ucode_write_complete: indicates that the ucode has been copied.
+ * @ucode_write_waitq: wait queue for uCode load
*/
struct iwl_trans_pcie {
struct iwl_rx_queue rxq;
/* PCI bus related data */
struct pci_dev *pci_dev;
void __iomem *hw_base;
+
+ bool ucode_write_complete;
+ wait_queue_head_t ucode_write_waitq;
};
#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
isr_stats->tx++;
handled |= CSR_INT_BIT_FH_TX;
/* Wake up uCode load routine, now that load is complete */
- trans->ucode_write_complete = 1;
- wake_up(&trans->shrd->wait_command_queue);
+ trans_pcie->ucode_write_complete = true;
+ wake_up(&trans_pcie->ucode_write_waitq);
}
if (inta & ~handled) {
static int iwl_load_section(struct iwl_trans *trans, const char *name,
const struct fw_desc *image, u32 dst_addr)
{
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
dma_addr_t phy_addr = image->p_addr;
u32 byte_cnt = image->len;
int ret;
- trans->ucode_write_complete = 0;
+ trans_pcie->ucode_write_complete = false;
iwl_write_direct32(trans,
FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
- ret = wait_event_timeout(trans->shrd->wait_command_queue,
- trans->ucode_write_complete, 5 * HZ);
+ ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
+ trans_pcie->ucode_write_complete, 5 * HZ);
if (!ret) {
IWL_ERR(trans, "Could not load the %s uCode section\n",
name);
trans->shrd = shrd;
trans_pcie->trans = trans;
spin_lock_init(&trans_pcie->irq_lock);
+ init_waitqueue_head(&trans_pcie->ucode_write_waitq);
/* W/A - seems to solve weird behavior. We need to remove this if we
* don't want to stay in L1 all the time. This wastes a lot of power */
* @hw_id: a u32 with the ID of the device / subdevice.
* Set during transport allocation.
* @hw_id_str: a string with info about HW ID. Set during transport allocation.
- * @ucode_write_complete: indicates that the ucode has been copied.
* @nvm_device_type: indicates OTP or eeprom
* @pm_support: set to true in start_hw if link pm is supported
*/
u32 hw_id;
char hw_id_str[52];
- u8 ucode_write_complete;
-
int nvm_device_type;
bool pm_support;