arm64: dts: ti: k3-am64-main: Add epwm nodes

Add DT nodes for all epwm instances present in AM64 SoC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20210721113625.17299-2-lokeshvutla@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 02c3fdf..9e762f6 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -217,6 +217,12 @@
                        reg = <0x4044 0x8>;
                        #phy-cells = <1>;
                };
+
+               epwm_tbclk: clock@4140 {
+                       compatible = "ti,am64-epwm-tbclk", "syscon";
+                       reg = <0x4130 0x4>;
+                       #clock-cells = <1>;
+               };
        };
 
        main_uart0: serial@2800000 {
@@ -859,4 +865,85 @@
                clock-names = "fck";
                max-functions = /bits/ 8 <1>;
        };
+
+       epwm0: pwm@23000000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23000000 0x0 0x100>;
+               power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
+               clock-names = "tbclk", "fck";
+       };
+
+       epwm1: pwm@23010000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23010000 0x0 0x100>;
+               power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
+               clock-names = "tbclk", "fck";
+       };
+
+       epwm2: pwm@23020000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23020000 0x0 0x100>;
+               power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
+               clock-names = "tbclk", "fck";
+       };
+
+       epwm3: pwm@23030000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23030000 0x0 0x100>;
+               power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
+               clock-names = "tbclk", "fck";
+       };
+
+       epwm4: pwm@23040000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23040000 0x0 0x100>;
+               power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
+               clock-names = "tbclk", "fck";
+       };
+
+       epwm5: pwm@23050000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23050000 0x0 0x100>;
+               power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
+               clock-names = "tbclk", "fck";
+       };
+
+       epwm6: pwm@23060000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23060000 0x0 0x100>;
+               power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
+               clock-names = "tbclk", "fck";
+       };
+
+       epwm7: pwm@23070000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23070000 0x0 0x100>;
+               power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
+               clock-names = "tbclk", "fck";
+       };
+
+       epwm8: pwm@23080000 {
+               compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+               #pwm-cells = <3>;
+               reg = <0x0 0x23080000 0x0 0x100>;
+               power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
+               clock-names = "tbclk", "fck";
+       };
 };