PD#SWPL-11266
Problem:
the emmc clock source is 792M, the emmc speed
should be 198M
Solution:
modify dts from 200M to 198M
Verify:
passed on tl1_t962x2_x301
Change-Id: I9baf345db06039c5df8f5b7714a8fbb6e0143b68
Signed-off-by: Ruixuan Li <ruixuan.li@amlogic.com>
"MMC_CAP_CMD23";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
- f_max = <200000000>;
+ f_max = <198000000>;
};
};
"MMC_CAP_DRIVER_TYPE_D";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
- f_max = <200000000>;
+ f_max = <198000000>;
};
};
"MMC_CAP_DRIVER_TYPE_D";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
- f_max = <200000000>;
+ f_max = <198000000>;
};
};
"MMC_CAP_DRIVER_TYPE_D";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
- f_max = <200000000>;
+ f_max = <198000000>;
};
};
"MMC_CAP_DRIVER_TYPE_D";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
- f_max = <200000000>;
+ f_max = <198000000>;
};
};
"MMC_CAP_DRIVER_TYPE_D";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
- f_max = <200000000>;
+ f_max = <198000000>;
};
};
"MMC_CAP_DRIVER_TYPE_D";
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
- f_max = <200000000>;
+ f_max = <198000000>;
};
};