arm64: zynqmp: Describe TI phy as ethernet-phy-id
authorMichal Simek <michal.simek@amd.com>
Fri, 9 Sep 2022 11:05:48 +0000 (13:05 +0200)
committerMichal Simek <michal.simek@amd.com>
Wed, 21 Sep 2022 07:55:19 +0000 (09:55 +0200)
TI DP83867 is using strapping based on MIO pins. Tristate setup can influce
PHY address. That's why switch description with ethernet-phy-id compatible
string which enable calling reset. PHY itself setups phy address after
power up or reset. Reset description will be added in separate commit.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/52bf9ac0453d4e4896d8edd2618e684bb1ff6012.1662721547.git.michal.simek@amd.com
arch/arm/dts/zynqmp-zcu102-revA.dts
arch/arm/dts/zynqmp-zcu104-revA.dts
arch/arm/dts/zynqmp-zcu104-revC.dts
arch/arm/dts/zynqmp-zcu111-revA.dts
arch/arm/dts/zynqmp-zcu208-revA.dts
arch/arm/dts/zynqmp-zcu216-revA.dts

index a4e92c8..8d8f495 100644 (file)
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@21 {
-               reg = <21>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
-               /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@21 {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <21>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+                       /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+               };
        };
 };
 
index 1418cff..6df9a13 100644 (file)
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+               };
        };
 };
 
index 7fd19ca..0721516 100644 (file)
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+               };
        };
 };
 
index e412992..c37c4b8 100644 (file)
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+               };
        };
 };
 
index c5cdd58..3e8ee42 100644 (file)
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+               };
        };
 };
 
index caae169..80e7ddb 100644 (file)
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+               };
        };
 };
-
 &gpio {
        status = "okay";
        gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */