KVM: arm64: Don't print warning when trapping SPE registers

KVM sets up MDCR_EL2 to trap accesses to the SPE buffer and sampling
control registers and it relies on the fact that KVM injects an undefined
exception for unknown registers. This mechanism of injecting undefined
exceptions also prints a warning message for the host kernel; for example,
when a guest tries to access PMSIDR_EL1:

[    2.691830] kvm [142]: Unsupported guest sys_reg access at: 80009e78 [800003c5]
[    2.691830]  { Op0( 3), Op1( 0), CRn( 9), CRm( 9), Op2( 7), func_read },

This is unnecessary, because KVM has explicitly configured trapping of
those registers and is well aware of their existence. Prevent the warning
by adding the SPE registers to the list of registers that KVM emulates.
The access function will inject the undefined exception.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210409152154.198566-2-alexandru.elisei@arm.com

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d4a5fca..43bca83 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -283,6 +283,8 @@
 #define SYS_PMSIRR_EL1_INTERVAL_MASK   0xffffffUL
 
 /* Filtering controls */
+#define SYS_PMSNEVFR_EL1               sys_reg(3, 0, 9, 9, 1)
+
 #define SYS_PMSFCR_EL1                 sys_reg(3, 0, 9, 9, 4)
 #define SYS_PMSFCR_EL1_FE_SHIFT                0
 #define SYS_PMSFCR_EL1_FT_SHIFT                1

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 4f2f1e3..402cd11 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1501,6 +1501,19 @@ static const struct sys_reg_desc sys_reg_descs[] = {
        { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
        { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
 
+       { SYS_DESC(SYS_PMSCR_EL1), undef_access },
+       { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
+       { SYS_DESC(SYS_PMSICR_EL1), undef_access },
+       { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
+       { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
+       { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
+       { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
+       { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
+       { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
+       { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
+       { SYS_DESC(SYS_PMBSR_EL1), undef_access },
+       /* PMBIDR_EL1 is not trapped */
+
        { PMU_SYS_REG(SYS_PMINTENSET_EL1),
          .access = access_pminten, .reg = PMINTENSET_EL1 },
        { PMU_SYS_REG(SYS_PMINTENCLR_EL1),