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drm/nv50: fix alignment of per-channel fifo cache
author
Ben Skeggs
<bskeggs@redhat.com>
Sun, 17 Jan 2010 22:33:04 +0000
(08:33 +1000)
committer
Ben Skeggs
<bskeggs@redhat.com>
Sun, 17 Jan 2010 23:56:19 +0000
(09:56 +1000)
GPU pointer to the structure is shifted right by 10 bits, so we need to
align to 1024 bytes, not 256.
Reported-by: Maarten Maathuis <madman2003@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nv50_fifo.c
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diff --git
a/drivers/gpu/drm/nouveau/nv50_fifo.c
b/drivers/gpu/drm/nouveau/nv50_fifo.c
index
39caf16
..
32b244b
100644
(file)
--- a/
drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/
drivers/gpu/drm/nouveau/nv50_fifo.c
@@
-272,7
+272,7
@@
nv50_fifo_create_context(struct nouveau_channel *chan)
return ret;
ramfc = chan->ramfc->gpuobj;
- ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096,
256
,
+ ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096,
1024
,
0, &chan->cache);
if (ret)
return ret;