; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_movk_i32 s3, 0x7f
; GFX6-NEXT: s_and_b32 s2, s2, s3
-; GFX6-NEXT: s_and_b32 s1, s1, s3
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x60001
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_lshr_b32 s1, s1, 1
; GFX6-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 6
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX6-NEXT: v_mov_b32_e32 v4, 0x7f
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX6-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 7, v2
define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX6-LABEL: s_fshl_i8:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xff
; GFX6-NEXT: s_and_b32 s3, s2, 7
; GFX6-NEXT: s_andn2_b32 s2, 7, s2
-; GFX6-NEXT: s_lshr_b32 s1, s1, 1
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX6-NEXT: s_lshl_b32 s0, s0, s3
; GFX6-NEXT: s_lshr_b32 s1, s1, s2
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_and_b32_e32 v3, 7, v2
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_fshl_i8_4:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xff
; GFX6-NEXT: s_lshl_b32 s0, s0, 4
-; GFX6-NEXT: s_lshr_b32 s1, s1, 4
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x40004
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX6-LABEL: v_fshl_i8_4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 4, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_fshl_i8_5:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xff
; GFX6-NEXT: s_lshl_b32 s0, s0, 5
-; GFX6-NEXT: s_lshr_b32 s1, s1, 3
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x50003
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX6-LABEL: v_fshl_i8_5:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 3, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 3, 5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-LABEL: s_fshl_v2i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s5, s2, 7
-; GFX6-NEXT: s_movk_i32 s6, 0xff
; GFX6-NEXT: s_lshr_b32 s3, s0, 8
-; GFX6-NEXT: s_lshl_b32 s0, s0, s5
-; GFX6-NEXT: s_and_b32 s5, s1, s6
; GFX6-NEXT: s_lshr_b32 s4, s2, 8
; GFX6-NEXT: s_andn2_b32 s2, 7, s2
-; GFX6-NEXT: s_lshr_b32 s5, s5, 1
+; GFX6-NEXT: s_lshl_b32 s0, s0, s5
+; GFX6-NEXT: s_bfe_u32 s5, s1, 0x70001
; GFX6-NEXT: s_lshr_b32 s2, s5, s2
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x80008
; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, 1
; GFX6-NEXT: s_lshl_b32 s2, s3, s2
; GFX6-NEXT: s_lshr_b32 s1, s1, s4
+; GFX6-NEXT: s_movk_i32 s6, 0xff
; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: s_and_b32 s1, s1, s6
; GFX6-NEXT: s_and_b32 s0, s0, s6
; GFX6-LABEL: v_fshl_v2i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v5, 7, v2
-; GFX6-NEXT: s_movk_i32 s4, 0xff
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; GFX6-NEXT: v_and_b32_e32 v5, 7, v2
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, v5, v0
-; GFX6-NEXT: v_and_b32_e32 v5, s4, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX6-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, v5, v0
+; GFX6-NEXT: v_bfe_u32 v5, v1, 1, 7
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 7, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xff
+; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
+; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX6-LABEL: s_fshl_v4i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s9, s2, 7
-; GFX6-NEXT: s_movk_i32 s10, 0xff
; GFX6-NEXT: s_lshr_b32 s3, s0, 8
; GFX6-NEXT: s_lshr_b32 s4, s0, 16
; GFX6-NEXT: s_lshr_b32 s5, s0, 24
-; GFX6-NEXT: s_lshl_b32 s0, s0, s9
-; GFX6-NEXT: s_and_b32 s9, s1, s10
; GFX6-NEXT: s_lshr_b32 s6, s2, 8
; GFX6-NEXT: s_lshr_b32 s7, s2, 16
; GFX6-NEXT: s_lshr_b32 s8, s2, 24
; GFX6-NEXT: s_andn2_b32 s2, 7, s2
-; GFX6-NEXT: s_lshr_b32 s9, s9, 1
+; GFX6-NEXT: s_lshl_b32 s0, s0, s9
+; GFX6-NEXT: s_bfe_u32 s9, s1, 0x70001
; GFX6-NEXT: s_lshr_b32 s2, s9, s2
; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_and_b32 s2, s6, 7
; GFX6-NEXT: s_bfe_u32 s4, s1, 0x80010
; GFX6-NEXT: s_andn2_b32 s6, 7, s7
; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_movk_i32 s10, 0xff
; GFX6-NEXT: s_lshr_b32 s4, s4, s6
; GFX6-NEXT: s_or_b32 s3, s3, s4
; GFX6-NEXT: s_and_b32 s4, s8, 7
; GFX6-NEXT: v_lshrrev_b32_e32 v8, 24, v2
; GFX6-NEXT: v_and_b32_e32 v9, 7, v2
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX6-NEXT: v_and_b32_e32 v10, 0xff, v1
-; GFX6-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v10, 1, v10
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 7, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v9, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v10
+; GFX6-NEXT: v_bfe_u32 v9, v1, 1, 7
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v9
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 7, v6
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX6-NEXT: v_bfe_u32 v4, v1, 16, 8
; GFX6-NEXT: v_and_b32_e32 v6, 7, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
-; GFX6-NEXT: v_mov_b32_e32 v9, 0xff
+; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v6, v4
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v8
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_and_b32_e32 v4, 7, v8
; GFX6-NEXT: v_and_b32_e32 v6, 7, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 25, v1
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v6, v1
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v9
+; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v3, v9
+; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v9
+; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_and_b32 s2, s2, s3
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: s_and_b32 s1, s1, s3
-; GFX6-NEXT: s_lshr_b32 s1, s1, 1
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX6-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX8-NEXT: s_and_b32 s2, s2, s3
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: s_and_b32 s1, s1, s3
-; GFX8-NEXT: s_lshr_b32 s1, s1, 1
+; GFX8-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX8-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: s_and_b32 s2, s2, s3
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_and_b32 s1, s1, s3
-; GFX9-NEXT: s_lshr_b32 s1, s1, 1
+; GFX9-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX9-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX10-NEXT: s_mov_b32 s3, 0xffffff
+; GFX10-NEXT: s_bfe_u32 s1, s1, 0x170001
; GFX10-NEXT: s_and_b32 s2, s2, s3
-; GFX10-NEXT: s_and_b32 s1, s1, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX10-NEXT: s_lshr_b32 s1, s1, 1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_lo_u32 v1, 0xffffffe8, v0
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 23
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX6-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX6-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v2
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX8-NEXT: v_bfe_u32 v1, v1, 1, 23
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX8-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX9-NEXT: v_bfe_u32 v1, v1, 1, 23
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX9-NEXT: v_and_b32_e32 v1, v1, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX9-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v2
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX10-NEXT: v_bfe_u32 v1, v1, 1, 23
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_mul_lo_u32 v4, 0xffffffe8, v3
; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4
-; GFX10-NEXT: v_mov_b32_e32 v4, 0xffffff
; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX10-NEXT: v_and_b32_e32 v1, v1, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_mul_lo_u32 v3, v3, 24
; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v2
; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v2
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v2
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v2
-; GFX10-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX10-NEXT: v_and_b32_e32 v3, v3, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, v3, v1
+; GFX10-NEXT: v_mov_b32_e32 v3, 0xffffff
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v2
+; GFX10-NEXT: v_and_b32_e32 v2, v2, v3
+; GFX10-NEXT: v_and_b32_e32 v4, v4, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v1, v4, v1
; GFX10-NEXT: v_lshl_or_b32 v0, v0, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.fshl.i24(i24 %lhs, i24 %rhs, i24 %amt)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX6-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
-; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v9
+; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
-; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX6-NEXT: v_and_b32_e32 v5, v5, v9
; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX6-NEXT: v_mul_lo_u32 v7, v7, v8
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
+; GFX6-NEXT: v_mul_hi_u32 v7, v8, v7
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, v7, v8
-; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 23, v4
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 23, v4
; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX6-NEXT: v_mul_hi_u32 v6, v8, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_and_b32_e32 v4, v5, v9
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v6
-; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT: v_and_b32_e32 v6, v7, v9
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v6, v2
+; GFX6-NEXT: v_and_b32_e32 v4, v6, v9
+; GFX6-NEXT: v_mul_lo_u32 v6, v7, 24
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_mul_lo_u32 v5, v5, 24
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v4, v5
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v2, v3, v9
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 23
; GFX6-NEXT: v_and_b32_e32 v3, v4, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX8-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX8-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
-; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX8-NEXT: v_rcp_iflag_f32_e32 v8, v9
+; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
-; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX8-NEXT: v_and_b32_e32 v5, v5, v9
; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX8-NEXT: v_mul_lo_u32 v7, v7, v8
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
+; GFX8-NEXT: v_mul_hi_u32 v7, v8, v7
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT: v_mul_lo_u32 v6, v7, v8
-; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 23, v4
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7
+; GFX8-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 23, v4
; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX8-NEXT: v_mul_hi_u32 v6, v8, v6
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT: v_and_b32_e32 v4, v5, v9
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, v8, v6
-; GFX8-NEXT: v_mul_hi_u32 v5, v4, v5
-; GFX8-NEXT: v_and_b32_e32 v6, v7, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, v6, v2
+; GFX8-NEXT: v_and_b32_e32 v4, v6, v9
+; GFX8-NEXT: v_mul_lo_u32 v6, v7, 24
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_lo_u32 v5, v5, 24
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v4, v5
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 24, v2
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_and_b32_e32 v2, v3, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_bfe_u32 v2, v3, 1, 23
; GFX8-NEXT: v_and_b32_e32 v3, v4, v9
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX9-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
+; GFX9-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX9-NEXT: v_mul_lo_u32 v8, v7, v6
+; GFX9-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v9
; GFX9-NEXT: v_and_b32_e32 v5, v5, v9
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v8
; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v2
; GFX9-NEXT: v_mul_hi_u32 v7, v8, v7
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
-; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4
-; GFX9-NEXT: v_and_b32_e32 v6, v6, v9
+; GFX9-NEXT: v_add_u32_e32 v6, v8, v7
+; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
+; GFX9-NEXT: v_and_b32_e32 v7, v7, v9
; GFX9-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, v6, v2
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, v7, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v4, v2
-; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7
+; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT: v_subrev_u32_e32 v4, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, 23, v2
-; GFX9-NEXT: v_and_b32_e32 v3, v3, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX9-NEXT: v_and_b32_e32 v4, v4, v9
; GFX9-NEXT: v_and_b32_e32 v2, v2, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX10-NEXT: v_mov_b32_e32 v10, 0xffffff
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX10-NEXT: v_bfe_u32 v2, v2, 1, 23
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX10-NEXT: v_and_b32_e32 v5, v5, v10
-; GFX10-NEXT: v_and_b32_e32 v2, v2, v10
-; GFX10-NEXT: v_and_b32_e32 v3, v3, v10
-; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_bfe_u32 v3, v3, 1, 23
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s3, s2, 15
; GFX6-NEXT: s_andn2_b32 s2, 15, s2
-; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX6-NEXT: s_lshr_b32 s1, s1, 1
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0xf0001
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_lshl_b32 s0, s0, s3
; GFX6-NEXT: s_lshr_b32 s1, s1, s2
define amdgpu_ps i16 @s_fshl_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_fshl_i16_4:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
; GFX6-NEXT: s_lshl_b32 s0, s0, 4
-; GFX6-NEXT: s_lshr_b32 s1, s1, 12
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x4000c
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
define amdgpu_ps i16 @s_fshl_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_fshl_i16_5:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
; GFX6-NEXT: s_lshl_b32 s0, s0, 5
-; GFX6-NEXT: s_lshr_b32 s1, s1, 11
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x5000b
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX6-NEXT: v_and_b32_e32 v3, 15, v2
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX6-NEXT: v_and_b32_e32 v2, 15, v2
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_bfe_u32 v3, v3, 0, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 15
; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-LABEL: v_fshl_i16_4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 12, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 12, 4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-LABEL: v_fshl_i16_5:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 5, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 11, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 11, 5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX6: ; %bb.0:
; GFX6-NEXT: v_and_b32_e32 v1, 15, v0
; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
; GFX6-NEXT: v_and_b32_e32 v0, 15, v0
+; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1
-; GFX6-NEXT: s_and_b32 s0, s1, 0xffff
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s0, s1, 0xf0001
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s2, s1, 15
; GFX6-NEXT: s_andn2_b32 s1, 15, s1
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_bfe_u32 v0, v0, 1, 15
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: s_lshl_b32 s0, s0, s2
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s1, v0
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s2, s1, 15
; GFX6-NEXT: s_andn2_b32 s1, 15, s1
-; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s0, s0, 0xf0001
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s2, v0
; GFX6-NEXT: s_lshr_b32 s0, s0, s1
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s6, s4, 15
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX6-NEXT: s_lshl_b32 s0, s0, s6
-; GFX6-NEXT: s_mov_b32 s6, 0xffff
; GFX6-NEXT: s_andn2_b32 s4, 15, s4
-; GFX6-NEXT: s_and_b32 s2, s2, s6
-; GFX6-NEXT: s_lshr_b32 s2, s2, 1
+; GFX6-NEXT: s_lshl_b32 s0, s0, s6
+; GFX6-NEXT: s_mov_b32 s6, 0xf0001
+; GFX6-NEXT: s_bfe_u32 s2, s2, s6
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshr_b32 s2, s2, s4
; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_and_b32 s2, s5, 15
-; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_andn2_b32 s4, 15, s5
+; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_lshl_b32 s1, s1, s2
-; GFX6-NEXT: s_and_b32 s2, s3, s6
-; GFX6-NEXT: s_lshr_b32 s2, s2, 1
+; GFX6-NEXT: s_bfe_u32 s2, s3, s6
; GFX6-NEXT: s_bfe_u32 s3, s4, 0x100000
; GFX6-NEXT: s_lshr_b32 s2, s2, s3
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_and_b32_e32 v6, 15, v4
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 15
; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 15, v5
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v5
-; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 15
; GFX6-NEXT: v_bfe_u32 v3, v4, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_bfe_u32 s4, 4, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 12, v2
+; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 15
+; GFX6-NEXT: s_bfe_u32 s4, 11, 0x100000
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2
+; GFX6-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: s_bfe_u32 s5, 8, 0x100000
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, s5, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 15
+; GFX6-NEXT: s_bfe_u32 s4, 7, 0x100000
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-LABEL: v_fshl_v2i16_ssv:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_and_b32_e32 v2, 15, v0
-; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
-; GFX6-NEXT: s_mov_b32 s0, 0xffff
+; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_and_b32_e32 v0, 15, v0
-; GFX6-NEXT: s_and_b32 s2, s2, s0
-; GFX6-NEXT: s_lshr_b32 s2, s2, 1
+; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
+; GFX6-NEXT: s_mov_b32 s0, 0xf0001
+; GFX6-NEXT: s_bfe_u32 s2, s2, s0
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
; GFX6-NEXT: v_lshr_b32_e32 v0, s2, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_and_b32_e32 v2, 15, v1
; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX6-NEXT: v_and_b32_e32 v1, 15, v1
-; GFX6-NEXT: s_and_b32 s0, s3, s0
; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s0, s3, s0
; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
; GFX6-NEXT: v_lshl_b32_e32 v2, s1, v2
; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1
; GFX6-LABEL: v_fshl_v2i16_svs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s4, s2, 15
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX6-NEXT: s_lshl_b32 s0, s0, s4
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_andn2_b32 s2, 15, s2
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
+; GFX6-NEXT: v_bfe_u32 v0, v0, 1, 15
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
+; GFX6-NEXT: s_lshl_b32 s0, s0, s4
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s2, v0
; GFX6-NEXT: v_or_b32_e32 v0, s0, v0
; GFX6-NEXT: s_and_b32 s0, s3, 15
; GFX6-NEXT: s_andn2_b32 s2, 15, s3
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: s_lshl_b32 s0, s1, s0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 15
; GFX6-NEXT: s_bfe_u32 s1, s2, 0x100000
; GFX6-NEXT: v_lshrrev_b32_e32 v1, s1, v1
; GFX6-NEXT: v_or_b32_e32 v1, s0, v1
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s4, s2, 15
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_andn2_b32 s2, 15, s2
-; GFX6-NEXT: s_and_b32 s0, s0, s4
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX6-NEXT: s_mov_b32 s4, 0xf0001
+; GFX6-NEXT: s_bfe_u32 s0, s0, s4
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_lshr_b32 s0, s0, s2
; GFX6-NEXT: v_or_b32_e32 v0, s0, v0
; GFX6-NEXT: s_and_b32 s0, s3, 15
-; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: s_andn2_b32 s2, 15, s3
+; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s0, v1
-; GFX6-NEXT: s_and_b32 s0, s1, s4
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s0, s1, s4
; GFX6-NEXT: s_bfe_u32 s1, s2, 0x100000
; GFX6-NEXT: s_lshr_b32 s0, s0, s1
; GFX6-NEXT: v_or_b32_e32 v1, s0, v1
; GFX6: ; %bb.0:
; GFX6-NEXT: s_and_b32 s12, s8, 15
; GFX6-NEXT: s_bfe_u32 s12, s12, 0x100000
-; GFX6-NEXT: s_lshl_b32 s0, s0, s12
-; GFX6-NEXT: s_mov_b32 s12, 0xffff
; GFX6-NEXT: s_andn2_b32 s8, 15, s8
-; GFX6-NEXT: s_and_b32 s4, s4, s12
-; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_lshl_b32 s0, s0, s12
+; GFX6-NEXT: s_mov_b32 s12, 0xf0001
+; GFX6-NEXT: s_bfe_u32 s4, s4, s12
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: s_lshr_b32 s4, s4, s8
; GFX6-NEXT: s_or_b32 s0, s0, s4
; GFX6-NEXT: s_and_b32 s4, s9, 15
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_andn2_b32 s8, 15, s9
+; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s1, s1, s4
-; GFX6-NEXT: s_and_b32 s4, s5, s12
-; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_bfe_u32 s4, s5, s12
; GFX6-NEXT: s_bfe_u32 s5, s8, 0x100000
; GFX6-NEXT: s_lshr_b32 s4, s4, s5
; GFX6-NEXT: s_or_b32 s1, s1, s4
; GFX6-NEXT: s_and_b32 s4, s10, 15
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_andn2_b32 s5, 15, s10
+; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s2, s2, s4
-; GFX6-NEXT: s_and_b32 s4, s6, s12
-; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_bfe_u32 s4, s6, s12
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX6-NEXT: s_lshr_b32 s4, s4, s5
; GFX6-NEXT: s_or_b32 s2, s2, s4
; GFX6-NEXT: s_and_b32 s4, s11, 15
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_andn2_b32 s5, 15, s11
+; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s3, s3, s4
-; GFX6-NEXT: s_and_b32 s4, s7, s12
-; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_bfe_u32 s4, s7, s12
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX6-NEXT: s_lshr_b32 s4, s4, s5
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_and_b32_e32 v12, 15, v8
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v8, 15, v8
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_bfe_u32 v12, v12, 0, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_bfe_u32 v4, v4, 1, 15
; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v12, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-NEXT: v_and_b32_e32 v4, 15, v9
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v9
-; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_and_b32_e32 v8, 15, v8
+; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, s4, v5
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_bfe_u32 v4, v5, 1, 15
; GFX6-NEXT: v_bfe_u32 v5, v8, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v4
; GFX6-NEXT: v_and_b32_e32 v4, 15, v10
-; GFX6-NEXT: v_mov_b32_e32 v12, 0xffff
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v10
-; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_and_b32_e32 v5, 15, v5
+; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX6-NEXT: v_and_b32_e32 v4, v6, v12
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_bfe_u32 v4, v6, 1, 15
; GFX6-NEXT: v_bfe_u32 v5, v5, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_and_b32_e32 v4, 15, v11
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v11
-; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_and_b32_e32 v5, 15, v5
+; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3
-; GFX6-NEXT: v_and_b32_e32 v4, v7, v12
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_bfe_u32 v4, v7, 1, 15
; GFX6-NEXT: v_bfe_u32 v5, v5, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_fshr_i8_4:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xff
; GFX6-NEXT: s_lshl_b32 s0, s0, 4
-; GFX6-NEXT: s_lshr_b32 s1, s1, 4
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x40004
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX6-LABEL: v_fshr_i8_4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 4, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_fshr_i8_5:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xff
; GFX6-NEXT: s_lshl_b32 s0, s0, 3
-; GFX6-NEXT: s_lshr_b32 s1, s1, 5
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0x30005
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX6-LABEL: v_fshr_i8_5:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 5, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 5, 3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
define amdgpu_ps i16 @s_fshr_i16_4(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_fshr_i16_4:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
; GFX6-NEXT: s_lshl_b32 s0, s0, 12
-; GFX6-NEXT: s_lshr_b32 s1, s1, 4
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0xc0004
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
define amdgpu_ps i16 @s_fshr_i16_5(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_fshr_i16_5:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
; GFX6-NEXT: s_lshl_b32 s0, s0, 11
-; GFX6-NEXT: s_lshr_b32 s1, s1, 5
+; GFX6-NEXT: s_bfe_u32 s1, s1, 0xb0005
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX6-LABEL: v_fshr_i16_4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 12, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 4, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 4, 12
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-LABEL: v_fshr_i16_5:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 11, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 5, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 5, 11
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) {
; GFX6-LABEL: s_fshr_v2i16:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s6, 0xffff
; GFX6-NEXT: s_lshl_b32 s5, s5, 16
-; GFX6-NEXT: s_and_b32 s4, s4, s6
+; GFX6-NEXT: s_and_b32 s4, s4, 0xffff
; GFX6-NEXT: s_or_b32 s4, s5, s4
; GFX6-NEXT: s_bfe_u32 s5, 1, 0x100000
+; GFX6-NEXT: s_mov_b32 s6, 0xf0001
; GFX6-NEXT: s_lshl_b32 s0, s0, s5
-; GFX6-NEXT: s_and_b32 s7, s2, s6
+; GFX6-NEXT: s_bfe_u32 s7, s2, s6
+; GFX6-NEXT: s_bfe_u32 s8, 14, 0x100000
; GFX6-NEXT: s_lshl_b32 s1, s1, s5
-; GFX6-NEXT: s_and_b32 s5, s3, s6
-; GFX6-NEXT: s_lshr_b32 s7, s7, 15
-; GFX6-NEXT: s_lshr_b32 s5, s5, 15
-; GFX6-NEXT: s_lshl_b32 s2, s2, 1
+; GFX6-NEXT: s_bfe_u32 s5, s3, s6
+; GFX6-NEXT: s_lshr_b32 s7, s7, s8
+; GFX6-NEXT: s_lshr_b32 s5, s5, s8
; GFX6-NEXT: s_xor_b32 s4, s4, -1
; GFX6-NEXT: s_or_b32 s0, s0, s7
; GFX6-NEXT: s_or_b32 s1, s1, s5
+; GFX6-NEXT: s_lshl_b32 s2, s2, 1
; GFX6-NEXT: s_lshr_b32 s5, s4, 16
; GFX6-NEXT: s_and_b32 s7, s4, 15
; GFX6-NEXT: s_andn2_b32 s4, 15, s4
-; GFX6-NEXT: s_and_b32 s2, s2, s6
; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX6-NEXT: s_lshr_b32 s2, s2, 1
+; GFX6-NEXT: s_bfe_u32 s2, s2, s6
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s0, s0, s7
; GFX6-NEXT: s_lshr_b32 s2, s2, s4
; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_and_b32 s2, s5, 15
; GFX6-NEXT: s_lshl_b32 s3, s3, 1
-; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_andn2_b32 s4, 15, s5
+; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_lshl_b32 s1, s1, s2
-; GFX6-NEXT: s_and_b32 s2, s3, s6
-; GFX6-NEXT: s_lshr_b32 s2, s2, 1
+; GFX6-NEXT: s_bfe_u32 s2, s3, s6
; GFX6-NEXT: s_bfe_u32 s3, s4, 0x100000
; GFX6-NEXT: s_lshr_b32 s2, s2, s3
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-LABEL: v_fshr_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v6, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v6
-; GFX6-NEXT: s_mov_b32 s5, 0xffff
+; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX6-NEXT: v_or_b32_e32 v4, v5, v4
; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
-; GFX6-NEXT: v_and_b32_e32 v5, s5, v2
+; GFX6-NEXT: v_bfe_u32 v5, v2, 1, 15
+; GFX6-NEXT: s_bfe_u32 s5, 14, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, 15, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, s5, v5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v5
-; GFX6-NEXT: v_and_b32_e32 v5, s5, v3
+; GFX6-NEXT: v_bfe_u32 v5, v3, 1, 15
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, 15, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, s5, v5
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 15, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 15, v4
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX6-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v6
-; GFX6-NEXT: v_bfe_u32 v7, v7, 0, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16
+; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 15
; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, v7, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, v6, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 15, v5
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 1, v3
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v5
-; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 1, v3
; GFX6-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v2, v3, v6
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
+; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 15
; GFX6-NEXT: v_bfe_u32 v3, v4, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_bfe_u32 s4, 12, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 4, v2
+; GFX6-NEXT: v_bfe_u32 v2, v2, 1, 15
+; GFX6-NEXT: s_bfe_u32 s4, 3, 0x100000
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2
+; GFX6-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: s_bfe_u32 s5, 8, 0x100000
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, s5, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_bfe_u32 v2, v3, 1, 15
+; GFX6-NEXT: s_bfe_u32 s4, 7, 0x100000
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX6-NEXT: s_mov_b32 s5, 0xffff
+; GFX6-NEXT: s_mov_b32 s5, 0xf0001
; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
-; GFX6-NEXT: s_and_b32 s6, s2, s5
+; GFX6-NEXT: s_bfe_u32 s6, s2, s5
+; GFX6-NEXT: s_bfe_u32 s7, 14, 0x100000
; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, s4
-; GFX6-NEXT: s_lshr_b32 s6, s6, 15
+; GFX6-NEXT: s_lshr_b32 s6, s6, s7
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: v_and_b32_e32 v2, 15, v0
+; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX6-NEXT: s_or_b32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s2, s2, 1
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_and_b32_e32 v0, 15, v0
+; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
-; GFX6-NEXT: s_and_b32 s0, s2, s5
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s0, s2, s5
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
; GFX6-NEXT: s_lshl_b32 s1, s1, s4
-; GFX6-NEXT: s_and_b32 s4, s3, s5
-; GFX6-NEXT: s_lshl_b32 s3, s3, 1
+; GFX6-NEXT: s_bfe_u32 s4, s3, s5
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_and_b32_e32 v2, 15, v1
; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1
-; GFX6-NEXT: s_lshr_b32 s4, s4, 15
+; GFX6-NEXT: s_lshr_b32 s4, s4, s7
+; GFX6-NEXT: s_lshl_b32 s3, s3, 1
; GFX6-NEXT: v_and_b32_e32 v1, 15, v1
-; GFX6-NEXT: s_and_b32 s0, s3, s5
; GFX6-NEXT: s_or_b32 s1, s1, s4
; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s0, s3, s5
; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 16
; GFX6-NEXT: v_lshl_b32_e32 v2, s1, v2
; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1
define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <2 x i16> inreg %amt) {
; GFX6-LABEL: v_fshr_v2i16_svs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_and_b32 s2, s2, s4
+; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
; GFX6-NEXT: s_or_b32 s2, s3, s2
; GFX6-NEXT: s_bfe_u32 s3, 1, 0x100000
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v0
+; GFX6-NEXT: v_bfe_u32 v2, v0, 1, 15
+; GFX6-NEXT: s_bfe_u32 s4, 14, 0x100000
; GFX6-NEXT: s_lshl_b32 s0, s0, s3
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 15, v2
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_bfe_u32 v3, v1, 1, 15
; GFX6-NEXT: v_or_b32_e32 v2, s0, v2
; GFX6-NEXT: s_lshl_b32 s0, s1, s3
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 15, v3
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, s4, v3
; GFX6-NEXT: v_or_b32_e32 v3, s0, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: s_xor_b32 s0, s2, -1
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: s_and_b32 s2, s0, 15
; GFX6-NEXT: s_andn2_b32 s0, 15, s0
-; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_bfe_u32 v0, v0, 1, 15
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX6-NEXT: s_and_b32 s0, s1, 15
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, s2, v2
; GFX6-NEXT: s_andn2_b32 s1, 15, s1
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, s0, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 15
; GFX6-NEXT: s_bfe_u32 s0, s1, 0x100000
; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <2 x i16> inreg %amt) {
; GFX6-LABEL: v_fshr_v2i16_vss:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
-; GFX6-NEXT: s_and_b32 s2, s2, s4
+; GFX6-NEXT: s_and_b32 s2, s2, 0xffff
; GFX6-NEXT: s_or_b32 s2, s3, s2
; GFX6-NEXT: s_bfe_u32 s3, 1, 0x100000
+; GFX6-NEXT: s_mov_b32 s4, 0xf0001
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s3, v0
-; GFX6-NEXT: s_and_b32 s5, s0, s4
+; GFX6-NEXT: s_bfe_u32 s5, s0, s4
+; GFX6-NEXT: s_bfe_u32 s6, 14, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s3, v1
-; GFX6-NEXT: s_and_b32 s3, s1, s4
-; GFX6-NEXT: s_lshr_b32 s5, s5, 15
-; GFX6-NEXT: s_lshr_b32 s3, s3, 15
-; GFX6-NEXT: s_lshl_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s3, s1, s4
+; GFX6-NEXT: s_lshr_b32 s5, s5, s6
+; GFX6-NEXT: s_lshr_b32 s3, s3, s6
; GFX6-NEXT: s_xor_b32 s2, s2, -1
; GFX6-NEXT: v_or_b32_e32 v0, s5, v0
; GFX6-NEXT: v_or_b32_e32 v1, s3, v1
+; GFX6-NEXT: s_lshl_b32 s0, s0, 1
; GFX6-NEXT: s_lshr_b32 s3, s2, 16
; GFX6-NEXT: s_and_b32 s5, s2, 15
; GFX6-NEXT: s_andn2_b32 s2, 15, s2
-; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s0, s0, s4
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s5, v0
; GFX6-NEXT: s_lshr_b32 s0, s0, s2
; GFX6-NEXT: v_or_b32_e32 v0, s0, v0
; GFX6-NEXT: s_and_b32 s0, s3, 15
; GFX6-NEXT: s_lshl_b32 s1, s1, 1
-; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: s_andn2_b32 s2, 15, s3
+; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s0, v1
-; GFX6-NEXT: s_and_b32 s0, s1, s4
-; GFX6-NEXT: s_lshr_b32 s0, s0, 1
+; GFX6-NEXT: s_bfe_u32 s0, s1, s4
; GFX6-NEXT: s_bfe_u32 s1, s2, 0x100000
; GFX6-NEXT: s_lshr_b32 s0, s0, s1
; GFX6-NEXT: v_or_b32_e32 v1, s0, v1
; GFX6-NEXT: s_or_b32 s8, s9, s8
; GFX6-NEXT: s_lshl_b32 s9, s11, 16
; GFX6-NEXT: s_and_b32 s10, s10, s12
+; GFX6-NEXT: s_mov_b32 s11, 0xf0001
; GFX6-NEXT: s_or_b32 s9, s9, s10
; GFX6-NEXT: s_bfe_u32 s10, 1, 0x100000
-; GFX6-NEXT: s_and_b32 s11, s4, s12
+; GFX6-NEXT: s_bfe_u32 s12, s4, s11
+; GFX6-NEXT: s_bfe_u32 s13, 14, 0x100000
; GFX6-NEXT: s_lshl_b32 s0, s0, s10
-; GFX6-NEXT: s_lshr_b32 s11, s11, 15
-; GFX6-NEXT: s_or_b32 s0, s0, s11
-; GFX6-NEXT: s_and_b32 s11, s5, s12
+; GFX6-NEXT: s_lshr_b32 s12, s12, s13
+; GFX6-NEXT: s_or_b32 s0, s0, s12
+; GFX6-NEXT: s_bfe_u32 s12, s5, s11
; GFX6-NEXT: s_lshl_b32 s1, s1, s10
-; GFX6-NEXT: s_lshr_b32 s11, s11, 15
-; GFX6-NEXT: s_lshl_b32 s4, s4, 1
+; GFX6-NEXT: s_lshr_b32 s12, s12, s13
; GFX6-NEXT: s_xor_b32 s8, s8, -1
-; GFX6-NEXT: s_or_b32 s1, s1, s11
-; GFX6-NEXT: s_lshr_b32 s11, s8, 16
-; GFX6-NEXT: s_and_b32 s13, s8, 15
+; GFX6-NEXT: s_or_b32 s1, s1, s12
+; GFX6-NEXT: s_lshl_b32 s4, s4, 1
+; GFX6-NEXT: s_lshr_b32 s12, s8, 16
+; GFX6-NEXT: s_and_b32 s14, s8, 15
; GFX6-NEXT: s_andn2_b32 s8, 15, s8
-; GFX6-NEXT: s_and_b32 s4, s4, s12
-; GFX6-NEXT: s_bfe_u32 s13, s13, 0x100000
-; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_bfe_u32 s14, s14, 0x100000
+; GFX6-NEXT: s_bfe_u32 s4, s4, s11
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX6-NEXT: s_lshl_b32 s0, s0, s13
+; GFX6-NEXT: s_lshl_b32 s0, s0, s14
; GFX6-NEXT: s_lshr_b32 s4, s4, s8
; GFX6-NEXT: s_or_b32 s0, s0, s4
-; GFX6-NEXT: s_and_b32 s4, s11, 15
+; GFX6-NEXT: s_and_b32 s4, s12, 15
; GFX6-NEXT: s_lshl_b32 s5, s5, 1
+; GFX6-NEXT: s_andn2_b32 s8, 15, s12
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX6-NEXT: s_andn2_b32 s8, 15, s11
; GFX6-NEXT: s_lshl_b32 s1, s1, s4
-; GFX6-NEXT: s_and_b32 s4, s5, s12
-; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_bfe_u32 s4, s5, s11
; GFX6-NEXT: s_bfe_u32 s5, s8, 0x100000
; GFX6-NEXT: s_lshr_b32 s4, s4, s5
; GFX6-NEXT: s_or_b32 s1, s1, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, s10
-; GFX6-NEXT: s_and_b32 s2, s6, s12
-; GFX6-NEXT: s_lshr_b32 s2, s2, 15
+; GFX6-NEXT: s_bfe_u32 s2, s6, s11
+; GFX6-NEXT: s_lshr_b32 s2, s2, s13
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, s10
-; GFX6-NEXT: s_and_b32 s3, s7, s12
-; GFX6-NEXT: s_lshr_b32 s3, s3, 15
+; GFX6-NEXT: s_bfe_u32 s3, s7, s11
+; GFX6-NEXT: s_lshr_b32 s3, s3, s13
+; GFX6-NEXT: s_xor_b32 s5, s9, -1
; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s6, 1
-; GFX6-NEXT: s_xor_b32 s5, s9, -1
; GFX6-NEXT: s_lshl_b32 s4, s7, 1
; GFX6-NEXT: s_lshr_b32 s6, s5, 16
; GFX6-NEXT: s_and_b32 s7, s5, 15
; GFX6-NEXT: s_andn2_b32 s5, 15, s5
-; GFX6-NEXT: s_and_b32 s3, s3, s12
; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX6-NEXT: s_lshr_b32 s3, s3, 1
+; GFX6-NEXT: s_bfe_u32 s3, s3, s11
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX6-NEXT: s_lshl_b32 s1, s1, s7
; GFX6-NEXT: s_lshr_b32 s3, s3, s5
; GFX6-NEXT: s_or_b32 s1, s1, s3
; GFX6-NEXT: s_and_b32 s3, s6, 15
-; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX6-NEXT: s_andn2_b32 s5, 15, s6
+; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX6-NEXT: s_lshl_b32 s2, s2, s3
-; GFX6-NEXT: s_and_b32 s3, s4, s12
-; GFX6-NEXT: s_lshr_b32 s3, s3, 1
+; GFX6-NEXT: s_bfe_u32 s3, s4, s11
; GFX6-NEXT: s_bfe_u32 s4, s5, 0x100000
; GFX6-NEXT: s_lshr_b32 s3, s3, s4
; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: v_or_b32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v9, 16, v11
; GFX6-NEXT: v_and_b32_e32 v10, v10, v12
-; GFX6-NEXT: s_mov_b32 s5, 0xffff
; GFX6-NEXT: v_or_b32_e32 v9, v9, v10
; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
-; GFX6-NEXT: v_and_b32_e32 v10, s5, v4
+; GFX6-NEXT: v_bfe_u32 v10, v4, 1, 15
+; GFX6-NEXT: s_bfe_u32 s5, 14, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v10, 15, v10
+; GFX6-NEXT: v_lshrrev_b32_e32 v10, s5, v10
; GFX6-NEXT: v_or_b32_e32 v0, v0, v10
-; GFX6-NEXT: v_and_b32_e32 v10, s5, v5
+; GFX6-NEXT: v_bfe_u32 v10, v5, 1, 15
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v10, 15, v10
+; GFX6-NEXT: v_lshrrev_b32_e32 v10, s5, v10
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX6-NEXT: v_or_b32_e32 v1, v1, v10
-; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v10, 16, v8
; GFX6-NEXT: v_and_b32_e32 v11, 15, v8
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_and_b32_e32 v8, 15, v8
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v12
; GFX6-NEXT: v_bfe_u32 v11, v11, 0, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_bfe_u32 v4, v4, 1, 15
; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v11, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
; GFX6-NEXT: v_and_b32_e32 v4, 15, v10
-; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v5
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v10
-; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
+; GFX6-NEXT: v_lshlrev_b32_e32 v5, 1, v5
; GFX6-NEXT: v_and_b32_e32 v8, 15, v8
+; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
-; GFX6-NEXT: v_and_b32_e32 v4, v5, v12
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_bfe_u32 v4, v5, 1, 15
; GFX6-NEXT: v_bfe_u32 v5, v8, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX6-NEXT: v_and_b32_e32 v4, v6, v12
+; GFX6-NEXT: v_bfe_u32 v4, v6, 1, 15
; GFX6-NEXT: v_lshlrev_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 15, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, s5, v4
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_and_b32_e32 v4, v7, v12
+; GFX6-NEXT: v_bfe_u32 v4, v7, 1, 15
; GFX6-NEXT: v_lshlrev_b32_e32 v3, s4, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 15, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, s5, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v6
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v9
; GFX6-NEXT: v_and_b32_e32 v8, 15, v6
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX6-NEXT: v_and_b32_e32 v6, 15, v6
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v12
; GFX6-NEXT: v_bfe_u32 v8, v8, 0, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_bfe_u32 v4, v4, 1, 15
; GFX6-NEXT: v_bfe_u32 v6, v6, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v6, v4
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_and_b32_e32 v4, 15, v7
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v7
-; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_and_b32_e32 v6, 15, v6
+; GFX6-NEXT: v_bfe_u32 v4, v4, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3
-; GFX6-NEXT: v_and_b32_e32 v4, v5, v12
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_bfe_u32 v4, v5, 1, 15
; GFX6-NEXT: v_bfe_u32 v5, v6, 0, 16
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4