* See intel_pps_reset_all() why we need a power domain reference here.
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
- mutex_lock(&dev_priv->pps_mutex);
+ mutex_lock(&dev_priv->display.pps.mutex);
return wakeref;
}
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- mutex_unlock(&dev_priv->pps_mutex);
+ mutex_unlock(&dev_priv->display.pps.mutex);
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
return 0;
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum pipe pipe;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
struct intel_connector *connector = intel_dp->attached_connector;
int backlight_controller = connector->panel.vbt.backlight.controller;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum port port = dig_port->base.port;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* try to find a pipe with this port selected */
/* first pick one where the panel is on */
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps.pps_pipe == INVALID_PIPE)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps.pps_pipe == INVALID_PIPE)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t pp_stat_reg, pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
intel_pps_verify_state(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 control;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
i915_reg_t pp_stat_reg, pp_ctrl_reg;
bool need_to_disable = !intel_dp->pps.want_panel_vdd;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!intel_dp_is_edp(intel_dp))
return false;
u32 pp;
i915_reg_t pp_stat_reg, pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!intel_dp_is_edp(intel_dp))
return;
u32 pp;
i915_reg_t pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!intel_dp_is_edp(intel_dp))
return;
u32 pp;
i915_reg_t pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!intel_dp_is_edp(intel_dp))
return;
{
struct intel_encoder *encoder;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!edp_have_panel_vdd(intel_dp))
return;
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
* our hw here, which are all in 100usec. */
struct edp_power_seq cur, vbt, spec,
*final = &intel_dp->pps.pps_delays;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* already initialized? */
if (pps_delays_valid(final))
enum port port = dp_to_dig_port(intel_dp)->base.port;
const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
intel_pps_get_registers(intel_dp, ®s);
void intel_pps_setup(struct drm_i915_private *i915)
{
if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- i915->pps_mmio_base = PCH_PPS_BASE;
+ i915->display.pps.mmio_base = PCH_PPS_BASE;
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- i915->pps_mmio_base = VLV_PPS_BASE;
+ i915->display.pps.mmio_base = VLV_PPS_BASE;
else
- i915->pps_mmio_base = PPS_BASE;
+ i915->display.pps.mmio_base = PPS_BASE;
}
void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)