r300g: add and enable square microtiling
authorMarek Olšák <maraeo@gmail.com>
Sun, 14 Feb 2010 16:43:32 +0000 (17:43 +0100)
committerMarek Olšák <maraeo@gmail.com>
Sun, 21 Mar 2010 20:54:07 +0000 (21:54 +0100)
It requires DRM 2.1.0 (e.g. kernel 2.6.34) and is disabled on older ones.

Finally, the texture tiling implementation is now complete. Uff.

src/gallium/drivers/r300/r300_texture.c
src/gallium/drivers/r300/r300_winsys.h
src/gallium/winsys/drm/radeon/core/radeon_drm.c
src/gallium/winsys/drm/radeon/core/radeon_drm_buffer.c
src/gallium/winsys/drm/radeon/core/radeon_r300.c
src/gallium/winsys/drm/radeon/core/radeon_winsys.h

index 2fa6560..fe2ba60 100644 (file)
@@ -715,6 +715,7 @@ static void r300_setup_flags(struct r300_texture* tex)
 static void r300_setup_tiling(struct pipe_screen *screen,
                               struct r300_texture *tex)
 {
+    struct r300_winsys_screen *rws = (struct r300_winsys_screen *)screen->winsys;
     enum pipe_format format = tex->tex.format;
     boolean rv350_mode = r300_screen(screen)->caps->family >= CHIP_FAMILY_RV350;
 
@@ -734,12 +735,12 @@ static void r300_setup_tiling(struct pipe_screen *screen,
             tex->microtile = R300_BUFFER_TILED;
             break;
 
-        /* XXX Square-tiling doesn't work with kernel older than 2.6.34,
-         * XXX need to check the DRM version */
-        /*case 2:
+        case 2:
         case 8:
-            tex->microtile = R300_BUFFER_SQUARETILED;
-            break;*/
+            if (rws->get_value(rws, R300_VID_SQUARE_TILING_SUPPORT)) {
+                tex->microtile = R300_BUFFER_SQUARETILED;
+            }
+            break;
     }
 
     /* Set macrotiling. */
index 93f9dd7..acfa5db 100644 (file)
@@ -49,6 +49,7 @@ enum r300_value_id {
     R300_VID_PCI_ID,
     R300_VID_GB_PIPES,
     R300_VID_Z_PIPES,
+    R300_VID_SQUARE_TILING_SUPPORT
 };
 
 struct r300_winsys_screen {
index d70173e..7aa9c54 100644 (file)
@@ -93,6 +93,10 @@ static void do_ioctls(int fd, struct radeon_libdrm_winsys* winsys)
         exit(1);
     }
 
+    // Supported since 2.1.0.
+    winsys->squaretiling = version->version_major > 2 ||
+                           version->version_minor >= 1;
+
     info.request = RADEON_INFO_DEVICE_ID;
     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
     if (retval) {
index 0a86acc..e36bad7 100644 (file)
@@ -314,9 +314,11 @@ void radeon_drm_bufmgr_set_tiling(struct pb_buffer *_buf,
     struct radeon_drm_buffer *buf = get_drm_buffer(_buf);
     uint32_t flags = 0, old_flags, old_pitch;
     if (microtiled == R300_BUFFER_TILED)
-       flags |= RADEON_BO_FLAGS_MICRO_TILE;
+        flags |= RADEON_BO_FLAGS_MICRO_TILE;
+    else if (microtiled == R300_BUFFER_SQUARETILED)
+        flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
     if (macrotiled == R300_BUFFER_TILED)
-       flags |= RADEON_BO_FLAGS_MACRO_TILE;
+        flags |= RADEON_BO_FLAGS_MACRO_TILE;
 
     radeon_bo_get_tiling(buf->bo, &old_flags, &old_pitch);
 
index 0c0fee1..38fcf88 100644 (file)
@@ -253,6 +253,8 @@ static uint32_t radeon_get_value(struct r300_winsys_screen *rws,
        return ws->gb_pipes;
     case R300_VID_Z_PIPES:
        return ws->z_pipes;
+    case R300_VID_SQUARE_TILING_SUPPORT:
+        return ws->squaretiling;
     }
     return 0;
 }
index ad7b976..4260dba 100644 (file)
@@ -57,6 +57,9 @@ struct radeon_libdrm_winsys {
     /* VRAM size. */
     uint32_t vram_size;
 
+    /* Square tiling support. */
+    boolean squaretiling;
+
     /* DRM FD */
     int fd;