const struct pipe_clip_state *state)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct pipe_constant_buffer cb;
- if (pm4 == NULL)
+ if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
return;
- for (int i = 0; i < 6; i++) {
- si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
- fui(state->ucp[i][0]));
- si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
- fui(state->ucp[i][1]));
- si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
- fui(state->ucp[i][2]));
- si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
- fui(state->ucp[i][3]));
- }
+ sctx->clip_state.state = *state;
+ si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
cb.buffer = NULL;
cb.user_buffer = state->ucp;
cb.buffer_size = 4*4*8;
ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
pipe_resource_reference(&cb.buffer, NULL);
+}
+
+static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
- si_pm4_set_state(sctx, clip, pm4);
+ r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
+ radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
}
#define SIX_BITS 0x3F
si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config, 10);
si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
+ si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state, 2+6*4);
si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors, 16*4);
si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports, 16*8);
struct {
struct si_state_blend *blend;
struct si_pm4_state *blend_color;
- struct si_pm4_state *clip;
struct si_state_sample_mask *sample_mask;
struct si_state_rasterizer *rasterizer;
struct si_state_dsa *dsa;
struct r600_atom *db_render_state;
struct r600_atom *msaa_config;
struct r600_atom *clip_regs;
+ struct r600_atom *clip_state;
struct r600_atom *shader_userdata;
struct r600_atom *scissors;
struct r600_atom *viewports;