MPC8555CDS \
MPC8560ADS \
MPC8568MDS \
+ MPC8572DS \
PM854 \
PM856 \
sbc8540 \
MPC8568MDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
+MPC8572DS_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale
+
PM854_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
--- /dev/null
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8572ds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ }
+ if (ctrl_num == 1 && i == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS2;
+ }
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 5;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/pixis.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+long int fixed_sdram(void);
+
+int checkboard (void)
+{
+ printf ("Board: MPC8572DS, System ID: 0x%02x, "
+ "System Version: 0x%02x, FPGA Version: 0x%02x\n",
+ in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
+ in8(PIXIS_BASE + PIXIS_PVER));
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ puts("Initializing....");
+
+#ifdef CONFIG_SPD_EEPROM
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+
+ dram_size *= 0x100000;
+#else
+ dram_size = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ puts(" DDR: ");
+ return dram_size;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ uint d_init;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+
+ ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE_1;
+ ddr->sdram_mode_2 = CFG_DDR_MODE_2;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ ddr->sdram_data_init = CFG_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
+ ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+
+#if defined (CONFIG_DDR_ECC)
+ ddr->err_int_en = CFG_DDR_ERR_INT_EN;
+ ddr->err_disable = CFG_DDR_ERR_DIS;
+ ddr->err_sbe = CFG_DDR_SBE;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+ debug("DDR: memory initialized\n\n");
+ asm("sync; isync");
+ udelay(500);
+#endif
+
+ return 512 * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+int first_free_busno=0;
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+ devdisr, io_sel, host_agent);
+
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ printf (" eTSEC1 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ printf (" eTSEC2 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ printf (" eTSEC3 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
+ printf (" eTSEC4 is in sgmii mode.\n");
+
+
+#ifdef CONFIG_PCIE3
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie3_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
+ (host_agent == 5) || (host_agent == 6);
+ int pcie_configured = io_sel >= 1;
+ u32 temp32;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE3 connected to ULI as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE3_MEM_BASE,
+ CFG_PCIE3_MEM_PHYS,
+ CFG_PCIE3_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE3_IO_BASE,
+ CFG_PCIE3_IO_PHYS,
+ CFG_PCIE3_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf (" PCIE3 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ /*
+ * Activate ULI1575 legacy chip by performing a fake
+ * memory access. Needed to make ULI RTC work.
+ * Device 1d has the first on-board memory BAR.
+ */
+
+ pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
+ PCI_BASE_ADDRESS_1, &temp32);
+ if (temp32 >= CFG_PCIE3_MEM_PHYS) {
+ debug(" uli1572 read to %x\n", temp32);
+ in_be32((unsigned *)temp32);
+ }
+ } else {
+ printf (" PCIE3: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie2_hose;
+ int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
+ (host_agent == 6);
+ int pcie_configured = io_sel & 4;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE2_MEM_BASE,
+ CFG_PCIE2_MEM_PHYS,
+ CFG_PCIE2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE2_IO_BASE,
+ CFG_PCIE2_IO_PHYS,
+ CFG_PCIE2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf (" PCIE2 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ printf (" PCIE2: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+#endif
+#ifdef CONFIG_PCIE1
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 1) || (host_agent == 4) ||
+ (host_agent == 5);
+ int pcie_configured = io_sel & 6;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+ hose->first_busno=first_free_busno;
+
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf(" PCIE1 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ printf (" PCIE1: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif
+
+int board_early_init_r(void)
+{
+ unsigned int i;
+ const unsigned int flashbase = CFG_FLASH_BASE;
+ const u8 flash_esel = 2;
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Invalidate any remaining lines of the flash from caches. */
+ for (i = 0; i < 256*1024*1024; i+=32) {
+ asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i));
+ asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i));
+ }
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
+
+ return 0;
+}
+
+#ifdef CONFIG_GET_CLK_FROM_ICS307
+/* decode S[0-2] to Output Divider (OD) */
+static unsigned char ics307_S_to_OD[] = {
+ 10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/* Calculate frequency being generated by ICS307-02 clock chip based upon
+ * the control bytes being programmed into it. */
+/* XXX: This function should probably go into a common library */
+static unsigned long
+ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
+{
+ const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
+ unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
+ unsigned long RDW = cw2 & 0x7F;
+ unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
+ unsigned long freq;
+
+ /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
+
+ /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
+ * cw1: V8 V7 V6 V5 V4 V3 V2 V1
+ * cw2: V0 R6 R5 R4 R3 R2 R1 R0
+ *
+ * R6:R0 = Reference Divider Word (RDW)
+ * V8:V0 = VCO Divider Word (VDW)
+ * S2:S0 = Output Divider Select (OD)
+ * F1:F0 = Function of CLK2 Output
+ * TTL = duty cycle
+ * C1:C0 = internal load capacitance for cyrstal
+ */
+
+ /* Adding 1 to get a "nicely" rounded number, but this needs
+ * more tweaking to get a "properly" rounded number. */
+
+ freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
+
+ debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
+ freq);
+ return freq;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ return ics307_clk_freq (
+ in8(PIXIS_BASE + PIXIS_VSYSCLK0),
+ in8(PIXIS_BASE + PIXIS_VSYSCLK1),
+ in8(PIXIS_BASE + PIXIS_VSYSCLK2)
+ );
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ return ics307_clk_freq (
+ in8(PIXIS_BASE + PIXIS_VDDRCLK0),
+ in8(PIXIS_BASE + PIXIS_VDDRCLK1),
+ in8(PIXIS_BASE + PIXIS_VDDRCLK2)
+ );
+}
+#else
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ u8 i;
+ ulong val = 0;
+
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33333333;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66666666;
+ break;
+ case 4:
+ val = 83333333;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 133333333;
+ break;
+ case 7:
+ val = 166666666;
+ break;
+ }
+
+ return val;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ u8 i;
+ ulong val = 0;
+
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ i &= 0x38;
+ i >>= 3;
+
+ switch (i) {
+ case 0:
+ val = 33333333;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66666666;
+ break;
+ case 4:
+ val = 83333333;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 133333333;
+ break;
+ case 7:
+ val = 166666666;
+ break;
+ }
+ return val;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+ ulong base, size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCIE3
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci2", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS, CFG_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x40000000, CFG_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x50000000, CFG_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CFG_PCIE3_IO_PHYS, CFG_PCIE3_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
--- /dev/null
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ } :text
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) + 0x7f000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ .resetvec ADDR(.text) + 0x7fffc :
+ {
+ *(.resetvec)
+ } :text = 0xffff
+
+ . = ADDR(.text) + 0x80000;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
+#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || defined(CONFIG_MPC8572)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.
#include <asm/cpm_85xx.h>
#include <pci.h>
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
static struct pci_controller *pci_hose;
--- /dev/null
+/*
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8572ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8572 1
+#define CONFIG_MPC8572DS 1
+#define CONFIG_MP 1 /* support multiple processors */
+#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+#define CONFIG_ICS307_REFCLK_HZ 33333333 /* ICS307 clock chip ref freq */
+#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
+ from ICS307 instead of switches */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x7fffffff
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#undef CONFIG_DDR_DLL
+
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD. */
+#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
+#define CFG_DDR_CS0_BNDS 0x0000001F
+#define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
+#define CFG_DDR_TIMING_3 0x00000000
+#define CFG_DDR_TIMING_0 0x00260802
+#define CFG_DDR_TIMING_1 0x3935d322
+#define CFG_DDR_TIMING_2 0x14904cc8
+#define CFG_DDR_MODE_1 0x00480432
+#define CFG_DDR_MODE_2 0x00000000
+#define CFG_DDR_INTERVAL 0x06180100
+#define CFG_DDR_DATA_INIT 0xdeadbeef
+#define CFG_DDR_CLK_CTRL 0x03800000
+#define CFG_DDR_OCD_CTRL 0x00000000
+#define CFG_DDR_OCD_STATUS 0x00000000
+#define CFG_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
+#define CFG_DDR_CONTROL2 0x04400010
+
+#define CFG_DDR_ERR_INT_EN 0x0000000d
+#define CFG_DDR_ERR_DIS 0x00000000
+#define CFG_DDR_SBE 0x00010000
+
+/*
+ * FIXME: Not used in fixed_sdram function
+ */
+#define CFG_DDR_MODE 0x00000022
+#define CFG_DDR_CS1_BNDS 0x00000000
+#define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
+#define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
+#define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
+#define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
+ * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
+ * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
+ * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
+ * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CFG_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
+
+#define CFG_BR0_PRELIM 0xe8001001
+#define CFG_OR0_PRELIM 0xf8000ff7
+
+#define CFG_BR1_PRELIM 0xe0001001
+#define CFG_OR1_PRELIM 0xf8000ff7
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE}
+#define CFG_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+
+#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
+#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
+
+#define CFG_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */
+#define CFG_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
+
+#define PIXIS_ID 0x0 /* Board ID at offset 0 */
+#define PIXIS_VER 0x1 /* Board version at offset 1 */
+#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
+#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
+#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
+#define PIXIS_PWR 0x5 /* PIXIS Power status register */
+#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
+#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
+#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
+#define PIXIS_VCTL 0x10 /* VELA Control Register */
+#define PIXIS_VSTAT 0x11 /* VELA Status Register */
+#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
+#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
+#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
+#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
+#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
+#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
+#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
+#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
+#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
+#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
+#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
+#define PIXIS_VWATCH 0x24 /* Watchdog Register */
+#define PIXIS_LED 0x25 /* LED Register */
+
+/* old pixis referenced names */
+#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
+#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK 0xc0
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#define CFG_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/* new uImage format support */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+/* controller 3, direct to uli, tgtid 3, Base address 8000 */
+#define CFG_PCIE3_MEM_BASE 0x80000000
+#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
+#define CFG_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE3_IO_BASE 0x00000000
+#define CFG_PCIE3_IO_PHYS 0xffc00000
+#define CFG_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CFG_PCIE2_MEM_BASE 0xa0000000
+#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
+#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE2_IO_BASE 0x00000000
+#define CFG_PCIE2_IO_PHYS 0xffc10000
+#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CFG_PCIE1_MEM_BASE 0xc0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xffc20000
+#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+#if defined(CONFIG_PCI)
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET CFG_PCIE1_IO_PHYS
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x) (x)
+#define _IO_BASE 0x00000000
+#endif
+
+#ifndef CONFIG_PCI_PNP
+ #define PCI_ENET0_IOADDR CFG_PCIE3_IO_BASE
+ #define PCI_ENET0_MEMADDR CFG_PCIE3_IO_BASE
+ #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID 4
+#define CFG_SCSI_MAX_LUN 1
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
+#endif /* SCSI */
+
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC3_PHY_ADDR 2
+#define TSEC4_PHY_ADDR 3
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#if CFG_MONITOR_BASE > 0xfff80000
+#define CFG_ENV_ADDR 0xfff80000
+#else
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000)
+#endif
+#define CFG_ENV_SIZE 0x2000
+#define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_EXT2
+#endif
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
+#endif
+
+#define CONFIG_IPADDR 192.168.1.254
+
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /opt/nfsroot
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=8572ds/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=8572ds/mpc8572ds.dtb\0" \
+ "bdev=sda3\0"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+
+#endif /* __CONFIG_H */
projects / kernel / u-boot.git / commitdiff