return addr;
}
+/* returns true if access using this ASI is to have address translated by MMU
+ otherwise access is to raw physical address */
+static inline int is_translating_asi(int asi)
+{
+#ifdef TARGET_SPARC64
+ /* Ultrasparc IIi translating asi
+ - note this list is defined by cpu implementation
+ */
+ switch (asi) {
+ case 0x04 ... 0x11:
+ case 0x18 ... 0x19:
+ case 0x24 ... 0x2C:
+ case 0x70 ... 0x73:
+ case 0x78 ... 0x79:
+ case 0x80 ... 0xFF:
+ return 1;
+
+ default:
+ return 0;
+ }
+#else
+ /* TODO: check sparc32 bits */
+ return 0;
+#endif
+}
+
+static inline target_ulong asi_address_mask(CPUState *env1,
+ int asi, target_ulong addr)
+{
+ if (is_translating_asi(asi)) {
+ return address_mask(env, addr);
+ } else {
+ return addr;
+ }
+}
+
static void raise_exception(int tt)
{
env->exception_index = tt;
raise_exception(TT_PRIV_ACT);
helper_check_align(addr, size - 1);
- addr = address_mask(env, addr);
+ addr = asi_address_mask(env, asi, addr);
switch (asi) {
case 0x82: // Primary no-fault
raise_exception(TT_PRIV_ACT);
helper_check_align(addr, size - 1);
- addr = address_mask(env, addr);
+ addr = asi_address_mask(env, asi, addr);
/* Convert to little endian */
switch (asi) {
raise_exception(TT_PRIV_ACT);
helper_check_align(addr, size - 1);
+ addr = asi_address_mask(env, asi, addr);
+
switch (asi) {
case 0x82: // Primary no-fault
case 0x8a: // Primary no-fault LE
raise_exception(TT_PRIV_ACT);
helper_check_align(addr, size - 1);
+ addr = asi_address_mask(env, asi, addr);
+
/* Convert to little endian */
switch (asi) {
case 0x0c: // Nucleus Little Endian (LE)
&& !(env->hpstate & HS_PRIV)))
raise_exception(TT_PRIV_ACT);
+ addr = asi_address_mask(env, asi, addr);
+
switch (asi) {
#if !defined(CONFIG_USER_ONLY)
case 0x24: // Nucleus quad LDD 128 bit atomic
target_ulong val;
helper_check_align(addr, 3);
+ addr = asi_address_mask(env, asi, addr);
+
switch (asi) {
case 0xf0: // Block load primary
case 0xf1: // Block load secondary
target_ulong val = 0;
helper_check_align(addr, 3);
+ addr = asi_address_mask(env, asi, addr);
+
switch (asi) {
case 0xe0: // UA2007 Block commit store primary (cache flush)
case 0xe1: // UA2007 Block commit store secondary (cache flush)
CHECK_FPU_FEATURE(dc, FLOAT128);
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_ldqf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_QT0_fpr(QFPREG(rd));
TCGv_i32 r_const;
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_lddf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_DT0_fpr(DFPREG(rd));
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_stqf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}
gen_op_load_fpr_DT0(DFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_stdf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}